?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
i2c-eg20t: change timeout value 50msec to 1000msec
[zen-stable.git] / sound / pci / hda / patch_hdmi.c
blob1168ebd3fb5c9cfe3bc964b9e223f45f3513c471
1 /*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 *
10 * Authors:
11 * Wu Fengguang <wfg@linux.intel.com>
12 *
13 * Maintained by:
14 * Wu Fengguang <wfg@linux.intel.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the Free
18 * Software Foundation; either version 2 of the License, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
23 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 * for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software Foundation,
28 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/slab.h>
34 #include <linux/module.h>
35 #include <sound/core.h>
36 #include <sound/jack.h>
37 #include "hda_codec.h"
38 #include "hda_local.h"
39 #include "hda_jack.h"
40
41 static bool static_hdmi_pcm;
42 module_param(static_hdmi_pcm, bool, 0644);
43 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
44
45 /*
46 * The HDMI/DisplayPort configuration can be highly dynamic. A graphics device
47 * could support N independent pipes, each of them can be connected to one or
48 * more ports (DVI, HDMI or DisplayPort).
49 *
50 * The HDA correspondence of pipes/ports are converter/pin nodes.
51 */
52 #define MAX_HDMI_CVTS 8
53 #define MAX_HDMI_PINS 8
54
55 struct hdmi_spec_per_cvt {
56 hda_nid_t cvt_nid;
57 int assigned;
58 unsigned int channels_min;
59 unsigned int channels_max;
60 u32 rates;
61 u64 formats;
62 unsigned int maxbps;
63 };
64
65 struct hdmi_spec_per_pin {
66 hda_nid_t pin_nid;
67 int num_mux_nids;
68 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
69
70 struct hda_codec *codec;
71 struct hdmi_eld sink_eld;
72 struct delayed_work work;
73 int repoll_count;
74 };
75
76 struct hdmi_spec {
77 int num_cvts;
78 struct hdmi_spec_per_cvt cvts[MAX_HDMI_CVTS];
79
80 int num_pins;
81 struct hdmi_spec_per_pin pins[MAX_HDMI_PINS];
82 struct hda_pcm pcm_rec[MAX_HDMI_PINS];
83
84 /*
85 * Non-generic ATI/NVIDIA specific
86 */
87 struct hda_multi_out multiout;
88 const struct hda_pcm_stream *pcm_playback;
89 };
90
91
92 struct hdmi_audio_infoframe {
93 u8 type; /* 0x84 */
94 u8 ver; /* 0x01 */
95 u8 len; /* 0x0a */
96
97 u8 checksum;
98
99 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
100 u8 SS01_SF24;
101 u8 CXT04;
102 u8 CA;
103 u8 LFEPBL01_LSV36_DM_INH7;
104 };
105
106 struct dp_audio_infoframe {
107 u8 type; /* 0x84 */
108 u8 len; /* 0x1b */
109 u8 ver; /* 0x11 << 2 */
110
111 u8 CC02_CT47; /* match with HDMI infoframe from this on */
112 u8 SS01_SF24;
113 u8 CXT04;
114 u8 CA;
115 u8 LFEPBL01_LSV36_DM_INH7;
116 };
117
118 union audio_infoframe {
119 struct hdmi_audio_infoframe hdmi;
120 struct dp_audio_infoframe dp;
121 u8 bytes[0];
122 };
123
124 /*
125 * CEA speaker placement:
126 *
127 * FLH FCH FRH
128 * FLW FL FLC FC FRC FR FRW
129 *
130 * LFE
131 * TC
132 *
133 * RL RLC RC RRC RR
134 *
135 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
136 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
137 */
138 enum cea_speaker_placement {
139 FL = (1 << 0), /* Front Left */
140 FC = (1 << 1), /* Front Center */
141 FR = (1 << 2), /* Front Right */
142 FLC = (1 << 3), /* Front Left Center */
143 FRC = (1 << 4), /* Front Right Center */
144 RL = (1 << 5), /* Rear Left */
145 RC = (1 << 6), /* Rear Center */
146 RR = (1 << 7), /* Rear Right */
147 RLC = (1 << 8), /* Rear Left Center */
148 RRC = (1 << 9), /* Rear Right Center */
149 LFE = (1 << 10), /* Low Frequency Effect */
150 FLW = (1 << 11), /* Front Left Wide */
151 FRW = (1 << 12), /* Front Right Wide */
152 FLH = (1 << 13), /* Front Left High */
153 FCH = (1 << 14), /* Front Center High */
154 FRH = (1 << 15), /* Front Right High */
155 TC = (1 << 16), /* Top Center */
156 };
157
158 /*
159 * ELD SA bits in the CEA Speaker Allocation data block
160 */
161 static int eld_speaker_allocation_bits[] = {
162 [0] = FL | FR,
163 [1] = LFE,
164 [2] = FC,
165 [3] = RL | RR,
166 [4] = RC,
167 [5] = FLC | FRC,
168 [6] = RLC | RRC,
169 /* the following are not defined in ELD yet */
170 [7] = FLW | FRW,
171 [8] = FLH | FRH,
172 [9] = TC,
173 [10] = FCH,
174 };
175
176 struct cea_channel_speaker_allocation {
177 int ca_index;
178 int speakers[8];
179
180 /* derived values, just for convenience */
181 int channels;
182 int spk_mask;
183 };
184
185 /*
186 * ALSA sequence is:
187 *
188 * surround40 surround41 surround50 surround51 surround71
189 * ch0 front left = = = =
190 * ch1 front right = = = =
191 * ch2 rear left = = = =
192 * ch3 rear right = = = =
193 * ch4 LFE center center center
194 * ch5 LFE LFE
195 * ch6 side left
196 * ch7 side right
197 *
198 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
199 */
200 static int hdmi_channel_mapping[0x32][8] = {
201 /* stereo */
202 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
203 /* 2.1 */
204 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
205 /* Dolby Surround */
206 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
207 /* surround40 */
208 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
209 /* 4ch */
210 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
211 /* surround41 */
212 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
213 /* surround50 */
214 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
215 /* surround51 */
216 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
217 /* 7.1 */
218 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
219 };
220
221 /*
222 * This is an ordered list!
223 *
224 * The preceding ones have better chances to be selected by
225 * hdmi_channel_allocation().
226 */
227 static struct cea_channel_speaker_allocation channel_allocations[] = {
228 /* channel: 7 6 5 4 3 2 1 0 */
229 { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
230 /* 2.1 */
231 { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
232 /* Dolby Surround */
233 { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
234 /* surround40 */
235 { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
236 /* surround41 */
237 { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
238 /* surround50 */
239 { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
240 /* surround51 */
241 { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
242 /* 6.1 */
243 { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
244 /* surround71 */
245 { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
246
247 { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
248 { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
249 { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
250 { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
251 { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
252 { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
253 { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
254 { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
255 { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
256 { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
257 { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
258 { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
259 { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
260 { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
261 { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
262 { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
263 { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
264 { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
265 { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
266 { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
267 { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
268 { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
269 { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
270 { .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
271 { .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
272 { .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
273 { .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
274 { .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
275 { .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
276 { .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
277 { .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
278 { .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
279 { .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
280 { .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
281 { .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
282 { .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
283 { .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
284 { .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
285 { .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
286 { .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
287 { .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
288 };
289
290
291 /*
292 * HDMI routines
293 */
294
295 static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
296 {
297 int pin_idx;
298
299 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
300 if (spec->pins[pin_idx].pin_nid == pin_nid)
301 return pin_idx;
302
303 snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
304 return -EINVAL;
305 }
306
307 static int hinfo_to_pin_index(struct hdmi_spec *spec,
308 struct hda_pcm_stream *hinfo)
309 {
310 int pin_idx;
311
312 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
313 if (&spec->pcm_rec[pin_idx].stream[0] == hinfo)
314 return pin_idx;
315
316 snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
317 return -EINVAL;
318 }
319
320 static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
321 {
322 int cvt_idx;
323
324 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
325 if (spec->cvts[cvt_idx].cvt_nid == cvt_nid)
326 return cvt_idx;
327
328 snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
329 return -EINVAL;
330 }
331
332 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
333 struct snd_ctl_elem_info *uinfo)
334 {
335 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
336 struct hdmi_spec *spec;
337 int pin_idx;
338
339 spec = codec->spec;
340 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
341
342 pin_idx = kcontrol->private_value;
343 uinfo->count = spec->pins[pin_idx].sink_eld.eld_size;
344
345 return 0;
346 }
347
348 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
349 struct snd_ctl_elem_value *ucontrol)
350 {
351 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
352 struct hdmi_spec *spec;
353 int pin_idx;
354
355 spec = codec->spec;
356 pin_idx = kcontrol->private_value;
357
358 memcpy(ucontrol->value.bytes.data,
359 spec->pins[pin_idx].sink_eld.eld_buffer, ELD_MAX_SIZE);
360
361 return 0;
362 }
363
364 static struct snd_kcontrol_new eld_bytes_ctl = {
365 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
366 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
367 .name = "ELD",
368 .info = hdmi_eld_ctl_info,
369 .get = hdmi_eld_ctl_get,
370 };
371
372 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
373 int device)
374 {
375 struct snd_kcontrol *kctl;
376 struct hdmi_spec *spec = codec->spec;
377 int err;
378
379 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
380 if (!kctl)
381 return -ENOMEM;
382 kctl->private_value = pin_idx;
383 kctl->id.device = device;
384
385 err = snd_hda_ctl_add(codec, spec->pins[pin_idx].pin_nid, kctl);
386 if (err < 0)
387 return err;
388
389 return 0;
390 }
391
392 #ifdef BE_PARANOID
393 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
394 int *packet_index, int *byte_index)
395 {
396 int val;
397
398 val = snd_hda_codec_read(codec, pin_nid, 0,
399 AC_VERB_GET_HDMI_DIP_INDEX, 0);
400
401 *packet_index = val >> 5;
402 *byte_index = val & 0x1f;
403 }
404 #endif
405
406 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
407 int packet_index, int byte_index)
408 {
409 int val;
410
411 val = (packet_index << 5) | (byte_index & 0x1f);
412
413 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
414 }
415
416 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
417 unsigned char val)
418 {
419 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
420 }
421
422 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
423 {
424 /* Unmute */
425 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
426 snd_hda_codec_write(codec, pin_nid, 0,
427 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
428 /* Disable pin out until stream is active*/
429 snd_hda_codec_write(codec, pin_nid, 0,
430 AC_VERB_SET_PIN_WIDGET_CONTROL, 0);
431 }
432
433 static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
434 {
435 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
436 AC_VERB_GET_CVT_CHAN_COUNT, 0);
437 }
438
439 static void hdmi_set_channel_count(struct hda_codec *codec,
440 hda_nid_t cvt_nid, int chs)
441 {
442 if (chs != hdmi_get_channel_count(codec, cvt_nid))
443 snd_hda_codec_write(codec, cvt_nid, 0,
444 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
445 }
446
447
448 /*
449 * Channel mapping routines
450 */
451
452 /*
453 * Compute derived values in channel_allocations[].
454 */
455 static void init_channel_allocations(void)
456 {
457 int i, j;
458 struct cea_channel_speaker_allocation *p;
459
460 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
461 p = channel_allocations + i;
462 p->channels = 0;
463 p->spk_mask = 0;
464 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
465 if (p->speakers[j]) {
466 p->channels++;
467 p->spk_mask |= p->speakers[j];
468 }
469 }
470 }
471
472 /*
473 * The transformation takes two steps:
474 *
475 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
476 * spk_mask => (channel_allocations[]) => ai->CA
477 *
478 * TODO: it could select the wrong CA from multiple candidates.
479 */
480 static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
481 {
482 int i;
483 int ca = 0;
484 int spk_mask = 0;
485 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
486
487 /*
488 * CA defaults to 0 for basic stereo audio
489 */
490 if (channels <= 2)
491 return 0;
492
493 /*
494 * expand ELD's speaker allocation mask
495 *
496 * ELD tells the speaker mask in a compact(paired) form,
497 * expand ELD's notions to match the ones used by Audio InfoFrame.
498 */
499 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
500 if (eld->spk_alloc & (1 << i))
501 spk_mask |= eld_speaker_allocation_bits[i];
502 }
503
504 /* search for the first working match in the CA table */
505 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
506 if (channels == channel_allocations[i].channels &&
507 (spk_mask & channel_allocations[i].spk_mask) ==
508 channel_allocations[i].spk_mask) {
509 ca = channel_allocations[i].ca_index;
510 break;
511 }
512 }
513
514 snd_print_channel_allocation(eld->spk_alloc, buf, sizeof(buf));
515 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
516 ca, channels, buf);
517
518 return ca;
519 }
520
521 static void hdmi_debug_channel_mapping(struct hda_codec *codec,
522 hda_nid_t pin_nid)
523 {
524 #ifdef CONFIG_SND_DEBUG_VERBOSE
525 int i;
526 int slot;
527
528 for (i = 0; i < 8; i++) {
529 slot = snd_hda_codec_read(codec, pin_nid, 0,
530 AC_VERB_GET_HDMI_CHAN_SLOT, i);
531 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
532 slot >> 4, slot & 0xf);
533 }
534 #endif
535 }
536
537
538 static void hdmi_setup_channel_mapping(struct hda_codec *codec,
539 hda_nid_t pin_nid,
540 int ca)
541 {
542 int i;
543 int err;
544
545 if (hdmi_channel_mapping[ca][1] == 0) {
546 for (i = 0; i < channel_allocations[ca].channels; i++)
547 hdmi_channel_mapping[ca][i] = i | (i << 4);
548 for (; i < 8; i++)
549 hdmi_channel_mapping[ca][i] = 0xf | (i << 4);
550 }
551
552 for (i = 0; i < 8; i++) {
553 err = snd_hda_codec_write(codec, pin_nid, 0,
554 AC_VERB_SET_HDMI_CHAN_SLOT,
555 hdmi_channel_mapping[ca][i]);
556 if (err) {
557 snd_printdd(KERN_NOTICE
558 "HDMI: channel mapping failed\n");
559 break;
560 }
561 }
562
563 hdmi_debug_channel_mapping(codec, pin_nid);
564 }
565
566
567 /*
568 * Audio InfoFrame routines
569 */
570
571 /*
572 * Enable Audio InfoFrame Transmission
573 */
574 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
575 hda_nid_t pin_nid)
576 {
577 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
578 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
579 AC_DIPXMIT_BEST);
580 }
581
582 /*
583 * Disable Audio InfoFrame Transmission
584 */
585 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
586 hda_nid_t pin_nid)
587 {
588 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
589 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
590 AC_DIPXMIT_DISABLE);
591 }
592
593 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
594 {
595 #ifdef CONFIG_SND_DEBUG_VERBOSE
596 int i;
597 int size;
598
599 size = snd_hdmi_get_eld_size(codec, pin_nid);
600 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
601
602 for (i = 0; i < 8; i++) {
603 size = snd_hda_codec_read(codec, pin_nid, 0,
604 AC_VERB_GET_HDMI_DIP_SIZE, i);
605 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
606 }
607 #endif
608 }
609
610 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
611 {
612 #ifdef BE_PARANOID
613 int i, j;
614 int size;
615 int pi, bi;
616 for (i = 0; i < 8; i++) {
617 size = snd_hda_codec_read(codec, pin_nid, 0,
618 AC_VERB_GET_HDMI_DIP_SIZE, i);
619 if (size == 0)
620 continue;
621
622 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
623 for (j = 1; j < 1000; j++) {
624 hdmi_write_dip_byte(codec, pin_nid, 0x0);
625 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
626 if (pi != i)
627 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
628 bi, pi, i);
629 if (bi == 0) /* byte index wrapped around */
630 break;
631 }
632 snd_printd(KERN_INFO
633 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
634 i, size, j);
635 }
636 #endif
637 }
638
639 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
640 {
641 u8 *bytes = (u8 *)hdmi_ai;
642 u8 sum = 0;
643 int i;
644
645 hdmi_ai->checksum = 0;
646
647 for (i = 0; i < sizeof(*hdmi_ai); i++)
648 sum += bytes[i];
649
650 hdmi_ai->checksum = -sum;
651 }
652
653 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
654 hda_nid_t pin_nid,
655 u8 *dip, int size)
656 {
657 int i;
658
659 hdmi_debug_dip_size(codec, pin_nid);
660 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
661
662 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
663 for (i = 0; i < size; i++)
664 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
665 }
666
667 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
668 u8 *dip, int size)
669 {
670 u8 val;
671 int i;
672
673 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
674 != AC_DIPXMIT_BEST)
675 return false;
676
677 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
678 for (i = 0; i < size; i++) {
679 val = snd_hda_codec_read(codec, pin_nid, 0,
680 AC_VERB_GET_HDMI_DIP_DATA, 0);
681 if (val != dip[i])
682 return false;
683 }
684
685 return true;
686 }
687
688 static void hdmi_setup_audio_infoframe(struct hda_codec *codec, int pin_idx,
689 struct snd_pcm_substream *substream)
690 {
691 struct hdmi_spec *spec = codec->spec;
692 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
693 hda_nid_t pin_nid = per_pin->pin_nid;
694 int channels = substream->runtime->channels;
695 struct hdmi_eld *eld;
696 int ca;
697 union audio_infoframe ai;
698
699 eld = &spec->pins[pin_idx].sink_eld;
700 if (!eld->monitor_present)
701 return;
702
703 ca = hdmi_channel_allocation(eld, channels);
704
705 memset(&ai, 0, sizeof(ai));
706 if (eld->conn_type == 0) { /* HDMI */
707 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
708
709 hdmi_ai->type = 0x84;
710 hdmi_ai->ver = 0x01;
711 hdmi_ai->len = 0x0a;
712 hdmi_ai->CC02_CT47 = channels - 1;
713 hdmi_ai->CA = ca;
714 hdmi_checksum_audio_infoframe(hdmi_ai);
715 } else if (eld->conn_type == 1) { /* DisplayPort */
716 struct dp_audio_infoframe *dp_ai = &ai.dp;
717
718 dp_ai->type = 0x84;
719 dp_ai->len = 0x1b;
720 dp_ai->ver = 0x11 << 2;
721 dp_ai->CC02_CT47 = channels - 1;
722 dp_ai->CA = ca;
723 } else {
724 snd_printd("HDMI: unknown connection type at pin %d\n",
725 pin_nid);
726 return;
727 }
728
729 /*
730 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
731 * sizeof(*dp_ai) to avoid partial match/update problems when
732 * the user switches between HDMI/DP monitors.
733 */
734 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
735 sizeof(ai))) {
736 snd_printdd("hdmi_setup_audio_infoframe: "
737 "pin=%d channels=%d\n",
738 pin_nid,
739 channels);
740 hdmi_setup_channel_mapping(codec, pin_nid, ca);
741 hdmi_stop_infoframe_trans(codec, pin_nid);
742 hdmi_fill_audio_infoframe(codec, pin_nid,
743 ai.bytes, sizeof(ai));
744 hdmi_start_infoframe_trans(codec, pin_nid);
745 }
746 }
747
748
749 /*
750 * Unsolicited events
751 */
752
753 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
754
755 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
756 {
757 struct hdmi_spec *spec = codec->spec;
758 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
759 int pin_nid;
760 int pd = !!(res & AC_UNSOL_RES_PD);
761 int eldv = !!(res & AC_UNSOL_RES_ELDV);
762 int pin_idx;
763 struct hda_jack_tbl *jack;
764
765 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
766 if (!jack)
767 return;
768 pin_nid = jack->nid;
769 jack->jack_dirty = 1;
770
771 printk(KERN_INFO
772 "HDMI hot plug event: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
773 codec->addr, pin_nid, pd, eldv);
774
775 pin_idx = pin_nid_to_pin_index(spec, pin_nid);
776 if (pin_idx < 0)
777 return;
778
779 hdmi_present_sense(&spec->pins[pin_idx], 1);
780 snd_hda_jack_report_sync(codec);
781 }
782
783 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
784 {
785 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
786 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
787 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
788 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
789
790 printk(KERN_INFO
791 "HDMI CP event: CODEC=%d PIN=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
792 codec->addr,
793 tag,
794 subtag,
795 cp_state,
796 cp_ready);
797
798 /* TODO */
799 if (cp_state)
800 ;
801 if (cp_ready)
802 ;
803 }
804
805
806 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
807 {
808 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
809 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
810
811 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
812 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
813 return;
814 }
815
816 if (subtag == 0)
817 hdmi_intrinsic_event(codec, res);
818 else
819 hdmi_non_intrinsic_event(codec, res);
820 }
821
822 /*
823 * Callbacks
824 */
825
826 /* HBR should be Non-PCM, 8 channels */
827 #define is_hbr_format(format) \
828 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
829
830 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
831 hda_nid_t pin_nid, u32 stream_tag, int format)
832 {
833 int pinctl;
834 int new_pinctl = 0;
835
836 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
837 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
838 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
839
840 new_pinctl = pinctl & ~AC_PINCTL_EPT;
841 if (is_hbr_format(format))
842 new_pinctl |= AC_PINCTL_EPT_HBR;
843 else
844 new_pinctl |= AC_PINCTL_EPT_NATIVE;
845
846 snd_printdd("hdmi_setup_stream: "
847 "NID=0x%x, %spinctl=0x%x\n",
848 pin_nid,
849 pinctl == new_pinctl ? "" : "new-",
850 new_pinctl);
851
852 if (pinctl != new_pinctl)
853 snd_hda_codec_write(codec, pin_nid, 0,
854 AC_VERB_SET_PIN_WIDGET_CONTROL,
855 new_pinctl);
856
857 }
858 if (is_hbr_format(format) && !new_pinctl) {
859 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
860 return -EINVAL;
861 }
862
863 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
864 return 0;
865 }
866
867 /*
868 * HDA PCM callbacks
869 */
870 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
871 struct hda_codec *codec,
872 struct snd_pcm_substream *substream)
873 {
874 struct hdmi_spec *spec = codec->spec;
875 struct snd_pcm_runtime *runtime = substream->runtime;
876 int pin_idx, cvt_idx, mux_idx = 0;
877 struct hdmi_spec_per_pin *per_pin;
878 struct hdmi_eld *eld;
879 struct hdmi_spec_per_cvt *per_cvt = NULL;
880 int pinctl;
881
882 /* Validate hinfo */
883 pin_idx = hinfo_to_pin_index(spec, hinfo);
884 if (snd_BUG_ON(pin_idx < 0))
885 return -EINVAL;
886 per_pin = &spec->pins[pin_idx];
887 eld = &per_pin->sink_eld;
888
889 /* Dynamically assign converter to stream */
890 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
891 per_cvt = &spec->cvts[cvt_idx];
892
893 /* Must not already be assigned */
894 if (per_cvt->assigned)
895 continue;
896 /* Must be in pin's mux's list of converters */
897 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
898 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
899 break;
900 /* Not in mux list */
901 if (mux_idx == per_pin->num_mux_nids)
902 continue;
903 break;
904 }
905 /* No free converters */
906 if (cvt_idx == spec->num_cvts)
907 return -ENODEV;
908
909 /* Claim converter */
910 per_cvt->assigned = 1;
911 hinfo->nid = per_cvt->cvt_nid;
912
913 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
914 AC_VERB_SET_CONNECT_SEL,
915 mux_idx);
916 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
917 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
918 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
919 AC_VERB_SET_PIN_WIDGET_CONTROL,
920 pinctl | PIN_OUT);
921 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
922
923 /* Initially set the converter's capabilities */
924 hinfo->channels_min = per_cvt->channels_min;
925 hinfo->channels_max = per_cvt->channels_max;
926 hinfo->rates = per_cvt->rates;
927 hinfo->formats = per_cvt->formats;
928 hinfo->maxbps = per_cvt->maxbps;
929
930 /* Restrict capabilities by ELD if this isn't disabled */
931 if (!static_hdmi_pcm && eld->eld_valid) {
932 snd_hdmi_eld_update_pcm_info(eld, hinfo);
933 if (hinfo->channels_min > hinfo->channels_max ||
934 !hinfo->rates || !hinfo->formats)
935 return -ENODEV;
936 }
937
938 /* Store the updated parameters */
939 runtime->hw.channels_min = hinfo->channels_min;
940 runtime->hw.channels_max = hinfo->channels_max;
941 runtime->hw.formats = hinfo->formats;
942 runtime->hw.rates = hinfo->rates;
943
944 snd_pcm_hw_constraint_step(substream->runtime, 0,
945 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
946 return 0;
947 }
948
949 /*
950 * HDA/HDMI auto parsing
951 */
952 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
953 {
954 struct hdmi_spec *spec = codec->spec;
955 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
956 hda_nid_t pin_nid = per_pin->pin_nid;
957
958 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
959 snd_printk(KERN_WARNING
960 "HDMI: pin %d wcaps %#x "
961 "does not support connection list\n",
962 pin_nid, get_wcaps(codec, pin_nid));
963 return -EINVAL;
964 }
965
966 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
967 per_pin->mux_nids,
968 HDA_MAX_CONNECTIONS);
969
970 return 0;
971 }
972
973 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
974 {
975 struct hda_codec *codec = per_pin->codec;
976 struct hdmi_eld *eld = &per_pin->sink_eld;
977 hda_nid_t pin_nid = per_pin->pin_nid;
978 /*
979 * Always execute a GetPinSense verb here, even when called from
980 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
981 * response's PD bit is not the real PD value, but indicates that
982 * the real PD value changed. An older version of the HD-audio
983 * specification worked this way. Hence, we just ignore the data in
984 * the unsolicited response to avoid custom WARs.
985 */
986 int present = snd_hda_pin_sense(codec, pin_nid);
987 bool eld_valid = false;
988
989 memset(eld, 0, offsetof(struct hdmi_eld, eld_buffer));
990
991 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
992 if (eld->monitor_present)
993 eld_valid = !!(present & AC_PINSENSE_ELDV);
994
995 printk(KERN_INFO
996 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
997 codec->addr, pin_nid, eld->monitor_present, eld_valid);
998
999 if (eld_valid) {
1000 if (!snd_hdmi_get_eld(eld, codec, pin_nid))
1001 snd_hdmi_show_eld(eld);
1002 else if (repoll) {
1003 queue_delayed_work(codec->bus->workq,
1004 &per_pin->work,
1005 msecs_to_jiffies(300));
1006 }
1007 }
1008 }
1009
1010 static void hdmi_repoll_eld(struct work_struct *work)
1011 {
1012 struct hdmi_spec_per_pin *per_pin =
1013 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1014
1015 if (per_pin->repoll_count++ > 6)
1016 per_pin->repoll_count = 0;
1017
1018 hdmi_present_sense(per_pin, per_pin->repoll_count);
1019 }
1020
1021 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1022 {
1023 struct hdmi_spec *spec = codec->spec;
1024 unsigned int caps, config;
1025 int pin_idx;
1026 struct hdmi_spec_per_pin *per_pin;
1027 int err;
1028
1029 caps = snd_hda_param_read(codec, pin_nid, AC_PAR_PIN_CAP);
1030 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1031 return 0;
1032
1033 config = snd_hda_codec_read(codec, pin_nid, 0,
1034 AC_VERB_GET_CONFIG_DEFAULT, 0);
1035 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1036 return 0;
1037
1038 if (snd_BUG_ON(spec->num_pins >= MAX_HDMI_PINS))
1039 return -E2BIG;
1040
1041 pin_idx = spec->num_pins;
1042 per_pin = &spec->pins[pin_idx];
1043
1044 per_pin->pin_nid = pin_nid;
1045
1046 err = hdmi_read_pin_conn(codec, pin_idx);
1047 if (err < 0)
1048 return err;
1049
1050 spec->num_pins++;
1051
1052 return 0;
1053 }
1054
1055 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1056 {
1057 struct hdmi_spec *spec = codec->spec;
1058 int cvt_idx;
1059 struct hdmi_spec_per_cvt *per_cvt;
1060 unsigned int chans;
1061 int err;
1062
1063 if (snd_BUG_ON(spec->num_cvts >= MAX_HDMI_CVTS))
1064 return -E2BIG;
1065
1066 chans = get_wcaps(codec, cvt_nid);
1067 chans = get_wcaps_channels(chans);
1068
1069 cvt_idx = spec->num_cvts;
1070 per_cvt = &spec->cvts[cvt_idx];
1071
1072 per_cvt->cvt_nid = cvt_nid;
1073 per_cvt->channels_min = 2;
1074 if (chans <= 16)
1075 per_cvt->channels_max = chans;
1076
1077 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1078 &per_cvt->rates,
1079 &per_cvt->formats,
1080 &per_cvt->maxbps);
1081 if (err < 0)
1082 return err;
1083
1084 spec->num_cvts++;
1085
1086 return 0;
1087 }
1088
1089 static int hdmi_parse_codec(struct hda_codec *codec)
1090 {
1091 hda_nid_t nid;
1092 int i, nodes;
1093
1094 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1095 if (!nid || nodes < 0) {
1096 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
1097 return -EINVAL;
1098 }
1099
1100 for (i = 0; i < nodes; i++, nid++) {
1101 unsigned int caps;
1102 unsigned int type;
1103
1104 caps = snd_hda_param_read(codec, nid, AC_PAR_AUDIO_WIDGET_CAP);
1105 type = get_wcaps_type(caps);
1106
1107 if (!(caps & AC_WCAP_DIGITAL))
1108 continue;
1109
1110 switch (type) {
1111 case AC_WID_AUD_OUT:
1112 hdmi_add_cvt(codec, nid);
1113 break;
1114 case AC_WID_PIN:
1115 hdmi_add_pin(codec, nid);
1116 break;
1117 }
1118 }
1119
1120 /*
1121 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
1122 * can be lost and presence sense verb will become inaccurate if the
1123 * HDA link is powered off at hot plug or hw initialization time.
1124 */
1125 #ifdef CONFIG_SND_HDA_POWER_SAVE
1126 if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
1127 AC_PWRST_EPSS))
1128 codec->bus->power_keep_link_on = 1;
1129 #endif
1130
1131 return 0;
1132 }
1133
1134 /*
1135 */
1136 static char *get_hdmi_pcm_name(int idx)
1137 {
1138 static char names[MAX_HDMI_PINS][8];
1139 sprintf(&names[idx][0], "HDMI %d", idx);
1140 return &names[idx][0];
1141 }
1142
1143 /*
1144 * HDMI callbacks
1145 */
1146
1147 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1148 struct hda_codec *codec,
1149 unsigned int stream_tag,
1150 unsigned int format,
1151 struct snd_pcm_substream *substream)
1152 {
1153 hda_nid_t cvt_nid = hinfo->nid;
1154 struct hdmi_spec *spec = codec->spec;
1155 int pin_idx = hinfo_to_pin_index(spec, hinfo);
1156 hda_nid_t pin_nid = spec->pins[pin_idx].pin_nid;
1157
1158 hdmi_set_channel_count(codec, cvt_nid, substream->runtime->channels);
1159
1160 hdmi_setup_audio_infoframe(codec, pin_idx, substream);
1161
1162 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
1163 }
1164
1165 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1166 struct hda_codec *codec,
1167 struct snd_pcm_substream *substream)
1168 {
1169 struct hdmi_spec *spec = codec->spec;
1170 int cvt_idx, pin_idx;
1171 struct hdmi_spec_per_cvt *per_cvt;
1172 struct hdmi_spec_per_pin *per_pin;
1173 int pinctl;
1174
1175 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1176
1177 if (hinfo->nid) {
1178 cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
1179 if (snd_BUG_ON(cvt_idx < 0))
1180 return -EINVAL;
1181 per_cvt = &spec->cvts[cvt_idx];
1182
1183 snd_BUG_ON(!per_cvt->assigned);
1184 per_cvt->assigned = 0;
1185 hinfo->nid = 0;
1186
1187 pin_idx = hinfo_to_pin_index(spec, hinfo);
1188 if (snd_BUG_ON(pin_idx < 0))
1189 return -EINVAL;
1190 per_pin = &spec->pins[pin_idx];
1191
1192 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1193 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1194 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1195 AC_VERB_SET_PIN_WIDGET_CONTROL,
1196 pinctl & ~PIN_OUT);
1197 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1198 }
1199
1200 return 0;
1201 }
1202
1203 static const struct hda_pcm_ops generic_ops = {
1204 .open = hdmi_pcm_open,
1205 .prepare = generic_hdmi_playback_pcm_prepare,
1206 .cleanup = generic_hdmi_playback_pcm_cleanup,
1207 };
1208
1209 static int generic_hdmi_build_pcms(struct hda_codec *codec)
1210 {
1211 struct hdmi_spec *spec = codec->spec;
1212 int pin_idx;
1213
1214 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1215 struct hda_pcm *info;
1216 struct hda_pcm_stream *pstr;
1217
1218 info = &spec->pcm_rec[pin_idx];
1219 info->name = get_hdmi_pcm_name(pin_idx);
1220 info->pcm_type = HDA_PCM_TYPE_HDMI;
1221
1222 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
1223 pstr->substreams = 1;
1224 pstr->ops = generic_ops;
1225 /* other pstr fields are set in open */
1226 }
1227
1228 codec->num_pcms = spec->num_pins;
1229 codec->pcm_info = spec->pcm_rec;
1230
1231 return 0;
1232 }
1233
1234 static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
1235 {
1236 char hdmi_str[32] = "HDMI/DP";
1237 struct hdmi_spec *spec = codec->spec;
1238 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1239 int pcmdev = spec->pcm_rec[pin_idx].device;
1240
1241 if (pcmdev > 0)
1242 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
1243
1244 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
1245 }
1246
1247 static int generic_hdmi_build_controls(struct hda_codec *codec)
1248 {
1249 struct hdmi_spec *spec = codec->spec;
1250 int err;
1251 int pin_idx;
1252
1253 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1254 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1255
1256 err = generic_hdmi_build_jack(codec, pin_idx);
1257 if (err < 0)
1258 return err;
1259
1260 err = snd_hda_create_spdif_out_ctls(codec,
1261 per_pin->pin_nid,
1262 per_pin->mux_nids[0]);
1263 if (err < 0)
1264 return err;
1265 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1266
1267 /* add control for ELD Bytes */
1268 err = hdmi_create_eld_ctl(codec,
1269 pin_idx,
1270 spec->pcm_rec[pin_idx].device);
1271
1272 if (err < 0)
1273 return err;
1274
1275 hdmi_present_sense(per_pin, 0);
1276 }
1277
1278 return 0;
1279 }
1280
1281 static int generic_hdmi_init(struct hda_codec *codec)
1282 {
1283 struct hdmi_spec *spec = codec->spec;
1284 int pin_idx;
1285
1286 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1287 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1288 hda_nid_t pin_nid = per_pin->pin_nid;
1289 struct hdmi_eld *eld = &per_pin->sink_eld;
1290
1291 hdmi_init_pin(codec, pin_nid);
1292 snd_hda_jack_detect_enable(codec, pin_nid, pin_nid);
1293
1294 per_pin->codec = codec;
1295 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
1296 snd_hda_eld_proc_new(codec, eld, pin_idx);
1297 }
1298 snd_hda_jack_report_sync(codec);
1299 return 0;
1300 }
1301
1302 static void generic_hdmi_free(struct hda_codec *codec)
1303 {
1304 struct hdmi_spec *spec = codec->spec;
1305 int pin_idx;
1306
1307 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1308 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1309 struct hdmi_eld *eld = &per_pin->sink_eld;
1310
1311 cancel_delayed_work(&per_pin->work);
1312 snd_hda_eld_proc_free(codec, eld);
1313 }
1314
1315 flush_workqueue(codec->bus->workq);
1316 kfree(spec);
1317 }
1318
1319 static const struct hda_codec_ops generic_hdmi_patch_ops = {
1320 .init = generic_hdmi_init,
1321 .free = generic_hdmi_free,
1322 .build_pcms = generic_hdmi_build_pcms,
1323 .build_controls = generic_hdmi_build_controls,
1324 .unsol_event = hdmi_unsol_event,
1325 };
1326
1327 static int patch_generic_hdmi(struct hda_codec *codec)
1328 {
1329 struct hdmi_spec *spec;
1330
1331 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1332 if (spec == NULL)
1333 return -ENOMEM;
1334
1335 codec->spec = spec;
1336 if (hdmi_parse_codec(codec) < 0) {
1337 codec->spec = NULL;
1338 kfree(spec);
1339 return -EINVAL;
1340 }
1341 codec->patch_ops = generic_hdmi_patch_ops;
1342
1343 init_channel_allocations();
1344
1345 return 0;
1346 }
1347
1348 /*
1349 * Shared non-generic implementations
1350 */
1351
1352 static int simple_playback_build_pcms(struct hda_codec *codec)
1353 {
1354 struct hdmi_spec *spec = codec->spec;
1355 struct hda_pcm *info = spec->pcm_rec;
1356 int i;
1357
1358 codec->num_pcms = spec->num_cvts;
1359 codec->pcm_info = info;
1360
1361 for (i = 0; i < codec->num_pcms; i++, info++) {
1362 unsigned int chans;
1363 struct hda_pcm_stream *pstr;
1364
1365 chans = get_wcaps(codec, spec->cvts[i].cvt_nid);
1366 chans = get_wcaps_channels(chans);
1367
1368 info->name = get_hdmi_pcm_name(i);
1369 info->pcm_type = HDA_PCM_TYPE_HDMI;
1370 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
1371 snd_BUG_ON(!spec->pcm_playback);
1372 *pstr = *spec->pcm_playback;
1373 pstr->nid = spec->cvts[i].cvt_nid;
1374 if (pstr->channels_max <= 2 && chans && chans <= 16)
1375 pstr->channels_max = chans;
1376 }
1377
1378 return 0;
1379 }
1380
1381 static int simple_playback_build_controls(struct hda_codec *codec)
1382 {
1383 struct hdmi_spec *spec = codec->spec;
1384 int err;
1385 int i;
1386
1387 for (i = 0; i < codec->num_pcms; i++) {
1388 err = snd_hda_create_spdif_out_ctls(codec,
1389 spec->cvts[i].cvt_nid,
1390 spec->cvts[i].cvt_nid);
1391 if (err < 0)
1392 return err;
1393 }
1394
1395 return 0;
1396 }
1397
1398 static void simple_playback_free(struct hda_codec *codec)
1399 {
1400 struct hdmi_spec *spec = codec->spec;
1401
1402 kfree(spec);
1403 }
1404
1405 /*
1406 * Nvidia specific implementations
1407 */
1408
1409 #define Nv_VERB_SET_Channel_Allocation 0xF79
1410 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
1411 #define Nv_VERB_SET_Audio_Protection_On 0xF98
1412 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
1413
1414 #define nvhdmi_master_con_nid_7x 0x04
1415 #define nvhdmi_master_pin_nid_7x 0x05
1416
1417 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
1418 /*front, rear, clfe, rear_surr */
1419 0x6, 0x8, 0xa, 0xc,
1420 };
1421
1422 static const struct hda_verb nvhdmi_basic_init_7x[] = {
1423 /* set audio protect on */
1424 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
1425 /* enable digital output on pin widget */
1426 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1427 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1428 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1429 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1430 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1431 {} /* terminator */
1432 };
1433
1434 #ifdef LIMITED_RATE_FMT_SUPPORT
1435 /* support only the safe format and rate */
1436 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
1437 #define SUPPORTED_MAXBPS 16
1438 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1439 #else
1440 /* support all rates and formats */
1441 #define SUPPORTED_RATES \
1442 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
1443 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
1444 SNDRV_PCM_RATE_192000)
1445 #define SUPPORTED_MAXBPS 24
1446 #define SUPPORTED_FORMATS \
1447 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
1448 #endif
1449
1450 static int nvhdmi_7x_init(struct hda_codec *codec)
1451 {
1452 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x);
1453 return 0;
1454 }
1455
1456 static unsigned int channels_2_6_8[] = {
1457 2, 6, 8
1458 };
1459
1460 static unsigned int channels_2_8[] = {
1461 2, 8
1462 };
1463
1464 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
1465 .count = ARRAY_SIZE(channels_2_6_8),
1466 .list = channels_2_6_8,
1467 .mask = 0,
1468 };
1469
1470 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
1471 .count = ARRAY_SIZE(channels_2_8),
1472 .list = channels_2_8,
1473 .mask = 0,
1474 };
1475
1476 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
1477 struct hda_codec *codec,
1478 struct snd_pcm_substream *substream)
1479 {
1480 struct hdmi_spec *spec = codec->spec;
1481 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
1482
1483 switch (codec->preset->id) {
1484 case 0x10de0002:
1485 case 0x10de0003:
1486 case 0x10de0005:
1487 case 0x10de0006:
1488 hw_constraints_channels = &hw_constraints_2_8_channels;
1489 break;
1490 case 0x10de0007:
1491 hw_constraints_channels = &hw_constraints_2_6_8_channels;
1492 break;
1493 default:
1494 break;
1495 }
1496
1497 if (hw_constraints_channels != NULL) {
1498 snd_pcm_hw_constraint_list(substream->runtime, 0,
1499 SNDRV_PCM_HW_PARAM_CHANNELS,
1500 hw_constraints_channels);
1501 } else {
1502 snd_pcm_hw_constraint_step(substream->runtime, 0,
1503 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1504 }
1505
1506 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
1507 }
1508
1509 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
1510 struct hda_codec *codec,
1511 struct snd_pcm_substream *substream)
1512 {
1513 struct hdmi_spec *spec = codec->spec;
1514 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
1515 }
1516
1517 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1518 struct hda_codec *codec,
1519 unsigned int stream_tag,
1520 unsigned int format,
1521 struct snd_pcm_substream *substream)
1522 {
1523 struct hdmi_spec *spec = codec->spec;
1524 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
1525 stream_tag, format, substream);
1526 }
1527
1528 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
1529 int channels)
1530 {
1531 unsigned int chanmask;
1532 int chan = channels ? (channels - 1) : 1;
1533
1534 switch (channels) {
1535 default:
1536 case 0:
1537 case 2:
1538 chanmask = 0x00;
1539 break;
1540 case 4:
1541 chanmask = 0x08;
1542 break;
1543 case 6:
1544 chanmask = 0x0b;
1545 break;
1546 case 8:
1547 chanmask = 0x13;
1548 break;
1549 }
1550
1551 /* Set the audio infoframe channel allocation and checksum fields. The
1552 * channel count is computed implicitly by the hardware. */
1553 snd_hda_codec_write(codec, 0x1, 0,
1554 Nv_VERB_SET_Channel_Allocation, chanmask);
1555
1556 snd_hda_codec_write(codec, 0x1, 0,
1557 Nv_VERB_SET_Info_Frame_Checksum,
1558 (0x71 - chan - chanmask));
1559 }
1560
1561 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
1562 struct hda_codec *codec,
1563 struct snd_pcm_substream *substream)
1564 {
1565 struct hdmi_spec *spec = codec->spec;
1566 int i;
1567
1568 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
1569 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
1570 for (i = 0; i < 4; i++) {
1571 /* set the stream id */
1572 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
1573 AC_VERB_SET_CHANNEL_STREAMID, 0);
1574 /* set the stream format */
1575 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
1576 AC_VERB_SET_STREAM_FORMAT, 0);
1577 }
1578
1579 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
1580 * streams are disabled. */
1581 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
1582
1583 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
1584 }
1585
1586 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
1587 struct hda_codec *codec,
1588 unsigned int stream_tag,
1589 unsigned int format,
1590 struct snd_pcm_substream *substream)
1591 {
1592 int chs;
1593 unsigned int dataDCC2, channel_id;
1594 int i;
1595 struct hdmi_spec *spec = codec->spec;
1596 struct hda_spdif_out *spdif =
1597 snd_hda_spdif_out_of_nid(codec, spec->cvts[0].cvt_nid);
1598
1599 mutex_lock(&codec->spdif_mutex);
1600
1601 chs = substream->runtime->channels;
1602
1603 dataDCC2 = 0x2;
1604
1605 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
1606 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
1607 snd_hda_codec_write(codec,
1608 nvhdmi_master_con_nid_7x,
1609 0,
1610 AC_VERB_SET_DIGI_CONVERT_1,
1611 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
1612
1613 /* set the stream id */
1614 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
1615 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
1616
1617 /* set the stream format */
1618 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
1619 AC_VERB_SET_STREAM_FORMAT, format);
1620
1621 /* turn on again (if needed) */
1622 /* enable and set the channel status audio/data flag */
1623 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
1624 snd_hda_codec_write(codec,
1625 nvhdmi_master_con_nid_7x,
1626 0,
1627 AC_VERB_SET_DIGI_CONVERT_1,
1628 spdif->ctls & 0xff);
1629 snd_hda_codec_write(codec,
1630 nvhdmi_master_con_nid_7x,
1631 0,
1632 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
1633 }
1634
1635 for (i = 0; i < 4; i++) {
1636 if (chs == 2)
1637 channel_id = 0;
1638 else
1639 channel_id = i * 2;
1640
1641 /* turn off SPDIF once;
1642 *otherwise the IEC958 bits won't be updated
1643 */
1644 if (codec->spdif_status_reset &&
1645 (spdif->ctls & AC_DIG1_ENABLE))
1646 snd_hda_codec_write(codec,
1647 nvhdmi_con_nids_7x[i],
1648 0,
1649 AC_VERB_SET_DIGI_CONVERT_1,
1650 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
1651 /* set the stream id */
1652 snd_hda_codec_write(codec,
1653 nvhdmi_con_nids_7x[i],
1654 0,
1655 AC_VERB_SET_CHANNEL_STREAMID,
1656 (stream_tag << 4) | channel_id);
1657 /* set the stream format */
1658 snd_hda_codec_write(codec,
1659 nvhdmi_con_nids_7x[i],
1660 0,
1661 AC_VERB_SET_STREAM_FORMAT,
1662 format);
1663 /* turn on again (if needed) */
1664 /* enable and set the channel status audio/data flag */
1665 if (codec->spdif_status_reset &&
1666 (spdif->ctls & AC_DIG1_ENABLE)) {
1667 snd_hda_codec_write(codec,
1668 nvhdmi_con_nids_7x[i],
1669 0,
1670 AC_VERB_SET_DIGI_CONVERT_1,
1671 spdif->ctls & 0xff);
1672 snd_hda_codec_write(codec,
1673 nvhdmi_con_nids_7x[i],
1674 0,
1675 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
1676 }
1677 }
1678
1679 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
1680
1681 mutex_unlock(&codec->spdif_mutex);
1682 return 0;
1683 }
1684
1685 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
1686 .substreams = 1,
1687 .channels_min = 2,
1688 .channels_max = 8,
1689 .nid = nvhdmi_master_con_nid_7x,
1690 .rates = SUPPORTED_RATES,
1691 .maxbps = SUPPORTED_MAXBPS,
1692 .formats = SUPPORTED_FORMATS,
1693 .ops = {
1694 .open = simple_playback_pcm_open,
1695 .close = nvhdmi_8ch_7x_pcm_close,
1696 .prepare = nvhdmi_8ch_7x_pcm_prepare
1697 },
1698 };
1699
1700 static const struct hda_pcm_stream nvhdmi_pcm_playback_2ch = {
1701 .substreams = 1,
1702 .channels_min = 2,
1703 .channels_max = 2,
1704 .nid = nvhdmi_master_con_nid_7x,
1705 .rates = SUPPORTED_RATES,
1706 .maxbps = SUPPORTED_MAXBPS,
1707 .formats = SUPPORTED_FORMATS,
1708 .ops = {
1709 .open = simple_playback_pcm_open,
1710 .close = simple_playback_pcm_close,
1711 .prepare = simple_playback_pcm_prepare
1712 },
1713 };
1714
1715 static const struct hda_codec_ops nvhdmi_patch_ops_8ch_7x = {
1716 .build_controls = simple_playback_build_controls,
1717 .build_pcms = simple_playback_build_pcms,
1718 .init = nvhdmi_7x_init,
1719 .free = simple_playback_free,
1720 };
1721
1722 static const struct hda_codec_ops nvhdmi_patch_ops_2ch = {
1723 .build_controls = simple_playback_build_controls,
1724 .build_pcms = simple_playback_build_pcms,
1725 .init = nvhdmi_7x_init,
1726 .free = simple_playback_free,
1727 };
1728
1729 static int patch_nvhdmi_2ch(struct hda_codec *codec)
1730 {
1731 struct hdmi_spec *spec;
1732
1733 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1734 if (spec == NULL)
1735 return -ENOMEM;
1736
1737 codec->spec = spec;
1738
1739 spec->multiout.num_dacs = 0; /* no analog */
1740 spec->multiout.max_channels = 2;
1741 spec->multiout.dig_out_nid = nvhdmi_master_con_nid_7x;
1742 spec->num_cvts = 1;
1743 spec->cvts[0].cvt_nid = nvhdmi_master_con_nid_7x;
1744 spec->pcm_playback = &nvhdmi_pcm_playback_2ch;
1745
1746 codec->patch_ops = nvhdmi_patch_ops_2ch;
1747
1748 return 0;
1749 }
1750
1751 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
1752 {
1753 struct hdmi_spec *spec;
1754 int err = patch_nvhdmi_2ch(codec);
1755
1756 if (err < 0)
1757 return err;
1758 spec = codec->spec;
1759 spec->multiout.max_channels = 8;
1760 spec->pcm_playback = &nvhdmi_pcm_playback_8ch_7x;
1761 codec->patch_ops = nvhdmi_patch_ops_8ch_7x;
1762
1763 /* Initialize the audio infoframe channel mask and checksum to something
1764 * valid */
1765 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
1766
1767 return 0;
1768 }
1769
1770 /*
1771 * ATI-specific implementations
1772 *
1773 * FIXME: we may omit the whole this and use the generic code once after
1774 * it's confirmed to work.
1775 */
1776
1777 #define ATIHDMI_CVT_NID 0x02 /* audio converter */
1778 #define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
1779
1780 static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1781 struct hda_codec *codec,
1782 unsigned int stream_tag,
1783 unsigned int format,
1784 struct snd_pcm_substream *substream)
1785 {
1786 struct hdmi_spec *spec = codec->spec;
1787 int chans = substream->runtime->channels;
1788 int i, err;
1789
1790 err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format,
1791 substream);
1792 if (err < 0)
1793 return err;
1794 snd_hda_codec_write(codec, spec->cvts[0].cvt_nid, 0,
1795 AC_VERB_SET_CVT_CHAN_COUNT, chans - 1);
1796 /* FIXME: XXX */
1797 for (i = 0; i < chans; i++) {
1798 snd_hda_codec_write(codec, spec->cvts[0].cvt_nid, 0,
1799 AC_VERB_SET_HDMI_CHAN_SLOT,
1800 (i << 4) | i);
1801 }
1802 return 0;
1803 }
1804
1805 static const struct hda_pcm_stream atihdmi_pcm_digital_playback = {
1806 .substreams = 1,
1807 .channels_min = 2,
1808 .channels_max = 2,
1809 .nid = ATIHDMI_CVT_NID,
1810 .ops = {
1811 .open = simple_playback_pcm_open,
1812 .close = simple_playback_pcm_close,
1813 .prepare = atihdmi_playback_pcm_prepare
1814 },
1815 };
1816
1817 static const struct hda_verb atihdmi_basic_init[] = {
1818 /* enable digital output on pin widget */
1819 { 0x03, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT },
1820 {} /* terminator */
1821 };
1822
1823 static int atihdmi_init(struct hda_codec *codec)
1824 {
1825 struct hdmi_spec *spec = codec->spec;
1826
1827 snd_hda_sequence_write(codec, atihdmi_basic_init);
1828 /* SI codec requires to unmute the pin */
1829 if (get_wcaps(codec, spec->pins[0].pin_nid) & AC_WCAP_OUT_AMP)
1830 snd_hda_codec_write(codec, spec->pins[0].pin_nid, 0,
1831 AC_VERB_SET_AMP_GAIN_MUTE,
1832 AMP_OUT_UNMUTE);
1833 return 0;
1834 }
1835
1836 static const struct hda_codec_ops atihdmi_patch_ops = {
1837 .build_controls = simple_playback_build_controls,
1838 .build_pcms = simple_playback_build_pcms,
1839 .init = atihdmi_init,
1840 .free = simple_playback_free,
1841 };
1842
1843
1844 static int patch_atihdmi(struct hda_codec *codec)
1845 {
1846 struct hdmi_spec *spec;
1847
1848 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1849 if (spec == NULL)
1850 return -ENOMEM;
1851
1852 codec->spec = spec;
1853
1854 spec->multiout.num_dacs = 0; /* no analog */
1855 spec->multiout.max_channels = 2;
1856 spec->multiout.dig_out_nid = ATIHDMI_CVT_NID;
1857 spec->num_cvts = 1;
1858 spec->cvts[0].cvt_nid = ATIHDMI_CVT_NID;
1859 spec->pins[0].pin_nid = ATIHDMI_PIN_NID;
1860 spec->pcm_playback = &atihdmi_pcm_digital_playback;
1861
1862 codec->patch_ops = atihdmi_patch_ops;
1863
1864 return 0;
1865 }
1866
1867
1868 /*
1869 * patch entries
1870 */
1871 static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
1872 { .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
1873 { .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
1874 { .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
1875 { .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi },
1876 { .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
1877 { .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
1878 { .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
1879 { .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1880 { .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1881 { .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1882 { .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1883 { .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
1884 { .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_generic_hdmi },
1885 { .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_generic_hdmi },
1886 { .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_generic_hdmi },
1887 { .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_generic_hdmi },
1888 { .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_generic_hdmi },
1889 { .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_generic_hdmi },
1890 { .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_generic_hdmi },
1891 { .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_generic_hdmi },
1892 { .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_generic_hdmi },
1893 { .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_generic_hdmi },
1894 { .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_generic_hdmi },
1895 /* 17 is known to be absent */
1896 { .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_generic_hdmi },
1897 { .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_generic_hdmi },
1898 { .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_generic_hdmi },
1899 { .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_generic_hdmi },
1900 { .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_generic_hdmi },
1901 { .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_generic_hdmi },
1902 { .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_generic_hdmi },
1903 { .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_generic_hdmi },
1904 { .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_generic_hdmi },
1905 { .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_generic_hdmi },
1906 { .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
1907 { .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
1908 { .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
1909 { .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
1910 { .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
1911 { .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
1912 { .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
1913 { .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
1914 { .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
1915 { .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
1916 {} /* terminator */
1917 };
1918
1919 MODULE_ALIAS("snd-hda-codec-id:1002793c");
1920 MODULE_ALIAS("snd-hda-codec-id:10027919");
1921 MODULE_ALIAS("snd-hda-codec-id:1002791a");
1922 MODULE_ALIAS("snd-hda-codec-id:1002aa01");
1923 MODULE_ALIAS("snd-hda-codec-id:10951390");
1924 MODULE_ALIAS("snd-hda-codec-id:10951392");
1925 MODULE_ALIAS("snd-hda-codec-id:10de0002");
1926 MODULE_ALIAS("snd-hda-codec-id:10de0003");
1927 MODULE_ALIAS("snd-hda-codec-id:10de0005");
1928 MODULE_ALIAS("snd-hda-codec-id:10de0006");
1929 MODULE_ALIAS("snd-hda-codec-id:10de0007");
1930 MODULE_ALIAS("snd-hda-codec-id:10de000a");
1931 MODULE_ALIAS("snd-hda-codec-id:10de000b");
1932 MODULE_ALIAS("snd-hda-codec-id:10de000c");
1933 MODULE_ALIAS("snd-hda-codec-id:10de000d");
1934 MODULE_ALIAS("snd-hda-codec-id:10de0010");
1935 MODULE_ALIAS("snd-hda-codec-id:10de0011");
1936 MODULE_ALIAS("snd-hda-codec-id:10de0012");
1937 MODULE_ALIAS("snd-hda-codec-id:10de0013");
1938 MODULE_ALIAS("snd-hda-codec-id:10de0014");
1939 MODULE_ALIAS("snd-hda-codec-id:10de0015");
1940 MODULE_ALIAS("snd-hda-codec-id:10de0016");
1941 MODULE_ALIAS("snd-hda-codec-id:10de0018");
1942 MODULE_ALIAS("snd-hda-codec-id:10de0019");
1943 MODULE_ALIAS("snd-hda-codec-id:10de001a");
1944 MODULE_ALIAS("snd-hda-codec-id:10de001b");
1945 MODULE_ALIAS("snd-hda-codec-id:10de001c");
1946 MODULE_ALIAS("snd-hda-codec-id:10de0040");
1947 MODULE_ALIAS("snd-hda-codec-id:10de0041");
1948 MODULE_ALIAS("snd-hda-codec-id:10de0042");
1949 MODULE_ALIAS("snd-hda-codec-id:10de0043");
1950 MODULE_ALIAS("snd-hda-codec-id:10de0044");
1951 MODULE_ALIAS("snd-hda-codec-id:10de0067");
1952 MODULE_ALIAS("snd-hda-codec-id:10de8001");
1953 MODULE_ALIAS("snd-hda-codec-id:17e80047");
1954 MODULE_ALIAS("snd-hda-codec-id:80860054");
1955 MODULE_ALIAS("snd-hda-codec-id:80862801");
1956 MODULE_ALIAS("snd-hda-codec-id:80862802");
1957 MODULE_ALIAS("snd-hda-codec-id:80862803");
1958 MODULE_ALIAS("snd-hda-codec-id:80862804");
1959 MODULE_ALIAS("snd-hda-codec-id:80862805");
1960 MODULE_ALIAS("snd-hda-codec-id:80862806");
1961 MODULE_ALIAS("snd-hda-codec-id:808629fb");
1962
1963 MODULE_LICENSE("GPL");
1964 MODULE_DESCRIPTION("HDMI HD-audio codec");
1965 MODULE_ALIAS("snd-hda-codec-intelhdmi");
1966 MODULE_ALIAS("snd-hda-codec-nvhdmi");
1967 MODULE_ALIAS("snd-hda-codec-atihdmi");
1968
1969 static struct hda_codec_preset_list intel_list = {
1970 .preset = snd_hda_preset_hdmi,
1971 .owner = THIS_MODULE,
1972 };
1973
1974 static int __init patch_hdmi_init(void)
1975 {
1976 return snd_hda_add_codec_preset(&intel_list);
1977 }
1978
1979 static void __exit patch_hdmi_exit(void)
1980 {
1981 snd_hda_delete_codec_preset(&intel_list);
1982 }
1983
1984 module_init(patch_hdmi_init)
1985 module_exit(patch_hdmi_exit)