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usb: Netlogic: Use CPU_XLR in place of NLM_XLR
[zen-stable.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_stats.c
blob02ac6a771bf99eaa254ee9c66e199dfbe70552df
1 /* bnx2x_stats.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2011 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20 #include "bnx2x_stats.h"
21 #include "bnx2x_cmn.h"
22
23
24 /* Statistics */
25
26 /*
27 * General service functions
28 */
29
30 static inline long bnx2x_hilo(u32 *hiref)
31 {
32 u32 lo = *(hiref + 1);
33 #if (BITS_PER_LONG == 64)
34 u32 hi = *hiref;
35
36 return HILO_U64(hi, lo);
37 #else
38 return lo;
39 #endif
40 }
41
42 /*
43 * Init service functions
44 */
45
46 /* Post the next statistics ramrod. Protect it with the spin in
47 * order to ensure the strict order between statistics ramrods
48 * (each ramrod has a sequence number passed in a
49 * bp->fw_stats_req->hdr.drv_stats_counter and ramrods must be
50 * sent in order).
51 */
52 static void bnx2x_storm_stats_post(struct bnx2x *bp)
53 {
54 if (!bp->stats_pending) {
55 int rc;
56
57 spin_lock_bh(&bp->stats_lock);
58
59 if (bp->stats_pending) {
60 spin_unlock_bh(&bp->stats_lock);
61 return;
62 }
63
64 bp->fw_stats_req->hdr.drv_stats_counter =
65 cpu_to_le16(bp->stats_counter++);
66
67 DP(NETIF_MSG_TIMER, "Sending statistics ramrod %d\n",
68 bp->fw_stats_req->hdr.drv_stats_counter);
69
70
71
72 /* send FW stats ramrod */
73 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_STAT_QUERY, 0,
74 U64_HI(bp->fw_stats_req_mapping),
75 U64_LO(bp->fw_stats_req_mapping),
76 NONE_CONNECTION_TYPE);
77 if (rc == 0)
78 bp->stats_pending = 1;
79
80 spin_unlock_bh(&bp->stats_lock);
81 }
82 }
83
84 static void bnx2x_hw_stats_post(struct bnx2x *bp)
85 {
86 struct dmae_command *dmae = &bp->stats_dmae;
87 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
88
89 *stats_comp = DMAE_COMP_VAL;
90 if (CHIP_REV_IS_SLOW(bp))
91 return;
92
93 /* loader */
94 if (bp->executer_idx) {
95 int loader_idx = PMF_DMAE_C(bp);
96 u32 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
97 true, DMAE_COMP_GRC);
98 opcode = bnx2x_dmae_opcode_clr_src_reset(opcode);
99
100 memset(dmae, 0, sizeof(struct dmae_command));
101 dmae->opcode = opcode;
102 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0]));
103 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0]));
104 dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
105 sizeof(struct dmae_command) *
106 (loader_idx + 1)) >> 2;
107 dmae->dst_addr_hi = 0;
108 dmae->len = sizeof(struct dmae_command) >> 2;
109 if (CHIP_IS_E1(bp))
110 dmae->len--;
111 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
112 dmae->comp_addr_hi = 0;
113 dmae->comp_val = 1;
114
115 *stats_comp = 0;
116 bnx2x_post_dmae(bp, dmae, loader_idx);
117
118 } else if (bp->func_stx) {
119 *stats_comp = 0;
120 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
121 }
122 }
123
124 static int bnx2x_stats_comp(struct bnx2x *bp)
125 {
126 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
127 int cnt = 10;
128
129 might_sleep();
130 while (*stats_comp != DMAE_COMP_VAL) {
131 if (!cnt) {
132 BNX2X_ERR("timeout waiting for stats finished\n");
133 break;
134 }
135 cnt--;
136 usleep_range(1000, 1000);
137 }
138 return 1;
139 }
140
141 /*
142 * Statistics service functions
143 */
144
145 static void bnx2x_stats_pmf_update(struct bnx2x *bp)
146 {
147 struct dmae_command *dmae;
148 u32 opcode;
149 int loader_idx = PMF_DMAE_C(bp);
150 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
151
152 /* sanity */
153 if (!IS_MF(bp) || !bp->port.pmf || !bp->port.port_stx) {
154 BNX2X_ERR("BUG!\n");
155 return;
156 }
157
158 bp->executer_idx = 0;
159
160 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI, false, 0);
161
162 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
163 dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_GRC);
164 dmae->src_addr_lo = bp->port.port_stx >> 2;
165 dmae->src_addr_hi = 0;
166 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
167 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
168 dmae->len = DMAE_LEN32_RD_MAX;
169 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
170 dmae->comp_addr_hi = 0;
171 dmae->comp_val = 1;
172
173 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
174 dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);
175 dmae->src_addr_lo = (bp->port.port_stx >> 2) + DMAE_LEN32_RD_MAX;
176 dmae->src_addr_hi = 0;
177 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats) +
178 DMAE_LEN32_RD_MAX * 4);
179 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats) +
180 DMAE_LEN32_RD_MAX * 4);
181 dmae->len = (sizeof(struct host_port_stats) >> 2) - DMAE_LEN32_RD_MAX;
182 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
183 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
184 dmae->comp_val = DMAE_COMP_VAL;
185
186 *stats_comp = 0;
187 bnx2x_hw_stats_post(bp);
188 bnx2x_stats_comp(bp);
189 }
190
191 static void bnx2x_port_stats_init(struct bnx2x *bp)
192 {
193 struct dmae_command *dmae;
194 int port = BP_PORT(bp);
195 u32 opcode;
196 int loader_idx = PMF_DMAE_C(bp);
197 u32 mac_addr;
198 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
199
200 /* sanity */
201 if (!bp->link_vars.link_up || !bp->port.pmf) {
202 BNX2X_ERR("BUG!\n");
203 return;
204 }
205
206 bp->executer_idx = 0;
207
208 /* MCP */
209 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
210 true, DMAE_COMP_GRC);
211
212 if (bp->port.port_stx) {
213
214 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
215 dmae->opcode = opcode;
216 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
217 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
218 dmae->dst_addr_lo = bp->port.port_stx >> 2;
219 dmae->dst_addr_hi = 0;
220 dmae->len = sizeof(struct host_port_stats) >> 2;
221 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
222 dmae->comp_addr_hi = 0;
223 dmae->comp_val = 1;
224 }
225
226 if (bp->func_stx) {
227
228 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
229 dmae->opcode = opcode;
230 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
231 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
232 dmae->dst_addr_lo = bp->func_stx >> 2;
233 dmae->dst_addr_hi = 0;
234 dmae->len = sizeof(struct host_func_stats) >> 2;
235 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
236 dmae->comp_addr_hi = 0;
237 dmae->comp_val = 1;
238 }
239
240 /* MAC */
241 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI,
242 true, DMAE_COMP_GRC);
243
244 /* EMAC is special */
245 if (bp->link_vars.mac_type == MAC_TYPE_EMAC) {
246 mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
247
248 /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
249 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
250 dmae->opcode = opcode;
251 dmae->src_addr_lo = (mac_addr +
252 EMAC_REG_EMAC_RX_STAT_AC) >> 2;
253 dmae->src_addr_hi = 0;
254 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
255 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
256 dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
257 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
258 dmae->comp_addr_hi = 0;
259 dmae->comp_val = 1;
260
261 /* EMAC_REG_EMAC_RX_STAT_AC_28 */
262 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
263 dmae->opcode = opcode;
264 dmae->src_addr_lo = (mac_addr +
265 EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
266 dmae->src_addr_hi = 0;
267 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
268 offsetof(struct emac_stats, rx_stat_falsecarriererrors));
269 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
270 offsetof(struct emac_stats, rx_stat_falsecarriererrors));
271 dmae->len = 1;
272 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
273 dmae->comp_addr_hi = 0;
274 dmae->comp_val = 1;
275
276 /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
277 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
278 dmae->opcode = opcode;
279 dmae->src_addr_lo = (mac_addr +
280 EMAC_REG_EMAC_TX_STAT_AC) >> 2;
281 dmae->src_addr_hi = 0;
282 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
283 offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
284 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
285 offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
286 dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
287 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
288 dmae->comp_addr_hi = 0;
289 dmae->comp_val = 1;
290 } else {
291 u32 tx_src_addr_lo, rx_src_addr_lo;
292 u16 rx_len, tx_len;
293
294 /* configure the params according to MAC type */
295 switch (bp->link_vars.mac_type) {
296 case MAC_TYPE_BMAC:
297 mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
298 NIG_REG_INGRESS_BMAC0_MEM);
299
300 /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
301 BIGMAC_REGISTER_TX_STAT_GTBYT */
302 if (CHIP_IS_E1x(bp)) {
303 tx_src_addr_lo = (mac_addr +
304 BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
305 tx_len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
306 BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
307 rx_src_addr_lo = (mac_addr +
308 BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
309 rx_len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
310 BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
311 } else {
312 tx_src_addr_lo = (mac_addr +
313 BIGMAC2_REGISTER_TX_STAT_GTPOK) >> 2;
314 tx_len = (8 + BIGMAC2_REGISTER_TX_STAT_GTBYT -
315 BIGMAC2_REGISTER_TX_STAT_GTPOK) >> 2;
316 rx_src_addr_lo = (mac_addr +
317 BIGMAC2_REGISTER_RX_STAT_GR64) >> 2;
318 rx_len = (8 + BIGMAC2_REGISTER_RX_STAT_GRIPJ -
319 BIGMAC2_REGISTER_RX_STAT_GR64) >> 2;
320 }
321 break;
322
323 case MAC_TYPE_UMAC: /* handled by MSTAT */
324 case MAC_TYPE_XMAC: /* handled by MSTAT */
325 default:
326 mac_addr = port ? GRCBASE_MSTAT1 : GRCBASE_MSTAT0;
327 tx_src_addr_lo = (mac_addr +
328 MSTAT_REG_TX_STAT_GTXPOK_LO) >> 2;
329 rx_src_addr_lo = (mac_addr +
330 MSTAT_REG_RX_STAT_GR64_LO) >> 2;
331 tx_len = sizeof(bp->slowpath->
332 mac_stats.mstat_stats.stats_tx) >> 2;
333 rx_len = sizeof(bp->slowpath->
334 mac_stats.mstat_stats.stats_rx) >> 2;
335 break;
336 }
337
338 /* TX stats */
339 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
340 dmae->opcode = opcode;
341 dmae->src_addr_lo = tx_src_addr_lo;
342 dmae->src_addr_hi = 0;
343 dmae->len = tx_len;
344 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
345 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
346 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
347 dmae->comp_addr_hi = 0;
348 dmae->comp_val = 1;
349
350 /* RX stats */
351 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
352 dmae->opcode = opcode;
353 dmae->src_addr_hi = 0;
354 dmae->src_addr_lo = rx_src_addr_lo;
355 dmae->dst_addr_lo =
356 U64_LO(bnx2x_sp_mapping(bp, mac_stats) + (tx_len << 2));
357 dmae->dst_addr_hi =
358 U64_HI(bnx2x_sp_mapping(bp, mac_stats) + (tx_len << 2));
359 dmae->len = rx_len;
360 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
361 dmae->comp_addr_hi = 0;
362 dmae->comp_val = 1;
363 }
364
365 /* NIG */
366 if (!CHIP_IS_E3(bp)) {
367 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
368 dmae->opcode = opcode;
369 dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :
370 NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;
371 dmae->src_addr_hi = 0;
372 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
373 offsetof(struct nig_stats, egress_mac_pkt0_lo));
374 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
375 offsetof(struct nig_stats, egress_mac_pkt0_lo));
376 dmae->len = (2*sizeof(u32)) >> 2;
377 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
378 dmae->comp_addr_hi = 0;
379 dmae->comp_val = 1;
380
381 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
382 dmae->opcode = opcode;
383 dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :
384 NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;
385 dmae->src_addr_hi = 0;
386 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
387 offsetof(struct nig_stats, egress_mac_pkt1_lo));
388 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
389 offsetof(struct nig_stats, egress_mac_pkt1_lo));
390 dmae->len = (2*sizeof(u32)) >> 2;
391 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
392 dmae->comp_addr_hi = 0;
393 dmae->comp_val = 1;
394 }
395
396 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
397 dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI,
398 true, DMAE_COMP_PCI);
399 dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
400 NIG_REG_STAT0_BRB_DISCARD) >> 2;
401 dmae->src_addr_hi = 0;
402 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats));
403 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats));
404 dmae->len = (sizeof(struct nig_stats) - 4*sizeof(u32)) >> 2;
405
406 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
407 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
408 dmae->comp_val = DMAE_COMP_VAL;
409
410 *stats_comp = 0;
411 }
412
413 static void bnx2x_func_stats_init(struct bnx2x *bp)
414 {
415 struct dmae_command *dmae = &bp->stats_dmae;
416 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
417
418 /* sanity */
419 if (!bp->func_stx) {
420 BNX2X_ERR("BUG!\n");
421 return;
422 }
423
424 bp->executer_idx = 0;
425 memset(dmae, 0, sizeof(struct dmae_command));
426
427 dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
428 true, DMAE_COMP_PCI);
429 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
430 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
431 dmae->dst_addr_lo = bp->func_stx >> 2;
432 dmae->dst_addr_hi = 0;
433 dmae->len = sizeof(struct host_func_stats) >> 2;
434 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
435 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
436 dmae->comp_val = DMAE_COMP_VAL;
437
438 *stats_comp = 0;
439 }
440
441 static void bnx2x_stats_start(struct bnx2x *bp)
442 {
443 if (bp->port.pmf)
444 bnx2x_port_stats_init(bp);
445
446 else if (bp->func_stx)
447 bnx2x_func_stats_init(bp);
448
449 bnx2x_hw_stats_post(bp);
450 bnx2x_storm_stats_post(bp);
451 }
452
453 static void bnx2x_stats_pmf_start(struct bnx2x *bp)
454 {
455 bnx2x_stats_comp(bp);
456 bnx2x_stats_pmf_update(bp);
457 bnx2x_stats_start(bp);
458 }
459
460 static void bnx2x_stats_restart(struct bnx2x *bp)
461 {
462 bnx2x_stats_comp(bp);
463 bnx2x_stats_start(bp);
464 }
465
466 static void bnx2x_bmac_stats_update(struct bnx2x *bp)
467 {
468 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
469 struct bnx2x_eth_stats *estats = &bp->eth_stats;
470 struct {
471 u32 lo;
472 u32 hi;
473 } diff;
474
475 if (CHIP_IS_E1x(bp)) {
476 struct bmac1_stats *new = bnx2x_sp(bp, mac_stats.bmac1_stats);
477
478 /* the macros below will use "bmac1_stats" type */
479 UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
480 UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
481 UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
482 UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
483 UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
484 UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
485 UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
486 UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
487 UPDATE_STAT64(rx_stat_grxpf, rx_stat_mac_xpf);
488
489 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
490 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
491 UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
492 UPDATE_STAT64(tx_stat_gt127,
493 tx_stat_etherstatspkts65octetsto127octets);
494 UPDATE_STAT64(tx_stat_gt255,
495 tx_stat_etherstatspkts128octetsto255octets);
496 UPDATE_STAT64(tx_stat_gt511,
497 tx_stat_etherstatspkts256octetsto511octets);
498 UPDATE_STAT64(tx_stat_gt1023,
499 tx_stat_etherstatspkts512octetsto1023octets);
500 UPDATE_STAT64(tx_stat_gt1518,
501 tx_stat_etherstatspkts1024octetsto1522octets);
502 UPDATE_STAT64(tx_stat_gt2047, tx_stat_mac_2047);
503 UPDATE_STAT64(tx_stat_gt4095, tx_stat_mac_4095);
504 UPDATE_STAT64(tx_stat_gt9216, tx_stat_mac_9216);
505 UPDATE_STAT64(tx_stat_gt16383, tx_stat_mac_16383);
506 UPDATE_STAT64(tx_stat_gterr,
507 tx_stat_dot3statsinternalmactransmiterrors);
508 UPDATE_STAT64(tx_stat_gtufl, tx_stat_mac_ufl);
509
510 } else {
511 struct bmac2_stats *new = bnx2x_sp(bp, mac_stats.bmac2_stats);
512
513 /* the macros below will use "bmac2_stats" type */
514 UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
515 UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
516 UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
517 UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
518 UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
519 UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
520 UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
521 UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
522 UPDATE_STAT64(rx_stat_grxpf, rx_stat_mac_xpf);
523 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
524 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
525 UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
526 UPDATE_STAT64(tx_stat_gt127,
527 tx_stat_etherstatspkts65octetsto127octets);
528 UPDATE_STAT64(tx_stat_gt255,
529 tx_stat_etherstatspkts128octetsto255octets);
530 UPDATE_STAT64(tx_stat_gt511,
531 tx_stat_etherstatspkts256octetsto511octets);
532 UPDATE_STAT64(tx_stat_gt1023,
533 tx_stat_etherstatspkts512octetsto1023octets);
534 UPDATE_STAT64(tx_stat_gt1518,
535 tx_stat_etherstatspkts1024octetsto1522octets);
536 UPDATE_STAT64(tx_stat_gt2047, tx_stat_mac_2047);
537 UPDATE_STAT64(tx_stat_gt4095, tx_stat_mac_4095);
538 UPDATE_STAT64(tx_stat_gt9216, tx_stat_mac_9216);
539 UPDATE_STAT64(tx_stat_gt16383, tx_stat_mac_16383);
540 UPDATE_STAT64(tx_stat_gterr,
541 tx_stat_dot3statsinternalmactransmiterrors);
542 UPDATE_STAT64(tx_stat_gtufl, tx_stat_mac_ufl);
543 }
544
545 estats->pause_frames_received_hi =
546 pstats->mac_stx[1].rx_stat_mac_xpf_hi;
547 estats->pause_frames_received_lo =
548 pstats->mac_stx[1].rx_stat_mac_xpf_lo;
549
550 estats->pause_frames_sent_hi =
551 pstats->mac_stx[1].tx_stat_outxoffsent_hi;
552 estats->pause_frames_sent_lo =
553 pstats->mac_stx[1].tx_stat_outxoffsent_lo;
554 }
555
556 static void bnx2x_mstat_stats_update(struct bnx2x *bp)
557 {
558 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
559 struct bnx2x_eth_stats *estats = &bp->eth_stats;
560
561 struct mstat_stats *new = bnx2x_sp(bp, mac_stats.mstat_stats);
562
563 ADD_STAT64(stats_rx.rx_grerb, rx_stat_ifhcinbadoctets);
564 ADD_STAT64(stats_rx.rx_grfcs, rx_stat_dot3statsfcserrors);
565 ADD_STAT64(stats_rx.rx_grund, rx_stat_etherstatsundersizepkts);
566 ADD_STAT64(stats_rx.rx_grovr, rx_stat_dot3statsframestoolong);
567 ADD_STAT64(stats_rx.rx_grfrg, rx_stat_etherstatsfragments);
568 ADD_STAT64(stats_rx.rx_grxcf, rx_stat_maccontrolframesreceived);
569 ADD_STAT64(stats_rx.rx_grxpf, rx_stat_xoffstateentered);
570 ADD_STAT64(stats_rx.rx_grxpf, rx_stat_mac_xpf);
571 ADD_STAT64(stats_tx.tx_gtxpf, tx_stat_outxoffsent);
572 ADD_STAT64(stats_tx.tx_gtxpf, tx_stat_flowcontroldone);
573
574
575 ADD_STAT64(stats_tx.tx_gt64, tx_stat_etherstatspkts64octets);
576 ADD_STAT64(stats_tx.tx_gt127,
577 tx_stat_etherstatspkts65octetsto127octets);
578 ADD_STAT64(stats_tx.tx_gt255,
579 tx_stat_etherstatspkts128octetsto255octets);
580 ADD_STAT64(stats_tx.tx_gt511,
581 tx_stat_etherstatspkts256octetsto511octets);
582 ADD_STAT64(stats_tx.tx_gt1023,
583 tx_stat_etherstatspkts512octetsto1023octets);
584 ADD_STAT64(stats_tx.tx_gt1518,
585 tx_stat_etherstatspkts1024octetsto1522octets);
586 ADD_STAT64(stats_tx.tx_gt2047, tx_stat_mac_2047);
587
588 ADD_STAT64(stats_tx.tx_gt4095, tx_stat_mac_4095);
589 ADD_STAT64(stats_tx.tx_gt9216, tx_stat_mac_9216);
590 ADD_STAT64(stats_tx.tx_gt16383, tx_stat_mac_16383);
591
592 ADD_STAT64(stats_tx.tx_gterr,
593 tx_stat_dot3statsinternalmactransmiterrors);
594 ADD_STAT64(stats_tx.tx_gtufl, tx_stat_mac_ufl);
595
596 ADD_64(estats->etherstatspkts1024octetsto1522octets_hi,
597 new->stats_tx.tx_gt1518_hi,
598 estats->etherstatspkts1024octetsto1522octets_lo,
599 new->stats_tx.tx_gt1518_lo);
600
601 ADD_64(estats->etherstatspktsover1522octets_hi,
602 new->stats_tx.tx_gt2047_hi,
603 estats->etherstatspktsover1522octets_lo,
604 new->stats_tx.tx_gt2047_lo);
605
606 ADD_64(estats->etherstatspktsover1522octets_hi,
607 new->stats_tx.tx_gt4095_hi,
608 estats->etherstatspktsover1522octets_lo,
609 new->stats_tx.tx_gt4095_lo);
610
611 ADD_64(estats->etherstatspktsover1522octets_hi,
612 new->stats_tx.tx_gt9216_hi,
613 estats->etherstatspktsover1522octets_lo,
614 new->stats_tx.tx_gt9216_lo);
615
616
617 ADD_64(estats->etherstatspktsover1522octets_hi,
618 new->stats_tx.tx_gt16383_hi,
619 estats->etherstatspktsover1522octets_lo,
620 new->stats_tx.tx_gt16383_lo);
621
622 estats->pause_frames_received_hi =
623 pstats->mac_stx[1].rx_stat_mac_xpf_hi;
624 estats->pause_frames_received_lo =
625 pstats->mac_stx[1].rx_stat_mac_xpf_lo;
626
627 estats->pause_frames_sent_hi =
628 pstats->mac_stx[1].tx_stat_outxoffsent_hi;
629 estats->pause_frames_sent_lo =
630 pstats->mac_stx[1].tx_stat_outxoffsent_lo;
631 }
632
633 static void bnx2x_emac_stats_update(struct bnx2x *bp)
634 {
635 struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac_stats);
636 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
637 struct bnx2x_eth_stats *estats = &bp->eth_stats;
638
639 UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);
640 UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);
641 UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);
642 UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);
643 UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);
644 UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);
645 UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);
646 UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);
647 UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);
648 UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);
649 UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);
650 UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);
651 UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);
652 UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);
653 UPDATE_EXTEND_STAT(tx_stat_outxonsent);
654 UPDATE_EXTEND_STAT(tx_stat_outxoffsent);
655 UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);
656 UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);
657 UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);
658 UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);
659 UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);
660 UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);
661 UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);
662 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);
663 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);
664 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);
665 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);
666 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);
667 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);
668 UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);
669 UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);
670
671 estats->pause_frames_received_hi =
672 pstats->mac_stx[1].rx_stat_xonpauseframesreceived_hi;
673 estats->pause_frames_received_lo =
674 pstats->mac_stx[1].rx_stat_xonpauseframesreceived_lo;
675 ADD_64(estats->pause_frames_received_hi,
676 pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_hi,
677 estats->pause_frames_received_lo,
678 pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_lo);
679
680 estats->pause_frames_sent_hi =
681 pstats->mac_stx[1].tx_stat_outxonsent_hi;
682 estats->pause_frames_sent_lo =
683 pstats->mac_stx[1].tx_stat_outxonsent_lo;
684 ADD_64(estats->pause_frames_sent_hi,
685 pstats->mac_stx[1].tx_stat_outxoffsent_hi,
686 estats->pause_frames_sent_lo,
687 pstats->mac_stx[1].tx_stat_outxoffsent_lo);
688 }
689
690 static int bnx2x_hw_stats_update(struct bnx2x *bp)
691 {
692 struct nig_stats *new = bnx2x_sp(bp, nig_stats);
693 struct nig_stats *old = &(bp->port.old_nig_stats);
694 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
695 struct bnx2x_eth_stats *estats = &bp->eth_stats;
696 struct {
697 u32 lo;
698 u32 hi;
699 } diff;
700
701 switch (bp->link_vars.mac_type) {
702 case MAC_TYPE_BMAC:
703 bnx2x_bmac_stats_update(bp);
704 break;
705
706 case MAC_TYPE_EMAC:
707 bnx2x_emac_stats_update(bp);
708 break;
709
710 case MAC_TYPE_UMAC:
711 case MAC_TYPE_XMAC:
712 bnx2x_mstat_stats_update(bp);
713 break;
714
715 case MAC_TYPE_NONE: /* unreached */
716 DP(BNX2X_MSG_STATS,
717 "stats updated by DMAE but no MAC active\n");
718 return -1;
719
720 default: /* unreached */
721 BNX2X_ERR("Unknown MAC type\n");
722 }
723
724 ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
725 new->brb_discard - old->brb_discard);
726 ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
727 new->brb_truncate - old->brb_truncate);
728
729 if (!CHIP_IS_E3(bp)) {
730 UPDATE_STAT64_NIG(egress_mac_pkt0,
731 etherstatspkts1024octetsto1522octets);
732 UPDATE_STAT64_NIG(egress_mac_pkt1,
733 etherstatspktsover1522octets);
734 }
735
736 memcpy(old, new, sizeof(struct nig_stats));
737
738 memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),
739 sizeof(struct mac_stx));
740 estats->brb_drop_hi = pstats->brb_drop_hi;
741 estats->brb_drop_lo = pstats->brb_drop_lo;
742
743 pstats->host_port_stats_start = ++pstats->host_port_stats_end;
744
745 if (!BP_NOMCP(bp)) {
746 u32 nig_timer_max =
747 SHMEM_RD(bp, port_mb[BP_PORT(bp)].stat_nig_timer);
748 if (nig_timer_max != estats->nig_timer_max) {
749 estats->nig_timer_max = nig_timer_max;
750 BNX2X_ERR("NIG timer max (%u)\n",
751 estats->nig_timer_max);
752 }
753 }
754
755 return 0;
756 }
757
758 static int bnx2x_storm_stats_update(struct bnx2x *bp)
759 {
760 struct tstorm_per_port_stats *tport =
761 &bp->fw_stats_data->port.tstorm_port_statistics;
762 struct tstorm_per_pf_stats *tfunc =
763 &bp->fw_stats_data->pf.tstorm_pf_statistics;
764 struct host_func_stats *fstats = bnx2x_sp(bp, func_stats);
765 struct bnx2x_eth_stats *estats = &bp->eth_stats;
766 struct stats_counter *counters = &bp->fw_stats_data->storm_counters;
767 int i;
768 u16 cur_stats_counter;
769
770 /* Make sure we use the value of the counter
771 * used for sending the last stats ramrod.
772 */
773 spin_lock_bh(&bp->stats_lock);
774 cur_stats_counter = bp->stats_counter - 1;
775 spin_unlock_bh(&bp->stats_lock);
776
777 /* are storm stats valid? */
778 if (le16_to_cpu(counters->xstats_counter) != cur_stats_counter) {
779 DP(BNX2X_MSG_STATS, "stats not updated by xstorm"
780 " xstorm counter (0x%x) != stats_counter (0x%x)\n",
781 le16_to_cpu(counters->xstats_counter), bp->stats_counter);
782 return -EAGAIN;
783 }
784
785 if (le16_to_cpu(counters->ustats_counter) != cur_stats_counter) {
786 DP(BNX2X_MSG_STATS, "stats not updated by ustorm"
787 " ustorm counter (0x%x) != stats_counter (0x%x)\n",
788 le16_to_cpu(counters->ustats_counter), bp->stats_counter);
789 return -EAGAIN;
790 }
791
792 if (le16_to_cpu(counters->cstats_counter) != cur_stats_counter) {
793 DP(BNX2X_MSG_STATS, "stats not updated by cstorm"
794 " cstorm counter (0x%x) != stats_counter (0x%x)\n",
795 le16_to_cpu(counters->cstats_counter), bp->stats_counter);
796 return -EAGAIN;
797 }
798
799 if (le16_to_cpu(counters->tstats_counter) != cur_stats_counter) {
800 DP(BNX2X_MSG_STATS, "stats not updated by tstorm"
801 " tstorm counter (0x%x) != stats_counter (0x%x)\n",
802 le16_to_cpu(counters->tstats_counter), bp->stats_counter);
803 return -EAGAIN;
804 }
805
806 memcpy(&(fstats->total_bytes_received_hi),
807 &(bnx2x_sp(bp, func_stats_base)->total_bytes_received_hi),
808 sizeof(struct host_func_stats) - 2*sizeof(u32));
809 estats->error_bytes_received_hi = 0;
810 estats->error_bytes_received_lo = 0;
811 estats->etherstatsoverrsizepkts_hi = 0;
812 estats->etherstatsoverrsizepkts_lo = 0;
813 estats->no_buff_discard_hi = 0;
814 estats->no_buff_discard_lo = 0;
815 estats->total_tpa_aggregations_hi = 0;
816 estats->total_tpa_aggregations_lo = 0;
817 estats->total_tpa_aggregated_frames_hi = 0;
818 estats->total_tpa_aggregated_frames_lo = 0;
819 estats->total_tpa_bytes_hi = 0;
820 estats->total_tpa_bytes_lo = 0;
821
822 for_each_eth_queue(bp, i) {
823 struct bnx2x_fastpath *fp = &bp->fp[i];
824 struct tstorm_per_queue_stats *tclient =
825 &bp->fw_stats_data->queue_stats[i].
826 tstorm_queue_statistics;
827 struct tstorm_per_queue_stats *old_tclient = &fp->old_tclient;
828 struct ustorm_per_queue_stats *uclient =
829 &bp->fw_stats_data->queue_stats[i].
830 ustorm_queue_statistics;
831 struct ustorm_per_queue_stats *old_uclient = &fp->old_uclient;
832 struct xstorm_per_queue_stats *xclient =
833 &bp->fw_stats_data->queue_stats[i].
834 xstorm_queue_statistics;
835 struct xstorm_per_queue_stats *old_xclient = &fp->old_xclient;
836 struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
837 u32 diff;
838
839 DP(BNX2X_MSG_STATS, "queue[%d]: ucast_sent 0x%x, "
840 "bcast_sent 0x%x mcast_sent 0x%x\n",
841 i, xclient->ucast_pkts_sent,
842 xclient->bcast_pkts_sent, xclient->mcast_pkts_sent);
843
844 DP(BNX2X_MSG_STATS, "---------------\n");
845
846 qstats->total_broadcast_bytes_received_hi =
847 le32_to_cpu(tclient->rcv_bcast_bytes.hi);
848 qstats->total_broadcast_bytes_received_lo =
849 le32_to_cpu(tclient->rcv_bcast_bytes.lo);
850
851 qstats->total_multicast_bytes_received_hi =
852 le32_to_cpu(tclient->rcv_mcast_bytes.hi);
853 qstats->total_multicast_bytes_received_lo =
854 le32_to_cpu(tclient->rcv_mcast_bytes.lo);
855
856 qstats->total_unicast_bytes_received_hi =
857 le32_to_cpu(tclient->rcv_ucast_bytes.hi);
858 qstats->total_unicast_bytes_received_lo =
859 le32_to_cpu(tclient->rcv_ucast_bytes.lo);
860
861 /*
862 * sum to total_bytes_received all
863 * unicast/multicast/broadcast
864 */
865 qstats->total_bytes_received_hi =
866 qstats->total_broadcast_bytes_received_hi;
867 qstats->total_bytes_received_lo =
868 qstats->total_broadcast_bytes_received_lo;
869
870 ADD_64(qstats->total_bytes_received_hi,
871 qstats->total_multicast_bytes_received_hi,
872 qstats->total_bytes_received_lo,
873 qstats->total_multicast_bytes_received_lo);
874
875 ADD_64(qstats->total_bytes_received_hi,
876 qstats->total_unicast_bytes_received_hi,
877 qstats->total_bytes_received_lo,
878 qstats->total_unicast_bytes_received_lo);
879
880 qstats->valid_bytes_received_hi =
881 qstats->total_bytes_received_hi;
882 qstats->valid_bytes_received_lo =
883 qstats->total_bytes_received_lo;
884
885
886 UPDATE_EXTEND_TSTAT(rcv_ucast_pkts,
887 total_unicast_packets_received);
888 UPDATE_EXTEND_TSTAT(rcv_mcast_pkts,
889 total_multicast_packets_received);
890 UPDATE_EXTEND_TSTAT(rcv_bcast_pkts,
891 total_broadcast_packets_received);
892 UPDATE_EXTEND_TSTAT(pkts_too_big_discard,
893 etherstatsoverrsizepkts);
894 UPDATE_EXTEND_TSTAT(no_buff_discard, no_buff_discard);
895
896 SUB_EXTEND_USTAT(ucast_no_buff_pkts,
897 total_unicast_packets_received);
898 SUB_EXTEND_USTAT(mcast_no_buff_pkts,
899 total_multicast_packets_received);
900 SUB_EXTEND_USTAT(bcast_no_buff_pkts,
901 total_broadcast_packets_received);
902 UPDATE_EXTEND_USTAT(ucast_no_buff_pkts, no_buff_discard);
903 UPDATE_EXTEND_USTAT(mcast_no_buff_pkts, no_buff_discard);
904 UPDATE_EXTEND_USTAT(bcast_no_buff_pkts, no_buff_discard);
905
906 qstats->total_broadcast_bytes_transmitted_hi =
907 le32_to_cpu(xclient->bcast_bytes_sent.hi);
908 qstats->total_broadcast_bytes_transmitted_lo =
909 le32_to_cpu(xclient->bcast_bytes_sent.lo);
910
911 qstats->total_multicast_bytes_transmitted_hi =
912 le32_to_cpu(xclient->mcast_bytes_sent.hi);
913 qstats->total_multicast_bytes_transmitted_lo =
914 le32_to_cpu(xclient->mcast_bytes_sent.lo);
915
916 qstats->total_unicast_bytes_transmitted_hi =
917 le32_to_cpu(xclient->ucast_bytes_sent.hi);
918 qstats->total_unicast_bytes_transmitted_lo =
919 le32_to_cpu(xclient->ucast_bytes_sent.lo);
920 /*
921 * sum to total_bytes_transmitted all
922 * unicast/multicast/broadcast
923 */
924 qstats->total_bytes_transmitted_hi =
925 qstats->total_unicast_bytes_transmitted_hi;
926 qstats->total_bytes_transmitted_lo =
927 qstats->total_unicast_bytes_transmitted_lo;
928
929 ADD_64(qstats->total_bytes_transmitted_hi,
930 qstats->total_broadcast_bytes_transmitted_hi,
931 qstats->total_bytes_transmitted_lo,
932 qstats->total_broadcast_bytes_transmitted_lo);
933
934 ADD_64(qstats->total_bytes_transmitted_hi,
935 qstats->total_multicast_bytes_transmitted_hi,
936 qstats->total_bytes_transmitted_lo,
937 qstats->total_multicast_bytes_transmitted_lo);
938
939 UPDATE_EXTEND_XSTAT(ucast_pkts_sent,
940 total_unicast_packets_transmitted);
941 UPDATE_EXTEND_XSTAT(mcast_pkts_sent,
942 total_multicast_packets_transmitted);
943 UPDATE_EXTEND_XSTAT(bcast_pkts_sent,
944 total_broadcast_packets_transmitted);
945
946 UPDATE_EXTEND_TSTAT(checksum_discard,
947 total_packets_received_checksum_discarded);
948 UPDATE_EXTEND_TSTAT(ttl0_discard,
949 total_packets_received_ttl0_discarded);
950
951 UPDATE_EXTEND_XSTAT(error_drop_pkts,
952 total_transmitted_dropped_packets_error);
953
954 /* TPA aggregations completed */
955 UPDATE_EXTEND_USTAT(coalesced_events, total_tpa_aggregations);
956 /* Number of network frames aggregated by TPA */
957 UPDATE_EXTEND_USTAT(coalesced_pkts,
958 total_tpa_aggregated_frames);
959 /* Total number of bytes in completed TPA aggregations */
960 qstats->total_tpa_bytes_lo =
961 le32_to_cpu(uclient->coalesced_bytes.lo);
962 qstats->total_tpa_bytes_hi =
963 le32_to_cpu(uclient->coalesced_bytes.hi);
964
965 /* TPA stats per-function */
966 ADD_64(estats->total_tpa_aggregations_hi,
967 qstats->total_tpa_aggregations_hi,
968 estats->total_tpa_aggregations_lo,
969 qstats->total_tpa_aggregations_lo);
970 ADD_64(estats->total_tpa_aggregated_frames_hi,
971 qstats->total_tpa_aggregated_frames_hi,
972 estats->total_tpa_aggregated_frames_lo,
973 qstats->total_tpa_aggregated_frames_lo);
974 ADD_64(estats->total_tpa_bytes_hi,
975 qstats->total_tpa_bytes_hi,
976 estats->total_tpa_bytes_lo,
977 qstats->total_tpa_bytes_lo);
978
979 ADD_64(fstats->total_bytes_received_hi,
980 qstats->total_bytes_received_hi,
981 fstats->total_bytes_received_lo,
982 qstats->total_bytes_received_lo);
983 ADD_64(fstats->total_bytes_transmitted_hi,
984 qstats->total_bytes_transmitted_hi,
985 fstats->total_bytes_transmitted_lo,
986 qstats->total_bytes_transmitted_lo);
987 ADD_64(fstats->total_unicast_packets_received_hi,
988 qstats->total_unicast_packets_received_hi,
989 fstats->total_unicast_packets_received_lo,
990 qstats->total_unicast_packets_received_lo);
991 ADD_64(fstats->total_multicast_packets_received_hi,
992 qstats->total_multicast_packets_received_hi,
993 fstats->total_multicast_packets_received_lo,
994 qstats->total_multicast_packets_received_lo);
995 ADD_64(fstats->total_broadcast_packets_received_hi,
996 qstats->total_broadcast_packets_received_hi,
997 fstats->total_broadcast_packets_received_lo,
998 qstats->total_broadcast_packets_received_lo);
999 ADD_64(fstats->total_unicast_packets_transmitted_hi,
1000 qstats->total_unicast_packets_transmitted_hi,
1001 fstats->total_unicast_packets_transmitted_lo,
1002 qstats->total_unicast_packets_transmitted_lo);
1003 ADD_64(fstats->total_multicast_packets_transmitted_hi,
1004 qstats->total_multicast_packets_transmitted_hi,
1005 fstats->total_multicast_packets_transmitted_lo,
1006 qstats->total_multicast_packets_transmitted_lo);
1007 ADD_64(fstats->total_broadcast_packets_transmitted_hi,
1008 qstats->total_broadcast_packets_transmitted_hi,
1009 fstats->total_broadcast_packets_transmitted_lo,
1010 qstats->total_broadcast_packets_transmitted_lo);
1011 ADD_64(fstats->valid_bytes_received_hi,
1012 qstats->valid_bytes_received_hi,
1013 fstats->valid_bytes_received_lo,
1014 qstats->valid_bytes_received_lo);
1015
1016 ADD_64(estats->etherstatsoverrsizepkts_hi,
1017 qstats->etherstatsoverrsizepkts_hi,
1018 estats->etherstatsoverrsizepkts_lo,
1019 qstats->etherstatsoverrsizepkts_lo);
1020 ADD_64(estats->no_buff_discard_hi, qstats->no_buff_discard_hi,
1021 estats->no_buff_discard_lo, qstats->no_buff_discard_lo);
1022 }
1023
1024 ADD_64(fstats->total_bytes_received_hi,
1025 estats->rx_stat_ifhcinbadoctets_hi,
1026 fstats->total_bytes_received_lo,
1027 estats->rx_stat_ifhcinbadoctets_lo);
1028
1029 ADD_64(fstats->total_bytes_received_hi,
1030 tfunc->rcv_error_bytes.hi,
1031 fstats->total_bytes_received_lo,
1032 tfunc->rcv_error_bytes.lo);
1033
1034 memcpy(estats, &(fstats->total_bytes_received_hi),
1035 sizeof(struct host_func_stats) - 2*sizeof(u32));
1036
1037 ADD_64(estats->error_bytes_received_hi,
1038 tfunc->rcv_error_bytes.hi,
1039 estats->error_bytes_received_lo,
1040 tfunc->rcv_error_bytes.lo);
1041
1042 ADD_64(estats->etherstatsoverrsizepkts_hi,
1043 estats->rx_stat_dot3statsframestoolong_hi,
1044 estats->etherstatsoverrsizepkts_lo,
1045 estats->rx_stat_dot3statsframestoolong_lo);
1046 ADD_64(estats->error_bytes_received_hi,
1047 estats->rx_stat_ifhcinbadoctets_hi,
1048 estats->error_bytes_received_lo,
1049 estats->rx_stat_ifhcinbadoctets_lo);
1050
1051 if (bp->port.pmf) {
1052 estats->mac_filter_discard =
1053 le32_to_cpu(tport->mac_filter_discard);
1054 estats->mf_tag_discard =
1055 le32_to_cpu(tport->mf_tag_discard);
1056 estats->brb_truncate_discard =
1057 le32_to_cpu(tport->brb_truncate_discard);
1058 estats->mac_discard = le32_to_cpu(tport->mac_discard);
1059 }
1060
1061 fstats->host_func_stats_start = ++fstats->host_func_stats_end;
1062
1063 bp->stats_pending = 0;
1064
1065 return 0;
1066 }
1067
1068 static void bnx2x_net_stats_update(struct bnx2x *bp)
1069 {
1070 struct bnx2x_eth_stats *estats = &bp->eth_stats;
1071 struct net_device_stats *nstats = &bp->dev->stats;
1072 unsigned long tmp;
1073 int i;
1074
1075 nstats->rx_packets =
1076 bnx2x_hilo(&estats->total_unicast_packets_received_hi) +
1077 bnx2x_hilo(&estats->total_multicast_packets_received_hi) +
1078 bnx2x_hilo(&estats->total_broadcast_packets_received_hi);
1079
1080 nstats->tx_packets =
1081 bnx2x_hilo(&estats->total_unicast_packets_transmitted_hi) +
1082 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) +
1083 bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi);
1084
1085 nstats->rx_bytes = bnx2x_hilo(&estats->total_bytes_received_hi);
1086
1087 nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi);
1088
1089 tmp = estats->mac_discard;
1090 for_each_rx_queue(bp, i)
1091 tmp += le32_to_cpu(bp->fp[i].old_tclient.checksum_discard);
1092 nstats->rx_dropped = tmp;
1093
1094 nstats->tx_dropped = 0;
1095
1096 nstats->multicast =
1097 bnx2x_hilo(&estats->total_multicast_packets_received_hi);
1098
1099 nstats->collisions =
1100 bnx2x_hilo(&estats->tx_stat_etherstatscollisions_hi);
1101
1102 nstats->rx_length_errors =
1103 bnx2x_hilo(&estats->rx_stat_etherstatsundersizepkts_hi) +
1104 bnx2x_hilo(&estats->etherstatsoverrsizepkts_hi);
1105 nstats->rx_over_errors = bnx2x_hilo(&estats->brb_drop_hi) +
1106 bnx2x_hilo(&estats->brb_truncate_hi);
1107 nstats->rx_crc_errors =
1108 bnx2x_hilo(&estats->rx_stat_dot3statsfcserrors_hi);
1109 nstats->rx_frame_errors =
1110 bnx2x_hilo(&estats->rx_stat_dot3statsalignmenterrors_hi);
1111 nstats->rx_fifo_errors = bnx2x_hilo(&estats->no_buff_discard_hi);
1112 nstats->rx_missed_errors = 0;
1113
1114 nstats->rx_errors = nstats->rx_length_errors +
1115 nstats->rx_over_errors +
1116 nstats->rx_crc_errors +
1117 nstats->rx_frame_errors +
1118 nstats->rx_fifo_errors +
1119 nstats->rx_missed_errors;
1120
1121 nstats->tx_aborted_errors =
1122 bnx2x_hilo(&estats->tx_stat_dot3statslatecollisions_hi) +
1123 bnx2x_hilo(&estats->tx_stat_dot3statsexcessivecollisions_hi);
1124 nstats->tx_carrier_errors =
1125 bnx2x_hilo(&estats->rx_stat_dot3statscarriersenseerrors_hi);
1126 nstats->tx_fifo_errors = 0;
1127 nstats->tx_heartbeat_errors = 0;
1128 nstats->tx_window_errors = 0;
1129
1130 nstats->tx_errors = nstats->tx_aborted_errors +
1131 nstats->tx_carrier_errors +
1132 bnx2x_hilo(&estats->tx_stat_dot3statsinternalmactransmiterrors_hi);
1133 }
1134
1135 static void bnx2x_drv_stats_update(struct bnx2x *bp)
1136 {
1137 struct bnx2x_eth_stats *estats = &bp->eth_stats;
1138 int i;
1139
1140 estats->driver_xoff = 0;
1141 estats->rx_err_discard_pkt = 0;
1142 estats->rx_skb_alloc_failed = 0;
1143 estats->hw_csum_err = 0;
1144 for_each_queue(bp, i) {
1145 struct bnx2x_eth_q_stats *qstats = &bp->fp[i].eth_q_stats;
1146
1147 estats->driver_xoff += qstats->driver_xoff;
1148 estats->rx_err_discard_pkt += qstats->rx_err_discard_pkt;
1149 estats->rx_skb_alloc_failed += qstats->rx_skb_alloc_failed;
1150 estats->hw_csum_err += qstats->hw_csum_err;
1151 }
1152 }
1153
1154 static bool bnx2x_edebug_stats_stopped(struct bnx2x *bp)
1155 {
1156 u32 val;
1157
1158 if (SHMEM2_HAS(bp, edebug_driver_if[1])) {
1159 val = SHMEM2_RD(bp, edebug_driver_if[1]);
1160
1161 if (val == EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT)
1162 return true;
1163 }
1164
1165 return false;
1166 }
1167
1168 static void bnx2x_stats_update(struct bnx2x *bp)
1169 {
1170 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
1171
1172 if (bnx2x_edebug_stats_stopped(bp))
1173 return;
1174
1175 if (*stats_comp != DMAE_COMP_VAL)
1176 return;
1177
1178 if (bp->port.pmf)
1179 bnx2x_hw_stats_update(bp);
1180
1181 if (bnx2x_storm_stats_update(bp) && (bp->stats_pending++ == 3)) {
1182 BNX2X_ERR("storm stats were not updated for 3 times\n");
1183 bnx2x_panic();
1184 return;
1185 }
1186
1187 bnx2x_net_stats_update(bp);
1188 bnx2x_drv_stats_update(bp);
1189
1190 if (netif_msg_timer(bp)) {
1191 struct bnx2x_eth_stats *estats = &bp->eth_stats;
1192 int i, cos;
1193
1194 netdev_dbg(bp->dev, "brb drops %u brb truncate %u\n",
1195 estats->brb_drop_lo, estats->brb_truncate_lo);
1196
1197 for_each_eth_queue(bp, i) {
1198 struct bnx2x_fastpath *fp = &bp->fp[i];
1199 struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
1200
1201 pr_debug("%s: rx usage(%4u) *rx_cons_sb(%u) rx pkt(%lu) rx calls(%lu %lu)\n",
1202 fp->name, (le16_to_cpu(*fp->rx_cons_sb) -
1203 fp->rx_comp_cons),
1204 le16_to_cpu(*fp->rx_cons_sb),
1205 bnx2x_hilo(&qstats->
1206 total_unicast_packets_received_hi),
1207 fp->rx_calls, fp->rx_pkt);
1208 }
1209
1210 for_each_eth_queue(bp, i) {
1211 struct bnx2x_fastpath *fp = &bp->fp[i];
1212 struct bnx2x_fp_txdata *txdata;
1213 struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
1214 struct netdev_queue *txq;
1215
1216 pr_debug("%s: tx pkt(%lu) (Xoff events %u)",
1217 fp->name,
1218 bnx2x_hilo(
1219 &qstats->total_unicast_packets_transmitted_hi),
1220 qstats->driver_xoff);
1221
1222 for_each_cos_in_tx_queue(fp, cos) {
1223 txdata = &fp->txdata[cos];
1224 txq = netdev_get_tx_queue(bp->dev,
1225 FP_COS_TO_TXQ(fp, cos));
1226
1227 pr_debug("%d: tx avail(%4u) *tx_cons_sb(%u) tx calls (%lu) %s\n",
1228 cos,
1229 bnx2x_tx_avail(bp, txdata),
1230 le16_to_cpu(*txdata->tx_cons_sb),
1231 txdata->tx_pkt,
1232 (netif_tx_queue_stopped(txq) ?
1233 "Xoff" : "Xon")
1234 );
1235 }
1236 }
1237 }
1238
1239 bnx2x_hw_stats_post(bp);
1240 bnx2x_storm_stats_post(bp);
1241 }
1242
1243 static void bnx2x_port_stats_stop(struct bnx2x *bp)
1244 {
1245 struct dmae_command *dmae;
1246 u32 opcode;
1247 int loader_idx = PMF_DMAE_C(bp);
1248 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
1249
1250 bp->executer_idx = 0;
1251
1252 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC, false, 0);
1253
1254 if (bp->port.port_stx) {
1255
1256 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
1257 if (bp->func_stx)
1258 dmae->opcode = bnx2x_dmae_opcode_add_comp(
1259 opcode, DMAE_COMP_GRC);
1260 else
1261 dmae->opcode = bnx2x_dmae_opcode_add_comp(
1262 opcode, DMAE_COMP_PCI);
1263
1264 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
1265 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
1266 dmae->dst_addr_lo = bp->port.port_stx >> 2;
1267 dmae->dst_addr_hi = 0;
1268 dmae->len = sizeof(struct host_port_stats) >> 2;
1269 if (bp->func_stx) {
1270 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
1271 dmae->comp_addr_hi = 0;
1272 dmae->comp_val = 1;
1273 } else {
1274 dmae->comp_addr_lo =
1275 U64_LO(bnx2x_sp_mapping(bp, stats_comp));
1276 dmae->comp_addr_hi =
1277 U64_HI(bnx2x_sp_mapping(bp, stats_comp));
1278 dmae->comp_val = DMAE_COMP_VAL;
1279
1280 *stats_comp = 0;
1281 }
1282 }
1283
1284 if (bp->func_stx) {
1285
1286 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
1287 dmae->opcode =
1288 bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);
1289 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
1290 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
1291 dmae->dst_addr_lo = bp->func_stx >> 2;
1292 dmae->dst_addr_hi = 0;
1293 dmae->len = sizeof(struct host_func_stats) >> 2;
1294 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
1295 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
1296 dmae->comp_val = DMAE_COMP_VAL;
1297
1298 *stats_comp = 0;
1299 }
1300 }
1301
1302 static void bnx2x_stats_stop(struct bnx2x *bp)
1303 {
1304 int update = 0;
1305
1306 bnx2x_stats_comp(bp);
1307
1308 if (bp->port.pmf)
1309 update = (bnx2x_hw_stats_update(bp) == 0);
1310
1311 update |= (bnx2x_storm_stats_update(bp) == 0);
1312
1313 if (update) {
1314 bnx2x_net_stats_update(bp);
1315
1316 if (bp->port.pmf)
1317 bnx2x_port_stats_stop(bp);
1318
1319 bnx2x_hw_stats_post(bp);
1320 bnx2x_stats_comp(bp);
1321 }
1322 }
1323
1324 static void bnx2x_stats_do_nothing(struct bnx2x *bp)
1325 {
1326 }
1327
1328 static const struct {
1329 void (*action)(struct bnx2x *bp);
1330 enum bnx2x_stats_state next_state;
1331 } bnx2x_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {
1332 /* state event */
1333 {
1334 /* DISABLED PMF */ {bnx2x_stats_pmf_update, STATS_STATE_DISABLED},
1335 /* LINK_UP */ {bnx2x_stats_start, STATS_STATE_ENABLED},
1336 /* UPDATE */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED},
1337 /* STOP */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED}
1338 },
1339 {
1340 /* ENABLED PMF */ {bnx2x_stats_pmf_start, STATS_STATE_ENABLED},
1341 /* LINK_UP */ {bnx2x_stats_restart, STATS_STATE_ENABLED},
1342 /* UPDATE */ {bnx2x_stats_update, STATS_STATE_ENABLED},
1343 /* STOP */ {bnx2x_stats_stop, STATS_STATE_DISABLED}
1344 }
1345 };
1346
1347 void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event)
1348 {
1349 enum bnx2x_stats_state state;
1350 if (unlikely(bp->panic))
1351 return;
1352 bnx2x_stats_stm[bp->stats_state][event].action(bp);
1353 spin_lock_bh(&bp->stats_lock);
1354 state = bp->stats_state;
1355 bp->stats_state = bnx2x_stats_stm[state][event].next_state;
1356 spin_unlock_bh(&bp->stats_lock);
1357
1358 if ((event != STATS_EVENT_UPDATE) || netif_msg_timer(bp))
1359 DP(BNX2X_MSG_STATS, "state %d -> event %d -> state %d\n",
1360 state, event, bp->stats_state);
1361 }
1362
1363 static void bnx2x_port_stats_base_init(struct bnx2x *bp)
1364 {
1365 struct dmae_command *dmae;
1366 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
1367
1368 /* sanity */
1369 if (!bp->port.pmf || !bp->port.port_stx) {
1370 BNX2X_ERR("BUG!\n");
1371 return;
1372 }
1373
1374 bp->executer_idx = 0;
1375
1376 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
1377 dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
1378 true, DMAE_COMP_PCI);
1379 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
1380 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
1381 dmae->dst_addr_lo = bp->port.port_stx >> 2;
1382 dmae->dst_addr_hi = 0;
1383 dmae->len = sizeof(struct host_port_stats) >> 2;
1384 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
1385 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
1386 dmae->comp_val = DMAE_COMP_VAL;
1387
1388 *stats_comp = 0;
1389 bnx2x_hw_stats_post(bp);
1390 bnx2x_stats_comp(bp);
1391 }
1392
1393 static void bnx2x_func_stats_base_init(struct bnx2x *bp)
1394 {
1395 int vn, vn_max = IS_MF(bp) ? BP_MAX_VN_NUM(bp) : E1VN_MAX;
1396 u32 func_stx;
1397
1398 /* sanity */
1399 if (!bp->port.pmf || !bp->func_stx) {
1400 BNX2X_ERR("BUG!\n");
1401 return;
1402 }
1403
1404 /* save our func_stx */
1405 func_stx = bp->func_stx;
1406
1407 for (vn = VN_0; vn < vn_max; vn++) {
1408 int mb_idx = BP_FW_MB_IDX_VN(bp, vn);
1409
1410 bp->func_stx = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_param);
1411 bnx2x_func_stats_init(bp);
1412 bnx2x_hw_stats_post(bp);
1413 bnx2x_stats_comp(bp);
1414 }
1415
1416 /* restore our func_stx */
1417 bp->func_stx = func_stx;
1418 }
1419
1420 static void bnx2x_func_stats_base_update(struct bnx2x *bp)
1421 {
1422 struct dmae_command *dmae = &bp->stats_dmae;
1423 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
1424
1425 /* sanity */
1426 if (!bp->func_stx) {
1427 BNX2X_ERR("BUG!\n");
1428 return;
1429 }
1430
1431 bp->executer_idx = 0;
1432 memset(dmae, 0, sizeof(struct dmae_command));
1433
1434 dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI,
1435 true, DMAE_COMP_PCI);
1436 dmae->src_addr_lo = bp->func_stx >> 2;
1437 dmae->src_addr_hi = 0;
1438 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats_base));
1439 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats_base));
1440 dmae->len = sizeof(struct host_func_stats) >> 2;
1441 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
1442 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
1443 dmae->comp_val = DMAE_COMP_VAL;
1444
1445 *stats_comp = 0;
1446 bnx2x_hw_stats_post(bp);
1447 bnx2x_stats_comp(bp);
1448 }
1449
1450 /**
1451 * This function will prepare the statistics ramrod data the way
1452 * we will only have to increment the statistics counter and
1453 * send the ramrod each time we have to.
1454 *
1455 * @param bp
1456 */
1457 static inline void bnx2x_prep_fw_stats_req(struct bnx2x *bp)
1458 {
1459 int i;
1460 struct stats_query_header *stats_hdr = &bp->fw_stats_req->hdr;
1461
1462 dma_addr_t cur_data_offset;
1463 struct stats_query_entry *cur_query_entry;
1464
1465 stats_hdr->cmd_num = bp->fw_stats_num;
1466 stats_hdr->drv_stats_counter = 0;
1467
1468 /* storm_counters struct contains the counters of completed
1469 * statistics requests per storm which are incremented by FW
1470 * each time it completes hadning a statistics ramrod. We will
1471 * check these counters in the timer handler and discard a
1472 * (statistics) ramrod completion.
1473 */
1474 cur_data_offset = bp->fw_stats_data_mapping +
1475 offsetof(struct bnx2x_fw_stats_data, storm_counters);
1476
1477 stats_hdr->stats_counters_addrs.hi =
1478 cpu_to_le32(U64_HI(cur_data_offset));
1479 stats_hdr->stats_counters_addrs.lo =
1480 cpu_to_le32(U64_LO(cur_data_offset));
1481
1482 /* prepare to the first stats ramrod (will be completed with
1483 * the counters equal to zero) - init counters to somethig different.
1484 */
1485 memset(&bp->fw_stats_data->storm_counters, 0xff,
1486 sizeof(struct stats_counter));
1487
1488 /**** Port FW statistics data ****/
1489 cur_data_offset = bp->fw_stats_data_mapping +
1490 offsetof(struct bnx2x_fw_stats_data, port);
1491
1492 cur_query_entry = &bp->fw_stats_req->query[BNX2X_PORT_QUERY_IDX];
1493
1494 cur_query_entry->kind = STATS_TYPE_PORT;
1495 /* For port query index is a DONT CARE */
1496 cur_query_entry->index = BP_PORT(bp);
1497 /* For port query funcID is a DONT CARE */
1498 cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
1499 cur_query_entry->address.hi = cpu_to_le32(U64_HI(cur_data_offset));
1500 cur_query_entry->address.lo = cpu_to_le32(U64_LO(cur_data_offset));
1501
1502 /**** PF FW statistics data ****/
1503 cur_data_offset = bp->fw_stats_data_mapping +
1504 offsetof(struct bnx2x_fw_stats_data, pf);
1505
1506 cur_query_entry = &bp->fw_stats_req->query[BNX2X_PF_QUERY_IDX];
1507
1508 cur_query_entry->kind = STATS_TYPE_PF;
1509 /* For PF query index is a DONT CARE */
1510 cur_query_entry->index = BP_PORT(bp);
1511 cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
1512 cur_query_entry->address.hi = cpu_to_le32(U64_HI(cur_data_offset));
1513 cur_query_entry->address.lo = cpu_to_le32(U64_LO(cur_data_offset));
1514
1515 /**** Clients' queries ****/
1516 cur_data_offset = bp->fw_stats_data_mapping +
1517 offsetof(struct bnx2x_fw_stats_data, queue_stats);
1518
1519 for_each_eth_queue(bp, i) {
1520 cur_query_entry =
1521 &bp->fw_stats_req->
1522 query[BNX2X_FIRST_QUEUE_QUERY_IDX + i];
1523
1524 cur_query_entry->kind = STATS_TYPE_QUEUE;
1525 cur_query_entry->index = bnx2x_stats_id(&bp->fp[i]);
1526 cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
1527 cur_query_entry->address.hi =
1528 cpu_to_le32(U64_HI(cur_data_offset));
1529 cur_query_entry->address.lo =
1530 cpu_to_le32(U64_LO(cur_data_offset));
1531
1532 cur_data_offset += sizeof(struct per_queue_stats);
1533 }
1534 }
1535
1536 void bnx2x_stats_init(struct bnx2x *bp)
1537 {
1538 int /*abs*/port = BP_PORT(bp);
1539 int mb_idx = BP_FW_MB_IDX(bp);
1540 int i;
1541
1542 bp->stats_pending = 0;
1543 bp->executer_idx = 0;
1544 bp->stats_counter = 0;
1545
1546 /* port and func stats for management */
1547 if (!BP_NOMCP(bp)) {
1548 bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx);
1549 bp->func_stx = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_param);
1550
1551 } else {
1552 bp->port.port_stx = 0;
1553 bp->func_stx = 0;
1554 }
1555 DP(BNX2X_MSG_STATS, "port_stx 0x%x func_stx 0x%x\n",
1556 bp->port.port_stx, bp->func_stx);
1557
1558 port = BP_PORT(bp);
1559 /* port stats */
1560 memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats));
1561 bp->port.old_nig_stats.brb_discard =
1562 REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
1563 bp->port.old_nig_stats.brb_truncate =
1564 REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
1565 if (!CHIP_IS_E3(bp)) {
1566 REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
1567 &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2);
1568 REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
1569 &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2);
1570 }
1571
1572 /* function stats */
1573 for_each_queue(bp, i) {
1574 struct bnx2x_fastpath *fp = &bp->fp[i];
1575
1576 memset(&fp->old_tclient, 0, sizeof(fp->old_tclient));
1577 memset(&fp->old_uclient, 0, sizeof(fp->old_uclient));
1578 memset(&fp->old_xclient, 0, sizeof(fp->old_xclient));
1579 memset(&fp->eth_q_stats, 0, sizeof(fp->eth_q_stats));
1580 }
1581
1582 /* Prepare statistics ramrod data */
1583 bnx2x_prep_fw_stats_req(bp);
1584
1585 memset(&bp->dev->stats, 0, sizeof(bp->dev->stats));
1586 memset(&bp->eth_stats, 0, sizeof(bp->eth_stats));
1587
1588 bp->stats_state = STATS_STATE_DISABLED;
1589
1590 if (bp->port.pmf) {
1591 if (bp->port.port_stx)
1592 bnx2x_port_stats_base_init(bp);
1593
1594 if (bp->func_stx)
1595 bnx2x_func_stats_base_init(bp);
1596
1597 } else if (bp->func_stx)
1598 bnx2x_func_stats_base_update(bp);
1599 }