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powerpc: use consistent types in mktree
[zen-stable.git] / drivers / ata / sata_sis.c
blob8f9833228619062825e00d625122b5bf6de6090a
1 /*
2 * sata_sis.c - Silicon Integrated Systems SATA
3 *
4 * Maintained by: Uwe Koziolek
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004 Uwe Koziolek
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware documentation available under NDA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/device.h>
41 #include <scsi/scsi_host.h>
42 #include <linux/libata.h>
43 #include "sis.h"
44
45 #define DRV_NAME "sata_sis"
46 #define DRV_VERSION "1.0"
47
48 enum {
49 sis_180 = 0,
50 SIS_SCR_PCI_BAR = 5,
51
52 /* PCI configuration registers */
53 SIS_GENCTL = 0x54, /* IDE General Control register */
54 SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
55 SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
56 SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */
57 SIS_PMR = 0x90, /* port mapping register */
58 SIS_PMR_COMBINED = 0x30,
59
60 /* random bits */
61 SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
62
63 GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
64 };
65
66 static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
67 static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
68 static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
69
70 static const struct pci_device_id sis_pci_tbl[] = {
71 { PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */
72 { PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */
73 { PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */
74 { PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */
75 { PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/680 */
76 { PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L/968/680 */
77
78 { } /* terminate list */
79 };
80
81 static struct pci_driver sis_pci_driver = {
82 .name = DRV_NAME,
83 .id_table = sis_pci_tbl,
84 .probe = sis_init_one,
85 .remove = ata_pci_remove_one,
86 };
87
88 static struct scsi_host_template sis_sht = {
89 ATA_BMDMA_SHT(DRV_NAME),
90 };
91
92 static struct ata_port_operations sis_ops = {
93 .inherits = &ata_bmdma_port_ops,
94 .scr_read = sis_scr_read,
95 .scr_write = sis_scr_write,
96 };
97
98 static const struct ata_port_info sis_port_info = {
99 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
100 .pio_mask = ATA_PIO4,
101 .mwdma_mask = ATA_MWDMA2,
102 .udma_mask = ATA_UDMA6,
103 .port_ops = &sis_ops,
104 };
105
106 MODULE_AUTHOR("Uwe Koziolek");
107 MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
108 MODULE_LICENSE("GPL");
109 MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
110 MODULE_VERSION(DRV_VERSION);
111
112 static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg)
113 {
114 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
115 unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
116 u8 pmr;
117
118 if (ap->port_no) {
119 switch (pdev->device) {
120 case 0x0180:
121 case 0x0181:
122 pci_read_config_byte(pdev, SIS_PMR, &pmr);
123 if ((pmr & SIS_PMR_COMBINED) == 0)
124 addr += SIS180_SATA1_OFS;
125 break;
126
127 case 0x0182:
128 case 0x0183:
129 case 0x1182:
130 addr += SIS182_SATA1_OFS;
131 break;
132 }
133 }
134 return addr;
135 }
136
137 static u32 sis_scr_cfg_read(struct ata_link *link,
138 unsigned int sc_reg, u32 *val)
139 {
140 struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
141 unsigned int cfg_addr = get_scr_cfg_addr(link->ap, sc_reg);
142 u32 val2 = 0;
143 u8 pmr;
144
145 if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
146 return -EINVAL;
147
148 pci_read_config_byte(pdev, SIS_PMR, &pmr);
149
150 pci_read_config_dword(pdev, cfg_addr, val);
151
152 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) ||
153 (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED))
154 pci_read_config_dword(pdev, cfg_addr+0x10, &val2);
155
156 *val |= val2;
157 *val &= 0xfffffffb; /* avoid problems with powerdowned ports */
158
159 return 0;
160 }
161
162 static int sis_scr_cfg_write(struct ata_link *link,
163 unsigned int sc_reg, u32 val)
164 {
165 struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
166 unsigned int cfg_addr = get_scr_cfg_addr(link->ap, sc_reg);
167 u8 pmr;
168
169 if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
170 return -EINVAL;
171
172 pci_read_config_byte(pdev, SIS_PMR, &pmr);
173
174 pci_write_config_dword(pdev, cfg_addr, val);
175
176 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) ||
177 (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED))
178 pci_write_config_dword(pdev, cfg_addr+0x10, val);
179
180 return 0;
181 }
182
183 static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
184 {
185 struct ata_port *ap = link->ap;
186 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
187 u8 pmr;
188
189 if (sc_reg > SCR_CONTROL)
190 return -EINVAL;
191
192 if (ap->flags & SIS_FLAG_CFGSCR)
193 return sis_scr_cfg_read(link, sc_reg, val);
194
195 pci_read_config_byte(pdev, SIS_PMR, &pmr);
196
197 *val = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4));
198
199 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) ||
200 (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED))
201 *val |= ioread32(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10);
202
203 *val &= 0xfffffffb;
204
205 return 0;
206 }
207
208 static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
209 {
210 struct ata_port *ap = link->ap;
211 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
212 u8 pmr;
213
214 if (sc_reg > SCR_CONTROL)
215 return -EINVAL;
216
217 pci_read_config_byte(pdev, SIS_PMR, &pmr);
218
219 if (ap->flags & SIS_FLAG_CFGSCR)
220 return sis_scr_cfg_write(link, sc_reg, val);
221 else {
222 iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4));
223 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) ||
224 (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED))
225 iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
226 return 0;
227 }
228 }
229
230 static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
231 {
232 static int printed_version;
233 struct ata_port_info pi = sis_port_info;
234 const struct ata_port_info *ppi[] = { &pi, &pi };
235 struct ata_host *host;
236 u32 genctl, val;
237 u8 pmr;
238 u8 port2_start = 0x20;
239 int rc;
240
241 if (!printed_version++)
242 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
243
244 rc = pcim_enable_device(pdev);
245 if (rc)
246 return rc;
247
248 /* check and see if the SCRs are in IO space or PCI cfg space */
249 pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
250 if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
251 pi.flags |= SIS_FLAG_CFGSCR;
252
253 /* if hardware thinks SCRs are in IO space, but there are
254 * no IO resources assigned, change to PCI cfg space.
255 */
256 if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
257 ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
258 (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
259 genctl &= ~GENCTL_IOMAPPED_SCR;
260 pci_write_config_dword(pdev, SIS_GENCTL, genctl);
261 pi.flags |= SIS_FLAG_CFGSCR;
262 }
263
264 pci_read_config_byte(pdev, SIS_PMR, &pmr);
265 switch (ent->device) {
266 case 0x0180:
267 case 0x0181:
268
269 /* The PATA-handling is provided by pata_sis */
270 switch (pmr & 0x30) {
271 case 0x10:
272 ppi[1] = &sis_info133_for_sata;
273 break;
274
275 case 0x30:
276 ppi[0] = &sis_info133_for_sata;
277 break;
278 }
279 if ((pmr & SIS_PMR_COMBINED) == 0) {
280 dev_printk(KERN_INFO, &pdev->dev,
281 "Detected SiS 180/181/964 chipset in SATA mode\n");
282 port2_start = 64;
283 } else {
284 dev_printk(KERN_INFO, &pdev->dev,
285 "Detected SiS 180/181 chipset in combined mode\n");
286 port2_start = 0;
287 pi.flags |= ATA_FLAG_SLAVE_POSS;
288 }
289 break;
290
291 case 0x0182:
292 case 0x0183:
293 pci_read_config_dword(pdev, 0x6C, &val);
294 if (val & (1L << 31)) {
295 dev_printk(KERN_INFO, &pdev->dev,
296 "Detected SiS 182/965 chipset\n");
297 pi.flags |= ATA_FLAG_SLAVE_POSS;
298 } else {
299 dev_printk(KERN_INFO, &pdev->dev,
300 "Detected SiS 182/965L chipset\n");
301 }
302 break;
303
304 case 0x1182:
305 dev_printk(KERN_INFO, &pdev->dev,
306 "Detected SiS 1182/966/680 SATA controller\n");
307 pi.flags |= ATA_FLAG_SLAVE_POSS;
308 break;
309
310 case 0x1183:
311 dev_printk(KERN_INFO, &pdev->dev,
312 "Detected SiS 1183/966/966L/968/680 controller in PATA mode\n");
313 ppi[0] = &sis_info133_for_sata;
314 ppi[1] = &sis_info133_for_sata;
315 break;
316 }
317
318 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
319 if (rc)
320 return rc;
321
322 if (!(pi.flags & SIS_FLAG_CFGSCR)) {
323 void __iomem *mmio;
324
325 rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME);
326 if (rc)
327 return rc;
328 mmio = host->iomap[SIS_SCR_PCI_BAR];
329
330 host->ports[0]->ioaddr.scr_addr = mmio;
331 host->ports[1]->ioaddr.scr_addr = mmio + port2_start;
332 }
333
334 pci_set_master(pdev);
335 pci_intx(pdev, 1);
336 return ata_host_activate(host, pdev->irq, ata_sff_interrupt,
337 IRQF_SHARED, &sis_sht);
338 }
339
340 static int __init sis_init(void)
341 {
342 return pci_register_driver(&sis_pci_driver);
343 }
344
345 static void __exit sis_exit(void)
346 {
347 pci_unregister_driver(&sis_pci_driver);
348 }
349
350 module_init(sis_init);
351 module_exit(sis_exit);