powerpc: use consistent types in mktree
[zen-stable.git] / drivers / gpu / drm / ati_pcigart.c
blob628eae3e9b8354a14ba1f74c2e6c21f01039085f
1 /**
2 * \file ati_pcigart.c
3 * ATI PCI GART support
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
8 /*
9 * Created: Wed Dec 13 21:52:19 2000 by gareth@valinux.com
11 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
12 * All Rights Reserved.
14 * Permission is hereby granted, free of charge, to any person obtaining a
15 * copy of this software and associated documentation files (the "Software"),
16 * to deal in the Software without restriction, including without limitation
17 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
18 * and/or sell copies of the Software, and to permit persons to whom the
19 * Software is furnished to do so, subject to the following conditions:
21 * The above copyright notice and this permission notice (including the next
22 * paragraph) shall be included in all copies or substantial portions of the
23 * Software.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
26 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
27 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
28 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
29 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
30 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
31 * DEALINGS IN THE SOFTWARE.
34 #include "drmP.h"
36 # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */
38 static int drm_ati_alloc_pcigart_table(struct drm_device *dev,
39 struct drm_ati_pcigart_info *gart_info)
41 gart_info->table_handle = drm_pci_alloc(dev, gart_info->table_size,
42 PAGE_SIZE,
43 gart_info->table_mask);
44 if (gart_info->table_handle == NULL)
45 return -ENOMEM;
47 return 0;
50 static void drm_ati_free_pcigart_table(struct drm_device *dev,
51 struct drm_ati_pcigart_info *gart_info)
53 drm_pci_free(dev, gart_info->table_handle);
54 gart_info->table_handle = NULL;
57 int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
59 struct drm_sg_mem *entry = dev->sg;
60 unsigned long pages;
61 int i;
62 int max_pages;
64 /* we need to support large memory configurations */
65 if (!entry) {
66 DRM_ERROR("no scatter/gather memory!\n");
67 return 0;
70 if (gart_info->bus_addr) {
72 max_pages = (gart_info->table_size / sizeof(u32));
73 pages = (entry->pages <= max_pages)
74 ? entry->pages : max_pages;
76 for (i = 0; i < pages; i++) {
77 if (!entry->busaddr[i])
78 break;
79 pci_unmap_page(dev->pdev, entry->busaddr[i],
80 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
83 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
84 gart_info->bus_addr = 0;
87 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN &&
88 gart_info->table_handle) {
89 drm_ati_free_pcigart_table(dev, gart_info);
92 return 1;
94 EXPORT_SYMBOL(drm_ati_pcigart_cleanup);
96 int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
98 struct drm_local_map *map = &gart_info->mapping;
99 struct drm_sg_mem *entry = dev->sg;
100 void *address = NULL;
101 unsigned long pages;
102 u32 *pci_gart = NULL, page_base, gart_idx;
103 dma_addr_t bus_address = 0;
104 int i, j, ret = 0;
105 int max_ati_pages, max_real_pages;
107 if (!entry) {
108 DRM_ERROR("no scatter/gather memory!\n");
109 goto done;
112 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
113 DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n");
115 ret = drm_ati_alloc_pcigart_table(dev, gart_info);
116 if (ret) {
117 DRM_ERROR("cannot allocate PCI GART page!\n");
118 goto done;
121 pci_gart = gart_info->table_handle->vaddr;
122 address = gart_info->table_handle->vaddr;
123 bus_address = gart_info->table_handle->busaddr;
124 } else {
125 address = gart_info->addr;
126 bus_address = gart_info->bus_addr;
127 DRM_DEBUG("PCI: Gart Table: VRAM %08LX mapped at %08lX\n",
128 (unsigned long long)bus_address,
129 (unsigned long)address);
133 max_ati_pages = (gart_info->table_size / sizeof(u32));
134 max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE);
135 pages = (entry->pages <= max_real_pages)
136 ? entry->pages : max_real_pages;
138 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
139 memset(pci_gart, 0, max_ati_pages * sizeof(u32));
140 } else {
141 memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u32));
144 gart_idx = 0;
145 for (i = 0; i < pages; i++) {
146 /* we need to support large memory configurations */
147 entry->busaddr[i] = pci_map_page(dev->pdev, entry->pagelist[i],
148 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
149 if (entry->busaddr[i] == 0) {
150 DRM_ERROR("unable to map PCIGART pages!\n");
151 drm_ati_pcigart_cleanup(dev, gart_info);
152 address = NULL;
153 bus_address = 0;
154 goto done;
156 page_base = (u32) entry->busaddr[i];
158 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
159 u32 val;
161 switch(gart_info->gart_reg_if) {
162 case DRM_ATI_GART_IGP:
163 val = page_base | 0xc;
164 break;
165 case DRM_ATI_GART_PCIE:
166 val = (page_base >> 8) | 0xc;
167 break;
168 default:
169 case DRM_ATI_GART_PCI:
170 val = page_base;
171 break;
173 if (gart_info->gart_table_location ==
174 DRM_ATI_GART_MAIN)
175 pci_gart[gart_idx] = cpu_to_le32(val);
176 else
177 DRM_WRITE32(map, gart_idx * sizeof(u32), val);
178 gart_idx++;
179 page_base += ATI_PCIGART_PAGE_SIZE;
182 ret = 1;
184 #if defined(__i386__) || defined(__x86_64__)
185 wbinvd();
186 #else
187 mb();
188 #endif
190 done:
191 gart_info->addr = address;
192 gart_info->bus_addr = bus_address;
193 return ret;
195 EXPORT_SYMBOL(drm_ati_pcigart_init);