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powerpc: use consistent types in mktree
[zen-stable.git] / drivers / media / video / pxa_camera.c
blob016bb45ba0c3e2f48e1801651c04dab25c262b74
1 /*
2 * V4L2 Driver for PXA camera host
3 *
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/io.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/errno.h>
19 #include <linux/fs.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mm.h>
23 #include <linux/moduleparam.h>
24 #include <linux/time.h>
25 #include <linux/version.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
29
30 #include <media/v4l2-common.h>
31 #include <media/v4l2-dev.h>
32 #include <media/videobuf-dma-sg.h>
33 #include <media/soc_camera.h>
34
35 #include <linux/videodev2.h>
36
37 #include <mach/dma.h>
38 #include <mach/camera.h>
39
40 #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
41 #define PXA_CAM_DRV_NAME "pxa27x-camera"
42
43 /* Camera Interface */
44 #define CICR0 0x0000
45 #define CICR1 0x0004
46 #define CICR2 0x0008
47 #define CICR3 0x000C
48 #define CICR4 0x0010
49 #define CISR 0x0014
50 #define CIFR 0x0018
51 #define CITOR 0x001C
52 #define CIBR0 0x0028
53 #define CIBR1 0x0030
54 #define CIBR2 0x0038
55
56 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
57 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
58 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
59 #define CICR0_ENB (1 << 28) /* Camera interface enable */
60 #define CICR0_DIS (1 << 27) /* Camera interface disable */
61 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
62 #define CICR0_TOM (1 << 9) /* Time-out mask */
63 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
64 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
65 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
66 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
67 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
68 #define CICR0_CDM (1 << 3) /* Disable-done mask */
69 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
70 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
71 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
72
73 #define CICR1_TBIT (1 << 31) /* Transparency bit */
74 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
75 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
76 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
77 #define CICR1_RGB_F (1 << 11) /* RGB format */
78 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
79 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
80 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
81 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
82 #define CICR1_DW (0x7 << 0) /* Data width mask */
83
84 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
85 wait count mask */
86 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
87 wait count mask */
88 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
89 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
90 wait count mask */
91 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
92 wait count mask */
93
94 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
95 wait count mask */
96 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
97 wait count mask */
98 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
99 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
100 wait count mask */
101 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
102
103 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
104 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
105 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
106 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
107 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
108 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
109 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
110 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
111
112 #define CISR_FTO (1 << 15) /* FIFO time-out */
113 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
114 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
115 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
116 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
117 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
118 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
119 #define CISR_EOL (1 << 8) /* End of line */
120 #define CISR_PAR_ERR (1 << 7) /* Parity error */
121 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
122 #define CISR_CDD (1 << 5) /* Camera interface disable done */
123 #define CISR_SOF (1 << 4) /* Start of frame */
124 #define CISR_EOF (1 << 3) /* End of frame */
125 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
126 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
127 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
128
129 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
130 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
131 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
132 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
133 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
134 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
135 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
136 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
137
138 #define CICR0_SIM_MP (0 << 24)
139 #define CICR0_SIM_SP (1 << 24)
140 #define CICR0_SIM_MS (2 << 24)
141 #define CICR0_SIM_EP (3 << 24)
142 #define CICR0_SIM_ES (4 << 24)
143
144 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
145 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
146 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
147 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
148 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
149
150 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
151 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
152 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
153 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
154 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
155
156 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
157 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
158 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
159 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
160
161 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
162 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
163 CICR0_EOFM | CICR0_FOM)
164
165 /*
166 * Structures
167 */
168 enum pxa_camera_active_dma {
169 DMA_Y = 0x1,
170 DMA_U = 0x2,
171 DMA_V = 0x4,
172 };
173
174 /* descriptor needed for the PXA DMA engine */
175 struct pxa_cam_dma {
176 dma_addr_t sg_dma;
177 struct pxa_dma_desc *sg_cpu;
178 size_t sg_size;
179 int sglen;
180 };
181
182 /* buffer for one video frame */
183 struct pxa_buffer {
184 /* common v4l buffer stuff -- must be first */
185 struct videobuf_buffer vb;
186
187 const struct soc_camera_data_format *fmt;
188
189 /* our descriptor lists for Y, U and V channels */
190 struct pxa_cam_dma dmas[3];
191
192 int inwork;
193
194 enum pxa_camera_active_dma active_dma;
195 };
196
197 struct pxa_camera_dev {
198 struct soc_camera_host soc_host;
199 /* PXA27x is only supposed to handle one camera on its Quick Capture
200 * interface. If anyone ever builds hardware to enable more than
201 * one camera, they will have to modify this driver too */
202 struct soc_camera_device *icd;
203 struct clk *clk;
204
205 unsigned int irq;
206 void __iomem *base;
207
208 int channels;
209 unsigned int dma_chans[3];
210
211 struct pxacamera_platform_data *pdata;
212 struct resource *res;
213 unsigned long platform_flags;
214 unsigned long ciclk;
215 unsigned long mclk;
216 u32 mclk_divisor;
217
218 struct list_head capture;
219
220 spinlock_t lock;
221
222 struct pxa_buffer *active;
223 struct pxa_dma_desc *sg_tail[3];
224
225 u32 save_cicr[5];
226 };
227
228 static const char *pxa_cam_driver_description = "PXA_Camera";
229
230 static unsigned int vid_limit = 16; /* Video memory limit, in Mb */
231
232 /*
233 * Videobuf operations
234 */
235 static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
236 unsigned int *size)
237 {
238 struct soc_camera_device *icd = vq->priv_data;
239
240 dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size);
241
242 *size = roundup(icd->width * icd->height *
243 ((icd->current_fmt->depth + 7) >> 3), 8);
244
245 if (0 == *count)
246 *count = 32;
247 while (*size * *count > vid_limit * 1024 * 1024)
248 (*count)--;
249
250 return 0;
251 }
252
253 static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
254 {
255 struct soc_camera_device *icd = vq->priv_data;
256 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
257 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
258 int i;
259
260 BUG_ON(in_interrupt());
261
262 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
263 &buf->vb, buf->vb.baddr, buf->vb.bsize);
264
265 /* This waits until this buffer is out of danger, i.e., until it is no
266 * longer in STATE_QUEUED or STATE_ACTIVE */
267 videobuf_waiton(&buf->vb, 0, 0);
268 videobuf_dma_unmap(vq, dma);
269 videobuf_dma_free(dma);
270
271 for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
272 if (buf->dmas[i].sg_cpu)
273 dma_free_coherent(ici->dev, buf->dmas[i].sg_size,
274 buf->dmas[i].sg_cpu,
275 buf->dmas[i].sg_dma);
276 buf->dmas[i].sg_cpu = NULL;
277 }
278
279 buf->vb.state = VIDEOBUF_NEEDS_INIT;
280 }
281
282 static int calculate_dma_sglen(struct scatterlist *sglist, int sglen,
283 int sg_first_ofs, int size)
284 {
285 int i, offset, dma_len, xfer_len;
286 struct scatterlist *sg;
287
288 offset = sg_first_ofs;
289 for_each_sg(sglist, sg, sglen, i) {
290 dma_len = sg_dma_len(sg);
291
292 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
293 xfer_len = roundup(min(dma_len - offset, size), 8);
294
295 size = max(0, size - xfer_len);
296 offset = 0;
297 if (size == 0)
298 break;
299 }
300
301 BUG_ON(size != 0);
302 return i + 1;
303 }
304
305 /**
306 * pxa_init_dma_channel - init dma descriptors
307 * @pcdev: pxa camera device
308 * @buf: pxa buffer to find pxa dma channel
309 * @dma: dma video buffer
310 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
311 * @cibr: camera Receive Buffer Register
312 * @size: bytes to transfer
313 * @sg_first: first element of sg_list
314 * @sg_first_ofs: offset in first element of sg_list
315 *
316 * Prepares the pxa dma descriptors to transfer one camera channel.
317 * Beware sg_first and sg_first_ofs are both input and output parameters.
318 *
319 * Returns 0 or -ENOMEM if no coherent memory is available
320 */
321 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
322 struct pxa_buffer *buf,
323 struct videobuf_dmabuf *dma, int channel,
324 int cibr, int size,
325 struct scatterlist **sg_first, int *sg_first_ofs)
326 {
327 struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
328 struct scatterlist *sg;
329 int i, offset, sglen;
330 int dma_len = 0, xfer_len = 0;
331
332 if (pxa_dma->sg_cpu)
333 dma_free_coherent(pcdev->soc_host.dev, pxa_dma->sg_size,
334 pxa_dma->sg_cpu, pxa_dma->sg_dma);
335
336 sglen = calculate_dma_sglen(*sg_first, dma->sglen,
337 *sg_first_ofs, size);
338
339 pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
340 pxa_dma->sg_cpu = dma_alloc_coherent(pcdev->soc_host.dev, pxa_dma->sg_size,
341 &pxa_dma->sg_dma, GFP_KERNEL);
342 if (!pxa_dma->sg_cpu)
343 return -ENOMEM;
344
345 pxa_dma->sglen = sglen;
346 offset = *sg_first_ofs;
347
348 dev_dbg(pcdev->soc_host.dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n",
349 *sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma);
350
351
352 for_each_sg(*sg_first, sg, sglen, i) {
353 dma_len = sg_dma_len(sg);
354
355 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
356 xfer_len = roundup(min(dma_len - offset, size), 8);
357
358 size = max(0, size - xfer_len);
359
360 pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
361 pxa_dma->sg_cpu[i].dtadr = sg_dma_address(sg) + offset;
362 pxa_dma->sg_cpu[i].dcmd =
363 DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
364 #ifdef DEBUG
365 if (!i)
366 pxa_dma->sg_cpu[i].dcmd |= DCMD_STARTIRQEN;
367 #endif
368 pxa_dma->sg_cpu[i].ddadr =
369 pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
370
371 dev_vdbg(pcdev->soc_host.dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n",
372 pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc),
373 sg_dma_address(sg) + offset, xfer_len);
374 offset = 0;
375
376 if (size == 0)
377 break;
378 }
379
380 pxa_dma->sg_cpu[sglen].ddadr = DDADR_STOP;
381 pxa_dma->sg_cpu[sglen].dcmd = DCMD_FLOWSRC | DCMD_BURST8 | DCMD_ENDIRQEN;
382
383 /*
384 * Handle 1 special case :
385 * - in 3 planes (YUV422P format), we might finish with xfer_len equal
386 * to dma_len (end on PAGE boundary). In this case, the sg element
387 * for next plane should be the next after the last used to store the
388 * last scatter gather RAM page
389 */
390 if (xfer_len >= dma_len) {
391 *sg_first_ofs = xfer_len - dma_len;
392 *sg_first = sg_next(sg);
393 } else {
394 *sg_first_ofs = xfer_len;
395 *sg_first = sg;
396 }
397
398 return 0;
399 }
400
401 static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
402 struct pxa_buffer *buf)
403 {
404 buf->active_dma = DMA_Y;
405 if (pcdev->channels == 3)
406 buf->active_dma |= DMA_U | DMA_V;
407 }
408
409 /*
410 * Please check the DMA prepared buffer structure in :
411 * Documentation/video4linux/pxa_camera.txt
412 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
413 * modification while DMA chain is running will work anyway.
414 */
415 static int pxa_videobuf_prepare(struct videobuf_queue *vq,
416 struct videobuf_buffer *vb, enum v4l2_field field)
417 {
418 struct soc_camera_device *icd = vq->priv_data;
419 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
420 struct pxa_camera_dev *pcdev = ici->priv;
421 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
422 int ret;
423 int size_y, size_u = 0, size_v = 0;
424
425 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
426 vb, vb->baddr, vb->bsize);
427
428 /* Added list head initialization on alloc */
429 WARN_ON(!list_empty(&vb->queue));
430
431 #ifdef DEBUG
432 /* This can be useful if you want to see if we actually fill
433 * the buffer with something */
434 memset((void *)vb->baddr, 0xaa, vb->bsize);
435 #endif
436
437 BUG_ON(NULL == icd->current_fmt);
438
439 /* I think, in buf_prepare you only have to protect global data,
440 * the actual buffer is yours */
441 buf->inwork = 1;
442
443 if (buf->fmt != icd->current_fmt ||
444 vb->width != icd->width ||
445 vb->height != icd->height ||
446 vb->field != field) {
447 buf->fmt = icd->current_fmt;
448 vb->width = icd->width;
449 vb->height = icd->height;
450 vb->field = field;
451 vb->state = VIDEOBUF_NEEDS_INIT;
452 }
453
454 vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3);
455 if (0 != vb->baddr && vb->bsize < vb->size) {
456 ret = -EINVAL;
457 goto out;
458 }
459
460 if (vb->state == VIDEOBUF_NEEDS_INIT) {
461 int size = vb->size;
462 int next_ofs = 0;
463 struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
464 struct scatterlist *sg;
465
466 ret = videobuf_iolock(vq, vb, NULL);
467 if (ret)
468 goto fail;
469
470 if (pcdev->channels == 3) {
471 size_y = size / 2;
472 size_u = size_v = size / 4;
473 } else {
474 size_y = size;
475 }
476
477 sg = dma->sglist;
478
479 /* init DMA for Y channel */
480 ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y,
481 &sg, &next_ofs);
482 if (ret) {
483 dev_err(pcdev->soc_host.dev,
484 "DMA initialization for Y/RGB failed\n");
485 goto fail;
486 }
487
488 /* init DMA for U channel */
489 if (size_u)
490 ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1,
491 size_u, &sg, &next_ofs);
492 if (ret) {
493 dev_err(pcdev->soc_host.dev,
494 "DMA initialization for U failed\n");
495 goto fail_u;
496 }
497
498 /* init DMA for V channel */
499 if (size_v)
500 ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2,
501 size_v, &sg, &next_ofs);
502 if (ret) {
503 dev_err(pcdev->soc_host.dev,
504 "DMA initialization for V failed\n");
505 goto fail_v;
506 }
507
508 vb->state = VIDEOBUF_PREPARED;
509 }
510
511 buf->inwork = 0;
512 pxa_videobuf_set_actdma(pcdev, buf);
513
514 return 0;
515
516 fail_v:
517 dma_free_coherent(pcdev->soc_host.dev, buf->dmas[1].sg_size,
518 buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
519 fail_u:
520 dma_free_coherent(pcdev->soc_host.dev, buf->dmas[0].sg_size,
521 buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
522 fail:
523 free_buffer(vq, buf);
524 out:
525 buf->inwork = 0;
526 return ret;
527 }
528
529 /**
530 * pxa_dma_start_channels - start DMA channel for active buffer
531 * @pcdev: pxa camera device
532 *
533 * Initialize DMA channels to the beginning of the active video buffer, and
534 * start these channels.
535 */
536 static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
537 {
538 int i;
539 struct pxa_buffer *active;
540
541 active = pcdev->active;
542
543 for (i = 0; i < pcdev->channels; i++) {
544 dev_dbg(pcdev->soc_host.dev, "%s (channel=%d) ddadr=%08x\n", __func__,
545 i, active->dmas[i].sg_dma);
546 DDADR(pcdev->dma_chans[i]) = active->dmas[i].sg_dma;
547 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
548 }
549 }
550
551 static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
552 {
553 int i;
554
555 for (i = 0; i < pcdev->channels; i++) {
556 dev_dbg(pcdev->soc_host.dev, "%s (channel=%d)\n", __func__, i);
557 DCSR(pcdev->dma_chans[i]) = 0;
558 }
559 }
560
561 static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
562 struct pxa_buffer *buf)
563 {
564 int i;
565 struct pxa_dma_desc *buf_last_desc;
566
567 for (i = 0; i < pcdev->channels; i++) {
568 buf_last_desc = buf->dmas[i].sg_cpu + buf->dmas[i].sglen;
569 buf_last_desc->ddadr = DDADR_STOP;
570
571 if (pcdev->sg_tail[i])
572 /* Link the new buffer to the old tail */
573 pcdev->sg_tail[i]->ddadr = buf->dmas[i].sg_dma;
574
575 /* Update the channel tail */
576 pcdev->sg_tail[i] = buf_last_desc;
577 }
578 }
579
580 /**
581 * pxa_camera_start_capture - start video capturing
582 * @pcdev: camera device
583 *
584 * Launch capturing. DMA channels should not be active yet. They should get
585 * activated at the end of frame interrupt, to capture only whole frames, and
586 * never begin the capture of a partial frame.
587 */
588 static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
589 {
590 unsigned long cicr0, cifr;
591
592 dev_dbg(pcdev->soc_host.dev, "%s\n", __func__);
593 /* Reset the FIFOs */
594 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
595 __raw_writel(cifr, pcdev->base + CIFR);
596 /* Enable End-Of-Frame Interrupt */
597 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
598 cicr0 &= ~CICR0_EOFM;
599 __raw_writel(cicr0, pcdev->base + CICR0);
600 }
601
602 static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
603 {
604 unsigned long cicr0;
605
606 pxa_dma_stop_channels(pcdev);
607
608 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
609 __raw_writel(cicr0, pcdev->base + CICR0);
610
611 pcdev->active = NULL;
612 dev_dbg(pcdev->soc_host.dev, "%s\n", __func__);
613 }
614
615 /* Called under spinlock_irqsave(&pcdev->lock, ...) */
616 static void pxa_videobuf_queue(struct videobuf_queue *vq,
617 struct videobuf_buffer *vb)
618 {
619 struct soc_camera_device *icd = vq->priv_data;
620 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
621 struct pxa_camera_dev *pcdev = ici->priv;
622 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
623
624 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d active=%p\n", __func__,
625 vb, vb->baddr, vb->bsize, pcdev->active);
626
627 list_add_tail(&vb->queue, &pcdev->capture);
628
629 vb->state = VIDEOBUF_ACTIVE;
630 pxa_dma_add_tail_buf(pcdev, buf);
631
632 if (!pcdev->active)
633 pxa_camera_start_capture(pcdev);
634 }
635
636 static void pxa_videobuf_release(struct videobuf_queue *vq,
637 struct videobuf_buffer *vb)
638 {
639 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
640 #ifdef DEBUG
641 struct soc_camera_device *icd = vq->priv_data;
642
643 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
644 vb, vb->baddr, vb->bsize);
645
646 switch (vb->state) {
647 case VIDEOBUF_ACTIVE:
648 dev_dbg(&icd->dev, "%s (active)\n", __func__);
649 break;
650 case VIDEOBUF_QUEUED:
651 dev_dbg(&icd->dev, "%s (queued)\n", __func__);
652 break;
653 case VIDEOBUF_PREPARED:
654 dev_dbg(&icd->dev, "%s (prepared)\n", __func__);
655 break;
656 default:
657 dev_dbg(&icd->dev, "%s (unknown)\n", __func__);
658 break;
659 }
660 #endif
661
662 free_buffer(vq, buf);
663 }
664
665 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
666 struct videobuf_buffer *vb,
667 struct pxa_buffer *buf)
668 {
669 int i;
670
671 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
672 list_del_init(&vb->queue);
673 vb->state = VIDEOBUF_DONE;
674 do_gettimeofday(&vb->ts);
675 vb->field_count++;
676 wake_up(&vb->done);
677 dev_dbg(pcdev->soc_host.dev, "%s dequeud buffer (vb=0x%p)\n", __func__, vb);
678
679 if (list_empty(&pcdev->capture)) {
680 pxa_camera_stop_capture(pcdev);
681 for (i = 0; i < pcdev->channels; i++)
682 pcdev->sg_tail[i] = NULL;
683 return;
684 }
685
686 pcdev->active = list_entry(pcdev->capture.next,
687 struct pxa_buffer, vb.queue);
688 }
689
690 /**
691 * pxa_camera_check_link_miss - check missed DMA linking
692 * @pcdev: camera device
693 *
694 * The DMA chaining is done with DMA running. This means a tiny temporal window
695 * remains, where a buffer is queued on the chain, while the chain is already
696 * stopped. This means the tailed buffer would never be transfered by DMA.
697 * This function restarts the capture for this corner case, where :
698 * - DADR() == DADDR_STOP
699 * - a videobuffer is queued on the pcdev->capture list
700 *
701 * Please check the "DMA hot chaining timeslice issue" in
702 * Documentation/video4linux/pxa_camera.txt
703 *
704 * Context: should only be called within the dma irq handler
705 */
706 static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev)
707 {
708 int i, is_dma_stopped = 1;
709
710 for (i = 0; i < pcdev->channels; i++)
711 if (DDADR(pcdev->dma_chans[i]) != DDADR_STOP)
712 is_dma_stopped = 0;
713 dev_dbg(pcdev->soc_host.dev, "%s : top queued buffer=%p, dma_stopped=%d\n",
714 __func__, pcdev->active, is_dma_stopped);
715 if (pcdev->active && is_dma_stopped)
716 pxa_camera_start_capture(pcdev);
717 }
718
719 static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
720 enum pxa_camera_active_dma act_dma)
721 {
722 struct pxa_buffer *buf;
723 unsigned long flags;
724 u32 status, camera_status, overrun;
725 struct videobuf_buffer *vb;
726
727 spin_lock_irqsave(&pcdev->lock, flags);
728
729 status = DCSR(channel);
730 DCSR(channel) = status;
731
732 camera_status = __raw_readl(pcdev->base + CISR);
733 overrun = CISR_IFO_0;
734 if (pcdev->channels == 3)
735 overrun |= CISR_IFO_1 | CISR_IFO_2;
736
737 if (status & DCSR_BUSERR) {
738 dev_err(pcdev->soc_host.dev, "DMA Bus Error IRQ!\n");
739 goto out;
740 }
741
742 if (!(status & (DCSR_ENDINTR | DCSR_STARTINTR))) {
743 dev_err(pcdev->soc_host.dev, "Unknown DMA IRQ source, "
744 "status: 0x%08x\n", status);
745 goto out;
746 }
747
748 /*
749 * pcdev->active should not be NULL in DMA irq handler.
750 *
751 * But there is one corner case : if capture was stopped due to an
752 * overrun of channel 1, and at that same channel 2 was completed.
753 *
754 * When handling the overrun in DMA irq for channel 1, we'll stop the
755 * capture and restart it (and thus set pcdev->active to NULL). But the
756 * DMA irq handler will already be pending for channel 2. So on entering
757 * the DMA irq handler for channel 2 there will be no active buffer, yet
758 * that is normal.
759 */
760 if (!pcdev->active)
761 goto out;
762
763 vb = &pcdev->active->vb;
764 buf = container_of(vb, struct pxa_buffer, vb);
765 WARN_ON(buf->inwork || list_empty(&vb->queue));
766
767 dev_dbg(pcdev->soc_host.dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n",
768 __func__, channel, status & DCSR_STARTINTR ? "SOF " : "",
769 status & DCSR_ENDINTR ? "EOF " : "", vb, DDADR(channel));
770
771 if (status & DCSR_ENDINTR) {
772 /*
773 * It's normal if the last frame creates an overrun, as there
774 * are no more DMA descriptors to fetch from QCI fifos
775 */
776 if (camera_status & overrun &&
777 !list_is_last(pcdev->capture.next, &pcdev->capture)) {
778 dev_dbg(pcdev->soc_host.dev, "FIFO overrun! CISR: %x\n",
779 camera_status);
780 pxa_camera_stop_capture(pcdev);
781 pxa_camera_start_capture(pcdev);
782 goto out;
783 }
784 buf->active_dma &= ~act_dma;
785 if (!buf->active_dma) {
786 pxa_camera_wakeup(pcdev, vb, buf);
787 pxa_camera_check_link_miss(pcdev);
788 }
789 }
790
791 out:
792 spin_unlock_irqrestore(&pcdev->lock, flags);
793 }
794
795 static void pxa_camera_dma_irq_y(int channel, void *data)
796 {
797 struct pxa_camera_dev *pcdev = data;
798 pxa_camera_dma_irq(channel, pcdev, DMA_Y);
799 }
800
801 static void pxa_camera_dma_irq_u(int channel, void *data)
802 {
803 struct pxa_camera_dev *pcdev = data;
804 pxa_camera_dma_irq(channel, pcdev, DMA_U);
805 }
806
807 static void pxa_camera_dma_irq_v(int channel, void *data)
808 {
809 struct pxa_camera_dev *pcdev = data;
810 pxa_camera_dma_irq(channel, pcdev, DMA_V);
811 }
812
813 static struct videobuf_queue_ops pxa_videobuf_ops = {
814 .buf_setup = pxa_videobuf_setup,
815 .buf_prepare = pxa_videobuf_prepare,
816 .buf_queue = pxa_videobuf_queue,
817 .buf_release = pxa_videobuf_release,
818 };
819
820 static void pxa_camera_init_videobuf(struct videobuf_queue *q,
821 struct soc_camera_device *icd)
822 {
823 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
824 struct pxa_camera_dev *pcdev = ici->priv;
825
826 /* We must pass NULL as dev pointer, then all pci_* dma operations
827 * transform to normal dma_* ones. */
828 videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock,
829 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
830 sizeof(struct pxa_buffer), icd);
831 }
832
833 static u32 mclk_get_divisor(struct pxa_camera_dev *pcdev)
834 {
835 unsigned long mclk = pcdev->mclk;
836 u32 div;
837 unsigned long lcdclk;
838
839 lcdclk = clk_get_rate(pcdev->clk);
840 pcdev->ciclk = lcdclk;
841
842 /* mclk <= ciclk / 4 (27.4.2) */
843 if (mclk > lcdclk / 4) {
844 mclk = lcdclk / 4;
845 dev_warn(pcdev->soc_host.dev, "Limiting master clock to %lu\n", mclk);
846 }
847
848 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
849 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
850
851 /* If we're not supplying MCLK, leave it at 0 */
852 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
853 pcdev->mclk = lcdclk / (2 * (div + 1));
854
855 dev_dbg(pcdev->soc_host.dev, "LCD clock %luHz, target freq %luHz, "
856 "divisor %u\n", lcdclk, mclk, div);
857
858 return div;
859 }
860
861 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
862 unsigned long pclk)
863 {
864 /* We want a timeout > 1 pixel time, not ">=" */
865 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
866
867 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
868 }
869
870 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
871 {
872 struct pxacamera_platform_data *pdata = pcdev->pdata;
873 u32 cicr4 = 0;
874
875 dev_dbg(pcdev->soc_host.dev, "Registered platform device at %p data %p\n",
876 pcdev, pdata);
877
878 if (pdata && pdata->init) {
879 dev_dbg(pcdev->soc_host.dev, "%s: Init gpios\n", __func__);
880 pdata->init(pcdev->soc_host.dev);
881 }
882
883 /* disable all interrupts */
884 __raw_writel(0x3ff, pcdev->base + CICR0);
885
886 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
887 cicr4 |= CICR4_PCLK_EN;
888 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
889 cicr4 |= CICR4_MCLK_EN;
890 if (pcdev->platform_flags & PXA_CAMERA_PCP)
891 cicr4 |= CICR4_PCP;
892 if (pcdev->platform_flags & PXA_CAMERA_HSP)
893 cicr4 |= CICR4_HSP;
894 if (pcdev->platform_flags & PXA_CAMERA_VSP)
895 cicr4 |= CICR4_VSP;
896
897 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
898
899 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
900 /* Initialise the timeout under the assumption pclk = mclk */
901 recalculate_fifo_timeout(pcdev, pcdev->mclk);
902 else
903 /* "Safe default" - 13MHz */
904 recalculate_fifo_timeout(pcdev, 13000000);
905
906 clk_enable(pcdev->clk);
907 }
908
909 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
910 {
911 clk_disable(pcdev->clk);
912 }
913
914 static irqreturn_t pxa_camera_irq(int irq, void *data)
915 {
916 struct pxa_camera_dev *pcdev = data;
917 unsigned long status, cicr0;
918 struct pxa_buffer *buf;
919 struct videobuf_buffer *vb;
920
921 status = __raw_readl(pcdev->base + CISR);
922 dev_dbg(pcdev->soc_host.dev, "Camera interrupt status 0x%lx\n", status);
923
924 if (!status)
925 return IRQ_NONE;
926
927 __raw_writel(status, pcdev->base + CISR);
928
929 if (status & CISR_EOF) {
930 pcdev->active = list_first_entry(&pcdev->capture,
931 struct pxa_buffer, vb.queue);
932 vb = &pcdev->active->vb;
933 buf = container_of(vb, struct pxa_buffer, vb);
934 pxa_videobuf_set_actdma(pcdev, buf);
935
936 pxa_dma_start_channels(pcdev);
937
938 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
939 __raw_writel(cicr0, pcdev->base + CICR0);
940 }
941
942 return IRQ_HANDLED;
943 }
944
945 /*
946 * The following two functions absolutely depend on the fact, that
947 * there can be only one camera on PXA quick capture interface
948 * Called with .video_lock held
949 */
950 static int pxa_camera_add_device(struct soc_camera_device *icd)
951 {
952 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
953 struct pxa_camera_dev *pcdev = ici->priv;
954 int ret;
955
956 if (pcdev->icd) {
957 ret = -EBUSY;
958 goto ebusy;
959 }
960
961 dev_info(&icd->dev, "PXA Camera driver attached to camera %d\n",
962 icd->devnum);
963
964 pxa_camera_activate(pcdev);
965 ret = icd->ops->init(icd);
966
967 if (!ret)
968 pcdev->icd = icd;
969
970 ebusy:
971 return ret;
972 }
973
974 /* Called with .video_lock held */
975 static void pxa_camera_remove_device(struct soc_camera_device *icd)
976 {
977 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
978 struct pxa_camera_dev *pcdev = ici->priv;
979
980 BUG_ON(icd != pcdev->icd);
981
982 dev_info(&icd->dev, "PXA Camera driver detached from camera %d\n",
983 icd->devnum);
984
985 /* disable capture, disable interrupts */
986 __raw_writel(0x3ff, pcdev->base + CICR0);
987
988 /* Stop DMA engine */
989 DCSR(pcdev->dma_chans[0]) = 0;
990 DCSR(pcdev->dma_chans[1]) = 0;
991 DCSR(pcdev->dma_chans[2]) = 0;
992
993 icd->ops->release(icd);
994
995 pxa_camera_deactivate(pcdev);
996
997 pcdev->icd = NULL;
998 }
999
1000 static int test_platform_param(struct pxa_camera_dev *pcdev,
1001 unsigned char buswidth, unsigned long *flags)
1002 {
1003 /*
1004 * Platform specified synchronization and pixel clock polarities are
1005 * only a recommendation and are only used during probing. The PXA270
1006 * quick capture interface supports both.
1007 */
1008 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1009 SOCAM_MASTER : SOCAM_SLAVE) |
1010 SOCAM_HSYNC_ACTIVE_HIGH |
1011 SOCAM_HSYNC_ACTIVE_LOW |
1012 SOCAM_VSYNC_ACTIVE_HIGH |
1013 SOCAM_VSYNC_ACTIVE_LOW |
1014 SOCAM_DATA_ACTIVE_HIGH |
1015 SOCAM_PCLK_SAMPLE_RISING |
1016 SOCAM_PCLK_SAMPLE_FALLING;
1017
1018 /* If requested data width is supported by the platform, use it */
1019 switch (buswidth) {
1020 case 10:
1021 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10))
1022 return -EINVAL;
1023 *flags |= SOCAM_DATAWIDTH_10;
1024 break;
1025 case 9:
1026 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9))
1027 return -EINVAL;
1028 *flags |= SOCAM_DATAWIDTH_9;
1029 break;
1030 case 8:
1031 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8))
1032 return -EINVAL;
1033 *flags |= SOCAM_DATAWIDTH_8;
1034 break;
1035 default:
1036 return -EINVAL;
1037 }
1038
1039 return 0;
1040 }
1041
1042 static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
1043 {
1044 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1045 struct pxa_camera_dev *pcdev = ici->priv;
1046 unsigned long dw, bpp, bus_flags, camera_flags, common_flags;
1047 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0;
1048 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
1049
1050 if (ret < 0)
1051 return ret;
1052
1053 camera_flags = icd->ops->query_bus_param(icd);
1054
1055 common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
1056 if (!common_flags)
1057 return -EINVAL;
1058
1059 pcdev->channels = 1;
1060
1061 /* Make choises, based on platform preferences */
1062 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
1063 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
1064 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1065 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
1066 else
1067 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
1068 }
1069
1070 if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
1071 (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
1072 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1073 common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
1074 else
1075 common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
1076 }
1077
1078 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
1079 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
1080 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1081 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
1082 else
1083 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
1084 }
1085
1086 ret = icd->ops->set_bus_param(icd, common_flags);
1087 if (ret < 0)
1088 return ret;
1089
1090 /* Datawidth is now guaranteed to be equal to one of the three values.
1091 * We fix bit-per-pixel equal to data-width... */
1092 switch (common_flags & SOCAM_DATAWIDTH_MASK) {
1093 case SOCAM_DATAWIDTH_10:
1094 dw = 4;
1095 bpp = 0x40;
1096 break;
1097 case SOCAM_DATAWIDTH_9:
1098 dw = 3;
1099 bpp = 0x20;
1100 break;
1101 default:
1102 /* Actually it can only be 8 now,
1103 * default is just to silence compiler warnings */
1104 case SOCAM_DATAWIDTH_8:
1105 dw = 2;
1106 bpp = 0;
1107 }
1108
1109 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1110 cicr4 |= CICR4_PCLK_EN;
1111 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1112 cicr4 |= CICR4_MCLK_EN;
1113 if (common_flags & SOCAM_PCLK_SAMPLE_FALLING)
1114 cicr4 |= CICR4_PCP;
1115 if (common_flags & SOCAM_HSYNC_ACTIVE_LOW)
1116 cicr4 |= CICR4_HSP;
1117 if (common_flags & SOCAM_VSYNC_ACTIVE_LOW)
1118 cicr4 |= CICR4_VSP;
1119
1120 cicr0 = __raw_readl(pcdev->base + CICR0);
1121 if (cicr0 & CICR0_ENB)
1122 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1123
1124 cicr1 = CICR1_PPL_VAL(icd->width - 1) | bpp | dw;
1125
1126 switch (pixfmt) {
1127 case V4L2_PIX_FMT_YUV422P:
1128 pcdev->channels = 3;
1129 cicr1 |= CICR1_YCBCR_F;
1130 /*
1131 * Normally, pxa bus wants as input UYVY format. We allow all
1132 * reorderings of the YUV422 format, as no processing is done,
1133 * and the YUV stream is just passed through without any
1134 * transformation. Note that UYVY is the only format that
1135 * should be used if pxa framebuffer Overlay2 is used.
1136 */
1137 case V4L2_PIX_FMT_UYVY:
1138 case V4L2_PIX_FMT_VYUY:
1139 case V4L2_PIX_FMT_YUYV:
1140 case V4L2_PIX_FMT_YVYU:
1141 cicr1 |= CICR1_COLOR_SP_VAL(2);
1142 break;
1143 case V4L2_PIX_FMT_RGB555:
1144 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1145 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1146 break;
1147 case V4L2_PIX_FMT_RGB565:
1148 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1149 break;
1150 }
1151
1152 cicr2 = 0;
1153 cicr3 = CICR3_LPF_VAL(icd->height - 1) |
1154 CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top));
1155 cicr4 |= pcdev->mclk_divisor;
1156
1157 __raw_writel(cicr1, pcdev->base + CICR1);
1158 __raw_writel(cicr2, pcdev->base + CICR2);
1159 __raw_writel(cicr3, pcdev->base + CICR3);
1160 __raw_writel(cicr4, pcdev->base + CICR4);
1161
1162 /* CIF interrupts are not used, only DMA */
1163 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1164 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1165 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1166 __raw_writel(cicr0, pcdev->base + CICR0);
1167
1168 return 0;
1169 }
1170
1171 static int pxa_camera_try_bus_param(struct soc_camera_device *icd,
1172 unsigned char buswidth)
1173 {
1174 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1175 struct pxa_camera_dev *pcdev = ici->priv;
1176 unsigned long bus_flags, camera_flags;
1177 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1178
1179 if (ret < 0)
1180 return ret;
1181
1182 camera_flags = icd->ops->query_bus_param(icd);
1183
1184 return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL;
1185 }
1186
1187 static const struct soc_camera_data_format pxa_camera_formats[] = {
1188 {
1189 .name = "Planar YUV422 16 bit",
1190 .depth = 16,
1191 .fourcc = V4L2_PIX_FMT_YUV422P,
1192 .colorspace = V4L2_COLORSPACE_JPEG,
1193 },
1194 };
1195
1196 static bool buswidth_supported(struct soc_camera_device *icd, int depth)
1197 {
1198 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1199 struct pxa_camera_dev *pcdev = ici->priv;
1200
1201 switch (depth) {
1202 case 8:
1203 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8);
1204 case 9:
1205 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9);
1206 case 10:
1207 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10);
1208 }
1209 return false;
1210 }
1211
1212 static int required_buswidth(const struct soc_camera_data_format *fmt)
1213 {
1214 switch (fmt->fourcc) {
1215 case V4L2_PIX_FMT_UYVY:
1216 case V4L2_PIX_FMT_VYUY:
1217 case V4L2_PIX_FMT_YUYV:
1218 case V4L2_PIX_FMT_YVYU:
1219 case V4L2_PIX_FMT_RGB565:
1220 case V4L2_PIX_FMT_RGB555:
1221 return 8;
1222 default:
1223 return fmt->depth;
1224 }
1225 }
1226
1227 static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx,
1228 struct soc_camera_format_xlate *xlate)
1229 {
1230 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1231 int formats = 0, buswidth, ret;
1232
1233 buswidth = required_buswidth(icd->formats + idx);
1234
1235 if (!buswidth_supported(icd, buswidth))
1236 return 0;
1237
1238 ret = pxa_camera_try_bus_param(icd, buswidth);
1239 if (ret < 0)
1240 return 0;
1241
1242 switch (icd->formats[idx].fourcc) {
1243 case V4L2_PIX_FMT_UYVY:
1244 formats++;
1245 if (xlate) {
1246 xlate->host_fmt = &pxa_camera_formats[0];
1247 xlate->cam_fmt = icd->formats + idx;
1248 xlate->buswidth = buswidth;
1249 xlate++;
1250 dev_dbg(ici->dev, "Providing format %s using %s\n",
1251 pxa_camera_formats[0].name,
1252 icd->formats[idx].name);
1253 }
1254 case V4L2_PIX_FMT_VYUY:
1255 case V4L2_PIX_FMT_YUYV:
1256 case V4L2_PIX_FMT_YVYU:
1257 case V4L2_PIX_FMT_RGB565:
1258 case V4L2_PIX_FMT_RGB555:
1259 formats++;
1260 if (xlate) {
1261 xlate->host_fmt = icd->formats + idx;
1262 xlate->cam_fmt = icd->formats + idx;
1263 xlate->buswidth = buswidth;
1264 xlate++;
1265 dev_dbg(ici->dev, "Providing format %s packed\n",
1266 icd->formats[idx].name);
1267 }
1268 break;
1269 default:
1270 /* Generic pass-through */
1271 formats++;
1272 if (xlate) {
1273 xlate->host_fmt = icd->formats + idx;
1274 xlate->cam_fmt = icd->formats + idx;
1275 xlate->buswidth = icd->formats[idx].depth;
1276 xlate++;
1277 dev_dbg(ici->dev,
1278 "Providing format %s in pass-through mode\n",
1279 icd->formats[idx].name);
1280 }
1281 }
1282
1283 return formats;
1284 }
1285
1286 static int pxa_camera_set_crop(struct soc_camera_device *icd,
1287 struct v4l2_rect *rect)
1288 {
1289 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1290 struct pxa_camera_dev *pcdev = ici->priv;
1291 struct soc_camera_sense sense = {
1292 .master_clock = pcdev->mclk,
1293 .pixel_clock_max = pcdev->ciclk / 4,
1294 };
1295 int ret;
1296
1297 /* If PCLK is used to latch data from the sensor, check sense */
1298 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1299 icd->sense = &sense;
1300
1301 ret = icd->ops->set_crop(icd, rect);
1302
1303 icd->sense = NULL;
1304
1305 if (ret < 0) {
1306 dev_warn(ici->dev, "Failed to crop to %ux%u@%u:%u\n",
1307 rect->width, rect->height, rect->left, rect->top);
1308 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1309 if (sense.pixel_clock > sense.pixel_clock_max) {
1310 dev_err(ici->dev,
1311 "pixel clock %lu set by the camera too high!",
1312 sense.pixel_clock);
1313 return -EIO;
1314 }
1315 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1316 }
1317
1318 return ret;
1319 }
1320
1321 static int pxa_camera_set_fmt(struct soc_camera_device *icd,
1322 struct v4l2_format *f)
1323 {
1324 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1325 struct pxa_camera_dev *pcdev = ici->priv;
1326 const struct soc_camera_data_format *cam_fmt = NULL;
1327 const struct soc_camera_format_xlate *xlate = NULL;
1328 struct soc_camera_sense sense = {
1329 .master_clock = pcdev->mclk,
1330 .pixel_clock_max = pcdev->ciclk / 4,
1331 };
1332 struct v4l2_pix_format *pix = &f->fmt.pix;
1333 struct v4l2_format cam_f = *f;
1334 int ret;
1335
1336 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1337 if (!xlate) {
1338 dev_warn(ici->dev, "Format %x not found\n", pix->pixelformat);
1339 return -EINVAL;
1340 }
1341
1342 cam_fmt = xlate->cam_fmt;
1343
1344 /* If PCLK is used to latch data from the sensor, check sense */
1345 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1346 icd->sense = &sense;
1347
1348 cam_f.fmt.pix.pixelformat = cam_fmt->fourcc;
1349 ret = icd->ops->set_fmt(icd, &cam_f);
1350
1351 icd->sense = NULL;
1352
1353 if (ret < 0) {
1354 dev_warn(ici->dev, "Failed to configure for format %x\n",
1355 pix->pixelformat);
1356 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1357 if (sense.pixel_clock > sense.pixel_clock_max) {
1358 dev_err(ici->dev,
1359 "pixel clock %lu set by the camera too high!",
1360 sense.pixel_clock);
1361 return -EIO;
1362 }
1363 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1364 }
1365
1366 if (!ret) {
1367 icd->buswidth = xlate->buswidth;
1368 icd->current_fmt = xlate->host_fmt;
1369 }
1370
1371 return ret;
1372 }
1373
1374 static int pxa_camera_try_fmt(struct soc_camera_device *icd,
1375 struct v4l2_format *f)
1376 {
1377 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1378 const struct soc_camera_format_xlate *xlate;
1379 struct v4l2_pix_format *pix = &f->fmt.pix;
1380 __u32 pixfmt = pix->pixelformat;
1381 enum v4l2_field field;
1382 int ret;
1383
1384 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1385 if (!xlate) {
1386 dev_warn(ici->dev, "Format %x not found\n", pixfmt);
1387 return -EINVAL;
1388 }
1389
1390 /*
1391 * Limit to pxa hardware capabilities. YUV422P planar format requires
1392 * images size to be a multiple of 16 bytes. If not, zeros will be
1393 * inserted between Y and U planes, and U and V planes, which violates
1394 * the YUV422P standard.
1395 */
1396 v4l_bound_align_image(&pix->width, 48, 2048, 1,
1397 &pix->height, 32, 2048, 0,
1398 xlate->host_fmt->fourcc == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1399
1400 pix->bytesperline = pix->width *
1401 DIV_ROUND_UP(xlate->host_fmt->depth, 8);
1402 pix->sizeimage = pix->height * pix->bytesperline;
1403
1404 /* camera has to see its format, but the user the original one */
1405 pix->pixelformat = xlate->cam_fmt->fourcc;
1406 /* limit to sensor capabilities */
1407 ret = icd->ops->try_fmt(icd, f);
1408 pix->pixelformat = xlate->host_fmt->fourcc;
1409
1410 field = pix->field;
1411
1412 if (field == V4L2_FIELD_ANY) {
1413 pix->field = V4L2_FIELD_NONE;
1414 } else if (field != V4L2_FIELD_NONE) {
1415 dev_err(&icd->dev, "Field type %d unsupported.\n", field);
1416 return -EINVAL;
1417 }
1418
1419 return ret;
1420 }
1421
1422 static int pxa_camera_reqbufs(struct soc_camera_file *icf,
1423 struct v4l2_requestbuffers *p)
1424 {
1425 int i;
1426
1427 /* This is for locking debugging only. I removed spinlocks and now I
1428 * check whether .prepare is ever called on a linked buffer, or whether
1429 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
1430 * it hadn't triggered */
1431 for (i = 0; i < p->count; i++) {
1432 struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i],
1433 struct pxa_buffer, vb);
1434 buf->inwork = 0;
1435 INIT_LIST_HEAD(&buf->vb.queue);
1436 }
1437
1438 return 0;
1439 }
1440
1441 static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
1442 {
1443 struct soc_camera_file *icf = file->private_data;
1444 struct pxa_buffer *buf;
1445
1446 buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer,
1447 vb.stream);
1448
1449 poll_wait(file, &buf->vb.done, pt);
1450
1451 if (buf->vb.state == VIDEOBUF_DONE ||
1452 buf->vb.state == VIDEOBUF_ERROR)
1453 return POLLIN|POLLRDNORM;
1454
1455 return 0;
1456 }
1457
1458 static int pxa_camera_querycap(struct soc_camera_host *ici,
1459 struct v4l2_capability *cap)
1460 {
1461 /* cap->name is set by the firendly caller:-> */
1462 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1463 cap->version = PXA_CAM_VERSION_CODE;
1464 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1465
1466 return 0;
1467 }
1468
1469 static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state)
1470 {
1471 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1472 struct pxa_camera_dev *pcdev = ici->priv;
1473 int i = 0, ret = 0;
1474
1475 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
1476 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
1477 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
1478 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
1479 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
1480
1481 if ((pcdev->icd) && (pcdev->icd->ops->suspend))
1482 ret = pcdev->icd->ops->suspend(pcdev->icd, state);
1483
1484 return ret;
1485 }
1486
1487 static int pxa_camera_resume(struct soc_camera_device *icd)
1488 {
1489 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1490 struct pxa_camera_dev *pcdev = ici->priv;
1491 int i = 0, ret = 0;
1492
1493 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1494 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1495 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1496
1497 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
1498 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
1499 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
1500 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
1501 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
1502
1503 if ((pcdev->icd) && (pcdev->icd->ops->resume))
1504 ret = pcdev->icd->ops->resume(pcdev->icd);
1505
1506 /* Restart frame capture if active buffer exists */
1507 if (!ret && pcdev->active)
1508 pxa_camera_start_capture(pcdev);
1509
1510 return ret;
1511 }
1512
1513 static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
1514 .owner = THIS_MODULE,
1515 .add = pxa_camera_add_device,
1516 .remove = pxa_camera_remove_device,
1517 .suspend = pxa_camera_suspend,
1518 .resume = pxa_camera_resume,
1519 .set_crop = pxa_camera_set_crop,
1520 .get_formats = pxa_camera_get_formats,
1521 .set_fmt = pxa_camera_set_fmt,
1522 .try_fmt = pxa_camera_try_fmt,
1523 .init_videobuf = pxa_camera_init_videobuf,
1524 .reqbufs = pxa_camera_reqbufs,
1525 .poll = pxa_camera_poll,
1526 .querycap = pxa_camera_querycap,
1527 .set_bus_param = pxa_camera_set_bus_param,
1528 };
1529
1530 static int __devinit pxa_camera_probe(struct platform_device *pdev)
1531 {
1532 struct pxa_camera_dev *pcdev;
1533 struct resource *res;
1534 void __iomem *base;
1535 int irq;
1536 int err = 0;
1537
1538 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1539 irq = platform_get_irq(pdev, 0);
1540 if (!res || irq < 0) {
1541 err = -ENODEV;
1542 goto exit;
1543 }
1544
1545 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1546 if (!pcdev) {
1547 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1548 err = -ENOMEM;
1549 goto exit;
1550 }
1551
1552 pcdev->clk = clk_get(&pdev->dev, NULL);
1553 if (IS_ERR(pcdev->clk)) {
1554 err = PTR_ERR(pcdev->clk);
1555 goto exit_kfree;
1556 }
1557
1558 pcdev->res = res;
1559
1560 pcdev->pdata = pdev->dev.platform_data;
1561 pcdev->platform_flags = pcdev->pdata->flags;
1562 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1563 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
1564 /* Platform hasn't set available data widths. This is bad.
1565 * Warn and use a default. */
1566 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1567 "data widths, using default 10 bit\n");
1568 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1569 }
1570 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
1571 if (!pcdev->mclk) {
1572 dev_warn(&pdev->dev,
1573 "mclk == 0! Please, fix your platform data. "
1574 "Using default 20MHz\n");
1575 pcdev->mclk = 20000000;
1576 }
1577
1578 pcdev->soc_host.dev = &pdev->dev;
1579 pcdev->mclk_divisor = mclk_get_divisor(pcdev);
1580
1581 INIT_LIST_HEAD(&pcdev->capture);
1582 spin_lock_init(&pcdev->lock);
1583
1584 /*
1585 * Request the regions.
1586 */
1587 if (!request_mem_region(res->start, resource_size(res),
1588 PXA_CAM_DRV_NAME)) {
1589 err = -EBUSY;
1590 goto exit_clk;
1591 }
1592
1593 base = ioremap(res->start, resource_size(res));
1594 if (!base) {
1595 err = -ENOMEM;
1596 goto exit_release;
1597 }
1598 pcdev->irq = irq;
1599 pcdev->base = base;
1600
1601 /* request dma */
1602 err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
1603 pxa_camera_dma_irq_y, pcdev);
1604 if (err < 0) {
1605 dev_err(&pdev->dev, "Can't request DMA for Y\n");
1606 goto exit_iounmap;
1607 }
1608 pcdev->dma_chans[0] = err;
1609 dev_dbg(&pdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
1610
1611 err = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
1612 pxa_camera_dma_irq_u, pcdev);
1613 if (err < 0) {
1614 dev_err(&pdev->dev, "Can't request DMA for U\n");
1615 goto exit_free_dma_y;
1616 }
1617 pcdev->dma_chans[1] = err;
1618 dev_dbg(&pdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
1619
1620 err = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
1621 pxa_camera_dma_irq_v, pcdev);
1622 if (err < 0) {
1623 dev_err(&pdev->dev, "Can't request DMA for V\n");
1624 goto exit_free_dma_u;
1625 }
1626 pcdev->dma_chans[2] = err;
1627 dev_dbg(&pdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
1628
1629 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1630 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1631 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1632
1633 /* request irq */
1634 err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
1635 pcdev);
1636 if (err) {
1637 dev_err(&pdev->dev, "Camera interrupt register failed \n");
1638 goto exit_free_dma;
1639 }
1640
1641 pcdev->soc_host.drv_name = PXA_CAM_DRV_NAME;
1642 pcdev->soc_host.ops = &pxa_soc_camera_host_ops;
1643 pcdev->soc_host.priv = pcdev;
1644 pcdev->soc_host.nr = pdev->id;
1645
1646 err = soc_camera_host_register(&pcdev->soc_host);
1647 if (err)
1648 goto exit_free_irq;
1649
1650 return 0;
1651
1652 exit_free_irq:
1653 free_irq(pcdev->irq, pcdev);
1654 exit_free_dma:
1655 pxa_free_dma(pcdev->dma_chans[2]);
1656 exit_free_dma_u:
1657 pxa_free_dma(pcdev->dma_chans[1]);
1658 exit_free_dma_y:
1659 pxa_free_dma(pcdev->dma_chans[0]);
1660 exit_iounmap:
1661 iounmap(base);
1662 exit_release:
1663 release_mem_region(res->start, resource_size(res));
1664 exit_clk:
1665 clk_put(pcdev->clk);
1666 exit_kfree:
1667 kfree(pcdev);
1668 exit:
1669 return err;
1670 }
1671
1672 static int __devexit pxa_camera_remove(struct platform_device *pdev)
1673 {
1674 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1675 struct pxa_camera_dev *pcdev = container_of(soc_host,
1676 struct pxa_camera_dev, soc_host);
1677 struct resource *res;
1678
1679 clk_put(pcdev->clk);
1680
1681 pxa_free_dma(pcdev->dma_chans[0]);
1682 pxa_free_dma(pcdev->dma_chans[1]);
1683 pxa_free_dma(pcdev->dma_chans[2]);
1684 free_irq(pcdev->irq, pcdev);
1685
1686 soc_camera_host_unregister(soc_host);
1687
1688 iounmap(pcdev->base);
1689
1690 res = pcdev->res;
1691 release_mem_region(res->start, resource_size(res));
1692
1693 kfree(pcdev);
1694
1695 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
1696
1697 return 0;
1698 }
1699
1700 static struct platform_driver pxa_camera_driver = {
1701 .driver = {
1702 .name = PXA_CAM_DRV_NAME,
1703 },
1704 .probe = pxa_camera_probe,
1705 .remove = __devexit_p(pxa_camera_remove),
1706 };
1707
1708
1709 static int __init pxa_camera_init(void)
1710 {
1711 return platform_driver_register(&pxa_camera_driver);
1712 }
1713
1714 static void __exit pxa_camera_exit(void)
1715 {
1716 platform_driver_unregister(&pxa_camera_driver);
1717 }
1718
1719 module_init(pxa_camera_init);
1720 module_exit(pxa_camera_exit);
1721
1722 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1723 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1724 MODULE_LICENSE("GPL");