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USB: OTG: langwell_otg: fix up some sysfs attribute permissions
[zen-stable.git] / drivers / usb / otg / langwell_otg.c
blob9fea48264fa2049fe7eefd18cada2013a180a5e0
1 /*
2 * Intel Langwell USB OTG transceiver driver
3 * Copyright (C) 2008 - 2010, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19 /* This driver helps to switch Langwell OTG controller function between host
20 * and peripheral. It works with EHCI driver and Langwell client controller
21 * driver together.
22 */
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/pci.h>
26 #include <linux/errno.h>
27 #include <linux/interrupt.h>
28 #include <linux/kernel.h>
29 #include <linux/device.h>
30 #include <linux/moduleparam.h>
31 #include <linux/usb/ch9.h>
32 #include <linux/usb/gadget.h>
33 #include <linux/usb.h>
34 #include <linux/usb/otg.h>
35 #include <linux/usb/hcd.h>
36 #include <linux/notifier.h>
37 #include <linux/delay.h>
38 #include <asm/intel_scu_ipc.h>
39
40 #include <linux/usb/langwell_otg.h>
41
42 #define DRIVER_DESC "Intel Langwell USB OTG transceiver driver"
43 #define DRIVER_VERSION "July 10, 2010"
44
45 MODULE_DESCRIPTION(DRIVER_DESC);
46 MODULE_AUTHOR("Henry Yuan <hang.yuan@intel.com>, Hao Wu <hao.wu@intel.com>");
47 MODULE_VERSION(DRIVER_VERSION);
48 MODULE_LICENSE("GPL");
49
50 static const char driver_name[] = "langwell_otg";
51
52 static int langwell_otg_probe(struct pci_dev *pdev,
53 const struct pci_device_id *id);
54 static void langwell_otg_remove(struct pci_dev *pdev);
55 static int langwell_otg_suspend(struct pci_dev *pdev, pm_message_t message);
56 static int langwell_otg_resume(struct pci_dev *pdev);
57
58 static int langwell_otg_set_host(struct otg_transceiver *otg,
59 struct usb_bus *host);
60 static int langwell_otg_set_peripheral(struct otg_transceiver *otg,
61 struct usb_gadget *gadget);
62 static int langwell_otg_start_srp(struct otg_transceiver *otg);
63
64 static const struct pci_device_id pci_ids[] = {{
65 .class = ((PCI_CLASS_SERIAL_USB << 8) | 0xfe),
66 .class_mask = ~0,
67 .vendor = 0x8086,
68 .device = 0x0811,
69 .subvendor = PCI_ANY_ID,
70 .subdevice = PCI_ANY_ID,
71 }, { /* end: all zeroes */ }
72 };
73
74 static struct pci_driver otg_pci_driver = {
75 .name = (char *) driver_name,
76 .id_table = pci_ids,
77
78 .probe = langwell_otg_probe,
79 .remove = langwell_otg_remove,
80
81 .suspend = langwell_otg_suspend,
82 .resume = langwell_otg_resume,
83 };
84
85 static const char *state_string(enum usb_otg_state state)
86 {
87 switch (state) {
88 case OTG_STATE_A_IDLE:
89 return "a_idle";
90 case OTG_STATE_A_WAIT_VRISE:
91 return "a_wait_vrise";
92 case OTG_STATE_A_WAIT_BCON:
93 return "a_wait_bcon";
94 case OTG_STATE_A_HOST:
95 return "a_host";
96 case OTG_STATE_A_SUSPEND:
97 return "a_suspend";
98 case OTG_STATE_A_PERIPHERAL:
99 return "a_peripheral";
100 case OTG_STATE_A_WAIT_VFALL:
101 return "a_wait_vfall";
102 case OTG_STATE_A_VBUS_ERR:
103 return "a_vbus_err";
104 case OTG_STATE_B_IDLE:
105 return "b_idle";
106 case OTG_STATE_B_SRP_INIT:
107 return "b_srp_init";
108 case OTG_STATE_B_PERIPHERAL:
109 return "b_peripheral";
110 case OTG_STATE_B_WAIT_ACON:
111 return "b_wait_acon";
112 case OTG_STATE_B_HOST:
113 return "b_host";
114 default:
115 return "UNDEFINED";
116 }
117 }
118
119 /* HSM timers */
120 static inline struct langwell_otg_timer *otg_timer_initializer
121 (void (*function)(unsigned long), unsigned long expires, unsigned long data)
122 {
123 struct langwell_otg_timer *timer;
124 timer = kmalloc(sizeof(struct langwell_otg_timer), GFP_KERNEL);
125 if (timer == NULL)
126 return timer;
127
128 timer->function = function;
129 timer->expires = expires;
130 timer->data = data;
131 return timer;
132 }
133
134 static struct langwell_otg_timer *a_wait_vrise_tmr, *a_aidl_bdis_tmr,
135 *b_se0_srp_tmr, *b_srp_init_tmr;
136
137 static struct list_head active_timers;
138
139 static struct langwell_otg *the_transceiver;
140
141 /* host/client notify transceiver when event affects HNP state */
142 void langwell_update_transceiver(void)
143 {
144 struct langwell_otg *lnw = the_transceiver;
145
146 dev_dbg(lnw->dev, "transceiver is updated\n");
147
148 if (!lnw->qwork)
149 return ;
150
151 queue_work(lnw->qwork, &lnw->work);
152 }
153 EXPORT_SYMBOL(langwell_update_transceiver);
154
155 static int langwell_otg_set_host(struct otg_transceiver *otg,
156 struct usb_bus *host)
157 {
158 otg->host = host;
159
160 return 0;
161 }
162
163 static int langwell_otg_set_peripheral(struct otg_transceiver *otg,
164 struct usb_gadget *gadget)
165 {
166 otg->gadget = gadget;
167
168 return 0;
169 }
170
171 static int langwell_otg_set_power(struct otg_transceiver *otg,
172 unsigned mA)
173 {
174 return 0;
175 }
176
177 /* A-device drives vbus, controlled through PMIC CHRGCNTL register*/
178 static int langwell_otg_set_vbus(struct otg_transceiver *otg, bool enabled)
179 {
180 struct langwell_otg *lnw = the_transceiver;
181 u8 r;
182
183 dev_dbg(lnw->dev, "%s <--- %s\n", __func__, enabled ? "on" : "off");
184
185 /* FIXME: surely we should cache this on the first read. If not use
186 readv to avoid two transactions */
187 if (intel_scu_ipc_ioread8(0x00, &r) < 0) {
188 dev_dbg(lnw->dev, "Failed to read PMIC register 0xD2");
189 return -EBUSY;
190 }
191 if ((r & 0x03) != 0x02) {
192 dev_dbg(lnw->dev, "not NEC PMIC attached\n");
193 return -EBUSY;
194 }
195
196 if (intel_scu_ipc_ioread8(0x20, &r) < 0) {
197 dev_dbg(lnw->dev, "Failed to read PMIC register 0xD2");
198 return -EBUSY;
199 }
200
201 if ((r & 0x20) == 0) {
202 dev_dbg(lnw->dev, "no battery attached\n");
203 return -EBUSY;
204 }
205
206 /* Workaround for battery attachment issue */
207 if (r == 0x34) {
208 dev_dbg(lnw->dev, "no battery attached on SH\n");
209 return -EBUSY;
210 }
211
212 dev_dbg(lnw->dev, "battery attached. 2 reg = %x\n", r);
213
214 /* workaround: FW detect writing 0x20/0xc0 to d4 event.
215 * this is only for NEC PMIC.
216 */
217
218 if (intel_scu_ipc_iowrite8(0xD4, enabled ? 0x20 : 0xC0))
219 dev_dbg(lnw->dev, "Failed to write PMIC.\n");
220
221 dev_dbg(lnw->dev, "%s --->\n", __func__);
222
223 return 0;
224 }
225
226 /* charge vbus or discharge vbus through a resistor to ground */
227 static void langwell_otg_chrg_vbus(int on)
228 {
229 struct langwell_otg *lnw = the_transceiver;
230 u32 val;
231
232 val = readl(lnw->iotg.base + CI_OTGSC);
233
234 if (on)
235 writel((val & ~OTGSC_INTSTS_MASK) | OTGSC_VC,
236 lnw->iotg.base + CI_OTGSC);
237 else
238 writel((val & ~OTGSC_INTSTS_MASK) | OTGSC_VD,
239 lnw->iotg.base + CI_OTGSC);
240 }
241
242 /* Start SRP */
243 static int langwell_otg_start_srp(struct otg_transceiver *otg)
244 {
245 struct langwell_otg *lnw = the_transceiver;
246 struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
247 u32 val;
248
249 dev_dbg(lnw->dev, "%s --->\n", __func__);
250
251 val = readl(iotg->base + CI_OTGSC);
252
253 writel((val & ~OTGSC_INTSTS_MASK) | OTGSC_HADP,
254 iotg->base + CI_OTGSC);
255
256 /* Check if the data plus is finished or not */
257 msleep(8);
258 val = readl(iotg->base + CI_OTGSC);
259 if (val & (OTGSC_HADP | OTGSC_DP))
260 dev_dbg(lnw->dev, "DataLine SRP Error\n");
261
262 /* Disable interrupt - b_sess_vld */
263 val = readl(iotg->base + CI_OTGSC);
264 val &= (~(OTGSC_BSVIE | OTGSC_BSEIE));
265 writel(val, iotg->base + CI_OTGSC);
266
267 /* Start VBus SRP, drive vbus to generate VBus pulse */
268 iotg->otg.set_vbus(&iotg->otg, true);
269 msleep(15);
270 iotg->otg.set_vbus(&iotg->otg, false);
271
272 /* Enable interrupt - b_sess_vld*/
273 val = readl(iotg->base + CI_OTGSC);
274 dev_dbg(lnw->dev, "after VBUS pulse otgsc = %x\n", val);
275
276 val |= (OTGSC_BSVIE | OTGSC_BSEIE);
277 writel(val, iotg->base + CI_OTGSC);
278
279 /* If Vbus is valid, then update the hsm */
280 if (val & OTGSC_BSV) {
281 dev_dbg(lnw->dev, "no b_sess_vld interrupt\n");
282
283 lnw->iotg.hsm.b_sess_vld = 1;
284 langwell_update_transceiver();
285 }
286
287 dev_dbg(lnw->dev, "%s <---\n", __func__);
288 return 0;
289 }
290
291 /* stop SOF via bus_suspend */
292 static void langwell_otg_loc_sof(int on)
293 {
294 struct langwell_otg *lnw = the_transceiver;
295 struct usb_hcd *hcd;
296 int err;
297
298 dev_dbg(lnw->dev, "%s ---> %s\n", __func__, on ? "suspend" : "resume");
299
300 hcd = bus_to_hcd(lnw->iotg.otg.host);
301 if (on)
302 err = hcd->driver->bus_resume(hcd);
303 else
304 err = hcd->driver->bus_suspend(hcd);
305
306 if (err)
307 dev_dbg(lnw->dev, "Fail to resume/suspend USB bus - %d\n", err);
308
309 dev_dbg(lnw->dev, "%s <---\n", __func__);
310 }
311
312 static int langwell_otg_check_otgsc(void)
313 {
314 struct langwell_otg *lnw = the_transceiver;
315 u32 otgsc, usbcfg;
316
317 dev_dbg(lnw->dev, "check sync OTGSC and USBCFG registers\n");
318
319 otgsc = readl(lnw->iotg.base + CI_OTGSC);
320 usbcfg = readl(lnw->usbcfg);
321
322 dev_dbg(lnw->dev, "OTGSC = %08x, USBCFG = %08x\n",
323 otgsc, usbcfg);
324 dev_dbg(lnw->dev, "OTGSC_AVV = %d\n", !!(otgsc & OTGSC_AVV));
325 dev_dbg(lnw->dev, "USBCFG.VBUSVAL = %d\n",
326 !!(usbcfg & USBCFG_VBUSVAL));
327 dev_dbg(lnw->dev, "OTGSC_ASV = %d\n", !!(otgsc & OTGSC_ASV));
328 dev_dbg(lnw->dev, "USBCFG.AVALID = %d\n",
329 !!(usbcfg & USBCFG_AVALID));
330 dev_dbg(lnw->dev, "OTGSC_BSV = %d\n", !!(otgsc & OTGSC_BSV));
331 dev_dbg(lnw->dev, "USBCFG.BVALID = %d\n",
332 !!(usbcfg & USBCFG_BVALID));
333 dev_dbg(lnw->dev, "OTGSC_BSE = %d\n", !!(otgsc & OTGSC_BSE));
334 dev_dbg(lnw->dev, "USBCFG.SESEND = %d\n",
335 !!(usbcfg & USBCFG_SESEND));
336
337 /* Check USBCFG VBusValid/AValid/BValid/SessEnd */
338 if (!!(otgsc & OTGSC_AVV) ^ !!(usbcfg & USBCFG_VBUSVAL)) {
339 dev_dbg(lnw->dev, "OTGSC.AVV != USBCFG.VBUSVAL\n");
340 goto err;
341 }
342 if (!!(otgsc & OTGSC_ASV) ^ !!(usbcfg & USBCFG_AVALID)) {
343 dev_dbg(lnw->dev, "OTGSC.ASV != USBCFG.AVALID\n");
344 goto err;
345 }
346 if (!!(otgsc & OTGSC_BSV) ^ !!(usbcfg & USBCFG_BVALID)) {
347 dev_dbg(lnw->dev, "OTGSC.BSV != USBCFG.BVALID\n");
348 goto err;
349 }
350 if (!!(otgsc & OTGSC_BSE) ^ !!(usbcfg & USBCFG_SESEND)) {
351 dev_dbg(lnw->dev, "OTGSC.BSE != USBCFG.SESSEN\n");
352 goto err;
353 }
354
355 dev_dbg(lnw->dev, "OTGSC and USBCFG are synced\n");
356
357 return 0;
358
359 err:
360 dev_warn(lnw->dev, "OTGSC isn't equal to USBCFG\n");
361 return -EPIPE;
362 }
363
364
365 static void langwell_otg_phy_low_power(int on)
366 {
367 struct langwell_otg *lnw = the_transceiver;
368 struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
369 u8 val, phcd;
370 int retval;
371
372 dev_dbg(lnw->dev, "%s ---> %s mode\n",
373 __func__, on ? "Low power" : "Normal");
374
375 phcd = 0x40;
376
377 val = readb(iotg->base + CI_HOSTPC1 + 2);
378
379 if (on) {
380 /* Due to hardware issue, after set PHCD, sync will failed
381 * between USBCFG and OTGSC, so before set PHCD, check if
382 * sync is in process now. If the answer is "yes", then do
383 * not touch PHCD bit */
384 retval = langwell_otg_check_otgsc();
385 if (retval) {
386 dev_dbg(lnw->dev, "Skip PHCD programming..\n");
387 return ;
388 }
389
390 writeb(val | phcd, iotg->base + CI_HOSTPC1 + 2);
391 } else
392 writeb(val & ~phcd, iotg->base + CI_HOSTPC1 + 2);
393
394 dev_dbg(lnw->dev, "%s <--- done\n", __func__);
395 }
396
397 /* After drv vbus, add 2 ms delay to set PHCD */
398 static void langwell_otg_phy_low_power_wait(int on)
399 {
400 struct langwell_otg *lnw = the_transceiver;
401
402 dev_dbg(lnw->dev, "add 2ms delay before programing PHCD\n");
403
404 mdelay(2);
405 langwell_otg_phy_low_power(on);
406 }
407
408 /* Enable/Disable OTG interrupt */
409 static void langwell_otg_intr(int on)
410 {
411 struct langwell_otg *lnw = the_transceiver;
412 struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
413 u32 val;
414
415 dev_dbg(lnw->dev, "%s ---> %s\n", __func__, on ? "on" : "off");
416
417 val = readl(iotg->base + CI_OTGSC);
418
419 /* OTGSC_INT_MASK doesn't contains 1msInt */
420 if (on) {
421 val = val | (OTGSC_INT_MASK);
422 writel(val, iotg->base + CI_OTGSC);
423 } else {
424 val = val & ~(OTGSC_INT_MASK);
425 writel(val, iotg->base + CI_OTGSC);
426 }
427
428 dev_dbg(lnw->dev, "%s <---\n", __func__);
429 }
430
431 /* set HAAR: Hardware Assist Auto-Reset */
432 static void langwell_otg_HAAR(int on)
433 {
434 struct langwell_otg *lnw = the_transceiver;
435 struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
436 u32 val;
437
438 dev_dbg(lnw->dev, "%s ---> %s\n", __func__, on ? "on" : "off");
439
440 val = readl(iotg->base + CI_OTGSC);
441 if (on)
442 writel((val & ~OTGSC_INTSTS_MASK) | OTGSC_HAAR,
443 iotg->base + CI_OTGSC);
444 else
445 writel((val & ~OTGSC_INTSTS_MASK) & ~OTGSC_HAAR,
446 iotg->base + CI_OTGSC);
447
448 dev_dbg(lnw->dev, "%s <---\n", __func__);
449 }
450
451 /* set HABA: Hardware Assist B-Disconnect to A-Connect */
452 static void langwell_otg_HABA(int on)
453 {
454 struct langwell_otg *lnw = the_transceiver;
455 struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
456 u32 val;
457
458 dev_dbg(lnw->dev, "%s ---> %s\n", __func__, on ? "on" : "off");
459
460 val = readl(iotg->base + CI_OTGSC);
461 if (on)
462 writel((val & ~OTGSC_INTSTS_MASK) | OTGSC_HABA,
463 iotg->base + CI_OTGSC);
464 else
465 writel((val & ~OTGSC_INTSTS_MASK) & ~OTGSC_HABA,
466 iotg->base + CI_OTGSC);
467
468 dev_dbg(lnw->dev, "%s <---\n", __func__);
469 }
470
471 static int langwell_otg_check_se0_srp(int on)
472 {
473 struct langwell_otg *lnw = the_transceiver;
474 int delay_time = TB_SE0_SRP * 10;
475 u32 val;
476
477 dev_dbg(lnw->dev, "%s --->\n", __func__);
478
479 do {
480 udelay(100);
481 if (!delay_time--)
482 break;
483 val = readl(lnw->iotg.base + CI_PORTSC1);
484 val &= PORTSC_LS;
485 } while (!val);
486
487 dev_dbg(lnw->dev, "%s <---\n", __func__);
488 return val;
489 }
490
491 /* The timeout callback function to set time out bit */
492 static void set_tmout(unsigned long indicator)
493 {
494 *(int *)indicator = 1;
495 }
496
497 void langwell_otg_nsf_msg(unsigned long indicator)
498 {
499 struct langwell_otg *lnw = the_transceiver;
500
501 switch (indicator) {
502 case 2:
503 case 4:
504 case 6:
505 case 7:
506 dev_warn(lnw->dev,
507 "OTG:NSF-%lu - deivce not responding\n", indicator);
508 break;
509 case 3:
510 dev_warn(lnw->dev,
511 "OTG:NSF-%lu - deivce not supported\n", indicator);
512 break;
513 default:
514 dev_warn(lnw->dev, "Do not have this kind of NSF\n");
515 break;
516 }
517 }
518
519 /* Initialize timers */
520 static int langwell_otg_init_timers(struct otg_hsm *hsm)
521 {
522 /* HSM used timers */
523 a_wait_vrise_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_VRISE,
524 (unsigned long)&hsm->a_wait_vrise_tmout);
525 if (a_wait_vrise_tmr == NULL)
526 return -ENOMEM;
527 a_aidl_bdis_tmr = otg_timer_initializer(&set_tmout, TA_AIDL_BDIS,
528 (unsigned long)&hsm->a_aidl_bdis_tmout);
529 if (a_aidl_bdis_tmr == NULL)
530 return -ENOMEM;
531 b_se0_srp_tmr = otg_timer_initializer(&set_tmout, TB_SE0_SRP,
532 (unsigned long)&hsm->b_se0_srp);
533 if (b_se0_srp_tmr == NULL)
534 return -ENOMEM;
535 b_srp_init_tmr = otg_timer_initializer(&set_tmout, TB_SRP_INIT,
536 (unsigned long)&hsm->b_srp_init_tmout);
537 if (b_srp_init_tmr == NULL)
538 return -ENOMEM;
539
540 return 0;
541 }
542
543 /* Free timers */
544 static void langwell_otg_free_timers(void)
545 {
546 kfree(a_wait_vrise_tmr);
547 kfree(a_aidl_bdis_tmr);
548 kfree(b_se0_srp_tmr);
549 kfree(b_srp_init_tmr);
550 }
551
552 /* The timeout callback function to set time out bit */
553 static void langwell_otg_timer_fn(unsigned long indicator)
554 {
555 struct langwell_otg *lnw = the_transceiver;
556
557 *(int *)indicator = 1;
558
559 dev_dbg(lnw->dev, "kernel timer - timeout\n");
560
561 langwell_update_transceiver();
562 }
563
564 /* kernel timer used instead of HW based interrupt */
565 static void langwell_otg_add_ktimer(enum langwell_otg_timer_type timers)
566 {
567 struct langwell_otg *lnw = the_transceiver;
568 struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
569 unsigned long j = jiffies;
570 unsigned long data, time;
571
572 switch (timers) {
573 case TA_WAIT_VRISE_TMR:
574 iotg->hsm.a_wait_vrise_tmout = 0;
575 data = (unsigned long)&iotg->hsm.a_wait_vrise_tmout;
576 time = TA_WAIT_VRISE;
577 break;
578 case TA_WAIT_BCON_TMR:
579 iotg->hsm.a_wait_bcon_tmout = 0;
580 data = (unsigned long)&iotg->hsm.a_wait_bcon_tmout;
581 time = TA_WAIT_BCON;
582 break;
583 case TA_AIDL_BDIS_TMR:
584 iotg->hsm.a_aidl_bdis_tmout = 0;
585 data = (unsigned long)&iotg->hsm.a_aidl_bdis_tmout;
586 time = TA_AIDL_BDIS;
587 break;
588 case TB_ASE0_BRST_TMR:
589 iotg->hsm.b_ase0_brst_tmout = 0;
590 data = (unsigned long)&iotg->hsm.b_ase0_brst_tmout;
591 time = TB_ASE0_BRST;
592 break;
593 case TB_SRP_INIT_TMR:
594 iotg->hsm.b_srp_init_tmout = 0;
595 data = (unsigned long)&iotg->hsm.b_srp_init_tmout;
596 time = TB_SRP_INIT;
597 break;
598 case TB_SRP_FAIL_TMR:
599 iotg->hsm.b_srp_fail_tmout = 0;
600 data = (unsigned long)&iotg->hsm.b_srp_fail_tmout;
601 time = TB_SRP_FAIL;
602 break;
603 case TB_BUS_SUSPEND_TMR:
604 iotg->hsm.b_bus_suspend_tmout = 0;
605 data = (unsigned long)&iotg->hsm.b_bus_suspend_tmout;
606 time = TB_BUS_SUSPEND;
607 break;
608 default:
609 dev_dbg(lnw->dev, "unkown timer, cannot enable it\n");
610 return;
611 }
612
613 lnw->hsm_timer.data = data;
614 lnw->hsm_timer.function = langwell_otg_timer_fn;
615 lnw->hsm_timer.expires = j + time * HZ / 1000; /* milliseconds */
616
617 add_timer(&lnw->hsm_timer);
618
619 dev_dbg(lnw->dev, "add timer successfully\n");
620 }
621
622 /* Add timer to timer list */
623 static void langwell_otg_add_timer(void *gtimer)
624 {
625 struct langwell_otg_timer *timer = (struct langwell_otg_timer *)gtimer;
626 struct langwell_otg_timer *tmp_timer;
627 struct intel_mid_otg_xceiv *iotg = &the_transceiver->iotg;
628 u32 val32;
629
630 /* Check if the timer is already in the active list,
631 * if so update timer count
632 */
633 list_for_each_entry(tmp_timer, &active_timers, list)
634 if (tmp_timer == timer) {
635 timer->count = timer->expires;
636 return;
637 }
638 timer->count = timer->expires;
639
640 if (list_empty(&active_timers)) {
641 val32 = readl(iotg->base + CI_OTGSC);
642 writel(val32 | OTGSC_1MSE, iotg->base + CI_OTGSC);
643 }
644
645 list_add_tail(&timer->list, &active_timers);
646 }
647
648 /* Remove timer from the timer list; clear timeout status */
649 static void langwell_otg_del_timer(void *gtimer)
650 {
651 struct langwell_otg *lnw = the_transceiver;
652 struct langwell_otg_timer *timer = (struct langwell_otg_timer *)gtimer;
653 struct langwell_otg_timer *tmp_timer, *del_tmp;
654 u32 val32;
655
656 list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list)
657 if (tmp_timer == timer)
658 list_del(&timer->list);
659
660 if (list_empty(&active_timers)) {
661 val32 = readl(lnw->iotg.base + CI_OTGSC);
662 writel(val32 & ~OTGSC_1MSE, lnw->iotg.base + CI_OTGSC);
663 }
664 }
665
666 /* Reduce timer count by 1, and find timeout conditions.*/
667 static int langwell_otg_tick_timer(u32 *int_sts)
668 {
669 struct langwell_otg *lnw = the_transceiver;
670 struct langwell_otg_timer *tmp_timer, *del_tmp;
671 int expired = 0;
672
673 list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list) {
674 tmp_timer->count--;
675 /* check if timer expires */
676 if (!tmp_timer->count) {
677 list_del(&tmp_timer->list);
678 tmp_timer->function(tmp_timer->data);
679 expired = 1;
680 }
681 }
682
683 if (list_empty(&active_timers)) {
684 dev_dbg(lnw->dev, "tick timer: disable 1ms int\n");
685 *int_sts = *int_sts & ~OTGSC_1MSE;
686 }
687 return expired;
688 }
689
690 static void reset_otg(void)
691 {
692 struct langwell_otg *lnw = the_transceiver;
693 int delay_time = 1000;
694 u32 val;
695
696 dev_dbg(lnw->dev, "reseting OTG controller ...\n");
697 val = readl(lnw->iotg.base + CI_USBCMD);
698 writel(val | USBCMD_RST, lnw->iotg.base + CI_USBCMD);
699 do {
700 udelay(100);
701 if (!delay_time--)
702 dev_dbg(lnw->dev, "reset timeout\n");
703 val = readl(lnw->iotg.base + CI_USBCMD);
704 val &= USBCMD_RST;
705 } while (val != 0);
706 dev_dbg(lnw->dev, "reset done.\n");
707 }
708
709 static void set_host_mode(void)
710 {
711 struct langwell_otg *lnw = the_transceiver;
712 u32 val;
713
714 reset_otg();
715 val = readl(lnw->iotg.base + CI_USBMODE);
716 val = (val & (~USBMODE_CM)) | USBMODE_HOST;
717 writel(val, lnw->iotg.base + CI_USBMODE);
718 }
719
720 static void set_client_mode(void)
721 {
722 struct langwell_otg *lnw = the_transceiver;
723 u32 val;
724
725 reset_otg();
726 val = readl(lnw->iotg.base + CI_USBMODE);
727 val = (val & (~USBMODE_CM)) | USBMODE_DEVICE;
728 writel(val, lnw->iotg.base + CI_USBMODE);
729 }
730
731 static void init_hsm(void)
732 {
733 struct langwell_otg *lnw = the_transceiver;
734 struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
735 u32 val32;
736
737 /* read OTGSC after reset */
738 val32 = readl(lnw->iotg.base + CI_OTGSC);
739 dev_dbg(lnw->dev, "%s: OTGSC init value = 0x%x\n", __func__, val32);
740
741 /* set init state */
742 if (val32 & OTGSC_ID) {
743 iotg->hsm.id = 1;
744 iotg->otg.default_a = 0;
745 set_client_mode();
746 iotg->otg.state = OTG_STATE_B_IDLE;
747 } else {
748 iotg->hsm.id = 0;
749 iotg->otg.default_a = 1;
750 set_host_mode();
751 iotg->otg.state = OTG_STATE_A_IDLE;
752 }
753
754 /* set session indicator */
755 if (val32 & OTGSC_BSE)
756 iotg->hsm.b_sess_end = 1;
757 if (val32 & OTGSC_BSV)
758 iotg->hsm.b_sess_vld = 1;
759 if (val32 & OTGSC_ASV)
760 iotg->hsm.a_sess_vld = 1;
761 if (val32 & OTGSC_AVV)
762 iotg->hsm.a_vbus_vld = 1;
763
764 /* defautly power the bus */
765 iotg->hsm.a_bus_req = 1;
766 iotg->hsm.a_bus_drop = 0;
767 /* defautly don't request bus as B device */
768 iotg->hsm.b_bus_req = 0;
769 /* no system error */
770 iotg->hsm.a_clr_err = 0;
771
772 langwell_otg_phy_low_power_wait(1);
773 }
774
775 static void update_hsm(void)
776 {
777 struct langwell_otg *lnw = the_transceiver;
778 struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
779 u32 val32;
780
781 /* read OTGSC */
782 val32 = readl(lnw->iotg.base + CI_OTGSC);
783 dev_dbg(lnw->dev, "%s: OTGSC value = 0x%x\n", __func__, val32);
784
785 iotg->hsm.id = !!(val32 & OTGSC_ID);
786 iotg->hsm.b_sess_end = !!(val32 & OTGSC_BSE);
787 iotg->hsm.b_sess_vld = !!(val32 & OTGSC_BSV);
788 iotg->hsm.a_sess_vld = !!(val32 & OTGSC_ASV);
789 iotg->hsm.a_vbus_vld = !!(val32 & OTGSC_AVV);
790 }
791
792 static irqreturn_t otg_dummy_irq(int irq, void *_dev)
793 {
794 struct langwell_otg *lnw = the_transceiver;
795 void __iomem *reg_base = _dev;
796 u32 val;
797 u32 int_mask = 0;
798
799 val = readl(reg_base + CI_USBMODE);
800 if ((val & USBMODE_CM) != USBMODE_DEVICE)
801 return IRQ_NONE;
802
803 val = readl(reg_base + CI_USBSTS);
804 int_mask = val & INTR_DUMMY_MASK;
805
806 if (int_mask == 0)
807 return IRQ_NONE;
808
809 /* clear hsm.b_conn here since host driver can't detect it
810 * otg_dummy_irq called means B-disconnect happened.
811 */
812 if (lnw->iotg.hsm.b_conn) {
813 lnw->iotg.hsm.b_conn = 0;
814 if (spin_trylock(&lnw->wq_lock)) {
815 langwell_update_transceiver();
816 spin_unlock(&lnw->wq_lock);
817 }
818 }
819
820 /* Clear interrupts */
821 writel(int_mask, reg_base + CI_USBSTS);
822 return IRQ_HANDLED;
823 }
824
825 static irqreturn_t otg_irq(int irq, void *_dev)
826 {
827 struct langwell_otg *lnw = _dev;
828 struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
829 u32 int_sts, int_en;
830 u32 int_mask = 0;
831 int flag = 0;
832
833 int_sts = readl(lnw->iotg.base + CI_OTGSC);
834 int_en = (int_sts & OTGSC_INTEN_MASK) >> 8;
835 int_mask = int_sts & int_en;
836 if (int_mask == 0)
837 return IRQ_NONE;
838
839 if (int_mask & OTGSC_IDIS) {
840 dev_dbg(lnw->dev, "%s: id change int\n", __func__);
841 iotg->hsm.id = (int_sts & OTGSC_ID) ? 1 : 0;
842 dev_dbg(lnw->dev, "id = %d\n", iotg->hsm.id);
843 flag = 1;
844 }
845 if (int_mask & OTGSC_DPIS) {
846 dev_dbg(lnw->dev, "%s: data pulse int\n", __func__);
847 iotg->hsm.a_srp_det = (int_sts & OTGSC_DPS) ? 1 : 0;
848 dev_dbg(lnw->dev, "data pulse = %d\n", iotg->hsm.a_srp_det);
849 flag = 1;
850 }
851 if (int_mask & OTGSC_BSEIS) {
852 dev_dbg(lnw->dev, "%s: b session end int\n", __func__);
853 iotg->hsm.b_sess_end = (int_sts & OTGSC_BSE) ? 1 : 0;
854 dev_dbg(lnw->dev, "b_sess_end = %d\n", iotg->hsm.b_sess_end);
855 flag = 1;
856 }
857 if (int_mask & OTGSC_BSVIS) {
858 dev_dbg(lnw->dev, "%s: b session valid int\n", __func__);
859 iotg->hsm.b_sess_vld = (int_sts & OTGSC_BSV) ? 1 : 0;
860 dev_dbg(lnw->dev, "b_sess_vld = %d\n", iotg->hsm.b_sess_end);
861 flag = 1;
862 }
863 if (int_mask & OTGSC_ASVIS) {
864 dev_dbg(lnw->dev, "%s: a session valid int\n", __func__);
865 iotg->hsm.a_sess_vld = (int_sts & OTGSC_ASV) ? 1 : 0;
866 dev_dbg(lnw->dev, "a_sess_vld = %d\n", iotg->hsm.a_sess_vld);
867 flag = 1;
868 }
869 if (int_mask & OTGSC_AVVIS) {
870 dev_dbg(lnw->dev, "%s: a vbus valid int\n", __func__);
871 iotg->hsm.a_vbus_vld = (int_sts & OTGSC_AVV) ? 1 : 0;
872 dev_dbg(lnw->dev, "a_vbus_vld = %d\n", iotg->hsm.a_vbus_vld);
873 flag = 1;
874 }
875
876 if (int_mask & OTGSC_1MSS) {
877 /* need to schedule otg_work if any timer is expired */
878 if (langwell_otg_tick_timer(&int_sts))
879 flag = 1;
880 }
881
882 writel((int_sts & ~OTGSC_INTSTS_MASK) | int_mask,
883 lnw->iotg.base + CI_OTGSC);
884 if (flag)
885 langwell_update_transceiver();
886
887 return IRQ_HANDLED;
888 }
889
890 static int langwell_otg_iotg_notify(struct notifier_block *nb,
891 unsigned long action, void *data)
892 {
893 struct langwell_otg *lnw = the_transceiver;
894 struct intel_mid_otg_xceiv *iotg = data;
895 int flag = 0;
896
897 if (iotg == NULL)
898 return NOTIFY_BAD;
899
900 if (lnw == NULL)
901 return NOTIFY_BAD;
902
903 switch (action) {
904 case MID_OTG_NOTIFY_CONNECT:
905 dev_dbg(lnw->dev, "Lnw OTG Notify Connect Event\n");
906 if (iotg->otg.default_a == 1)
907 iotg->hsm.b_conn = 1;
908 else
909 iotg->hsm.a_conn = 1;
910 flag = 1;
911 break;
912 case MID_OTG_NOTIFY_DISCONN:
913 dev_dbg(lnw->dev, "Lnw OTG Notify Disconnect Event\n");
914 if (iotg->otg.default_a == 1)
915 iotg->hsm.b_conn = 0;
916 else
917 iotg->hsm.a_conn = 0;
918 flag = 1;
919 break;
920 case MID_OTG_NOTIFY_HSUSPEND:
921 dev_dbg(lnw->dev, "Lnw OTG Notify Host Bus suspend Event\n");
922 if (iotg->otg.default_a == 1)
923 iotg->hsm.a_suspend_req = 1;
924 else
925 iotg->hsm.b_bus_req = 0;
926 flag = 1;
927 break;
928 case MID_OTG_NOTIFY_HRESUME:
929 dev_dbg(lnw->dev, "Lnw OTG Notify Host Bus resume Event\n");
930 if (iotg->otg.default_a == 1)
931 iotg->hsm.b_bus_resume = 1;
932 flag = 1;
933 break;
934 case MID_OTG_NOTIFY_CSUSPEND:
935 dev_dbg(lnw->dev, "Lnw OTG Notify Client Bus suspend Event\n");
936 if (iotg->otg.default_a == 1) {
937 if (iotg->hsm.b_bus_suspend_vld == 2) {
938 iotg->hsm.b_bus_suspend = 1;
939 iotg->hsm.b_bus_suspend_vld = 0;
940 flag = 1;
941 } else {
942 iotg->hsm.b_bus_suspend_vld++;
943 flag = 0;
944 }
945 } else {
946 if (iotg->hsm.a_bus_suspend == 0) {
947 iotg->hsm.a_bus_suspend = 1;
948 flag = 1;
949 }
950 }
951 break;
952 case MID_OTG_NOTIFY_CRESUME:
953 dev_dbg(lnw->dev, "Lnw OTG Notify Client Bus resume Event\n");
954 if (iotg->otg.default_a == 0)
955 iotg->hsm.a_bus_suspend = 0;
956 flag = 0;
957 break;
958 case MID_OTG_NOTIFY_HOSTADD:
959 dev_dbg(lnw->dev, "Lnw OTG Nofity Host Driver Add\n");
960 flag = 1;
961 break;
962 case MID_OTG_NOTIFY_HOSTREMOVE:
963 dev_dbg(lnw->dev, "Lnw OTG Nofity Host Driver remove\n");
964 flag = 1;
965 break;
966 case MID_OTG_NOTIFY_CLIENTADD:
967 dev_dbg(lnw->dev, "Lnw OTG Nofity Client Driver Add\n");
968 flag = 1;
969 break;
970 case MID_OTG_NOTIFY_CLIENTREMOVE:
971 dev_dbg(lnw->dev, "Lnw OTG Nofity Client Driver remove\n");
972 flag = 1;
973 break;
974 default:
975 dev_dbg(lnw->dev, "Lnw OTG Nofity unknown notify message\n");
976 return NOTIFY_DONE;
977 }
978
979 if (flag)
980 langwell_update_transceiver();
981
982 return NOTIFY_OK;
983 }
984
985 static void langwell_otg_work(struct work_struct *work)
986 {
987 struct langwell_otg *lnw;
988 struct intel_mid_otg_xceiv *iotg;
989 int retval;
990 struct pci_dev *pdev;
991
992 lnw = container_of(work, struct langwell_otg, work);
993 iotg = &lnw->iotg;
994 pdev = to_pci_dev(lnw->dev);
995
996 dev_dbg(lnw->dev, "%s: old state = %s\n", __func__,
997 state_string(iotg->otg.state));
998
999 switch (iotg->otg.state) {
1000 case OTG_STATE_UNDEFINED:
1001 case OTG_STATE_B_IDLE:
1002 if (!iotg->hsm.id) {
1003 langwell_otg_del_timer(b_srp_init_tmr);
1004 del_timer_sync(&lnw->hsm_timer);
1005
1006 iotg->otg.default_a = 1;
1007 iotg->hsm.a_srp_det = 0;
1008
1009 langwell_otg_chrg_vbus(0);
1010 set_host_mode();
1011 langwell_otg_phy_low_power(1);
1012
1013 iotg->otg.state = OTG_STATE_A_IDLE;
1014 langwell_update_transceiver();
1015 } else if (iotg->hsm.b_sess_vld) {
1016 langwell_otg_del_timer(b_srp_init_tmr);
1017 del_timer_sync(&lnw->hsm_timer);
1018 iotg->hsm.b_sess_end = 0;
1019 iotg->hsm.a_bus_suspend = 0;
1020 langwell_otg_chrg_vbus(0);
1021
1022 if (lnw->iotg.start_peripheral) {
1023 lnw->iotg.start_peripheral(&lnw->iotg);
1024 iotg->otg.state = OTG_STATE_B_PERIPHERAL;
1025 } else
1026 dev_dbg(lnw->dev, "client driver not loaded\n");
1027
1028 } else if (iotg->hsm.b_srp_init_tmout) {
1029 iotg->hsm.b_srp_init_tmout = 0;
1030 dev_warn(lnw->dev, "SRP init timeout\n");
1031 } else if (iotg->hsm.b_srp_fail_tmout) {
1032 iotg->hsm.b_srp_fail_tmout = 0;
1033 iotg->hsm.b_bus_req = 0;
1034
1035 /* No silence failure */
1036 langwell_otg_nsf_msg(6);
1037 } else if (iotg->hsm.b_bus_req && iotg->hsm.b_sess_end) {
1038 del_timer_sync(&lnw->hsm_timer);
1039 /* workaround for b_se0_srp detection */
1040 retval = langwell_otg_check_se0_srp(0);
1041 if (retval) {
1042 iotg->hsm.b_bus_req = 0;
1043 dev_dbg(lnw->dev, "LS isn't SE0, try later\n");
1044 } else {
1045 /* clear the PHCD before start srp */
1046 langwell_otg_phy_low_power(0);
1047
1048 /* Start SRP */
1049 langwell_otg_add_timer(b_srp_init_tmr);
1050 iotg->otg.start_srp(&iotg->otg);
1051 langwell_otg_del_timer(b_srp_init_tmr);
1052 langwell_otg_add_ktimer(TB_SRP_FAIL_TMR);
1053
1054 /* reset PHY low power mode here */
1055 langwell_otg_phy_low_power_wait(1);
1056 }
1057 }
1058 break;
1059 case OTG_STATE_B_SRP_INIT:
1060 if (!iotg->hsm.id) {
1061 iotg->otg.default_a = 1;
1062 iotg->hsm.a_srp_det = 0;
1063
1064 /* Turn off VBus */
1065 iotg->otg.set_vbus(&iotg->otg, false);
1066 langwell_otg_chrg_vbus(0);
1067 set_host_mode();
1068 langwell_otg_phy_low_power(1);
1069 iotg->otg.state = OTG_STATE_A_IDLE;
1070 langwell_update_transceiver();
1071 } else if (iotg->hsm.b_sess_vld) {
1072 langwell_otg_chrg_vbus(0);
1073 if (lnw->iotg.start_peripheral) {
1074 lnw->iotg.start_peripheral(&lnw->iotg);
1075 iotg->otg.state = OTG_STATE_B_PERIPHERAL;
1076 } else
1077 dev_dbg(lnw->dev, "client driver not loaded\n");
1078 }
1079 break;
1080 case OTG_STATE_B_PERIPHERAL:
1081 if (!iotg->hsm.id) {
1082 iotg->otg.default_a = 1;
1083 iotg->hsm.a_srp_det = 0;
1084
1085 langwell_otg_chrg_vbus(0);
1086
1087 if (lnw->iotg.stop_peripheral)
1088 lnw->iotg.stop_peripheral(&lnw->iotg);
1089 else
1090 dev_dbg(lnw->dev,
1091 "client driver has been removed.\n");
1092
1093 set_host_mode();
1094 langwell_otg_phy_low_power(1);
1095 iotg->otg.state = OTG_STATE_A_IDLE;
1096 langwell_update_transceiver();
1097 } else if (!iotg->hsm.b_sess_vld) {
1098 iotg->hsm.b_hnp_enable = 0;
1099
1100 if (lnw->iotg.stop_peripheral)
1101 lnw->iotg.stop_peripheral(&lnw->iotg);
1102 else
1103 dev_dbg(lnw->dev,
1104 "client driver has been removed.\n");
1105
1106 iotg->otg.state = OTG_STATE_B_IDLE;
1107 } else if (iotg->hsm.b_bus_req && iotg->otg.gadget &&
1108 iotg->otg.gadget->b_hnp_enable &&
1109 iotg->hsm.a_bus_suspend) {
1110
1111 if (lnw->iotg.stop_peripheral)
1112 lnw->iotg.stop_peripheral(&lnw->iotg);
1113 else
1114 dev_dbg(lnw->dev,
1115 "client driver has been removed.\n");
1116
1117 langwell_otg_HAAR(1);
1118 iotg->hsm.a_conn = 0;
1119
1120 if (lnw->iotg.start_host) {
1121 lnw->iotg.start_host(&lnw->iotg);
1122 iotg->otg.state = OTG_STATE_B_WAIT_ACON;
1123 } else
1124 dev_dbg(lnw->dev,
1125 "host driver not loaded.\n");
1126
1127 iotg->hsm.a_bus_resume = 0;
1128 langwell_otg_add_ktimer(TB_ASE0_BRST_TMR);
1129 }
1130 break;
1131
1132 case OTG_STATE_B_WAIT_ACON:
1133 if (!iotg->hsm.id) {
1134 /* delete hsm timer for b_ase0_brst_tmr */
1135 del_timer_sync(&lnw->hsm_timer);
1136
1137 iotg->otg.default_a = 1;
1138 iotg->hsm.a_srp_det = 0;
1139
1140 langwell_otg_chrg_vbus(0);
1141
1142 langwell_otg_HAAR(0);
1143 if (lnw->iotg.stop_host)
1144 lnw->iotg.stop_host(&lnw->iotg);
1145 else
1146 dev_dbg(lnw->dev,
1147 "host driver has been removed.\n");
1148
1149 set_host_mode();
1150 langwell_otg_phy_low_power(1);
1151 iotg->otg.state = OTG_STATE_A_IDLE;
1152 langwell_update_transceiver();
1153 } else if (!iotg->hsm.b_sess_vld) {
1154 /* delete hsm timer for b_ase0_brst_tmr */
1155 del_timer_sync(&lnw->hsm_timer);
1156
1157 iotg->hsm.b_hnp_enable = 0;
1158 iotg->hsm.b_bus_req = 0;
1159
1160 langwell_otg_chrg_vbus(0);
1161 langwell_otg_HAAR(0);
1162
1163 if (lnw->iotg.stop_host)
1164 lnw->iotg.stop_host(&lnw->iotg);
1165 else
1166 dev_dbg(lnw->dev,
1167 "host driver has been removed.\n");
1168
1169 set_client_mode();
1170 langwell_otg_phy_low_power(1);
1171 iotg->otg.state = OTG_STATE_B_IDLE;
1172 } else if (iotg->hsm.a_conn) {
1173 /* delete hsm timer for b_ase0_brst_tmr */
1174 del_timer_sync(&lnw->hsm_timer);
1175
1176 langwell_otg_HAAR(0);
1177 iotg->otg.state = OTG_STATE_B_HOST;
1178 langwell_update_transceiver();
1179 } else if (iotg->hsm.a_bus_resume ||
1180 iotg->hsm.b_ase0_brst_tmout) {
1181 /* delete hsm timer for b_ase0_brst_tmr */
1182 del_timer_sync(&lnw->hsm_timer);
1183
1184 langwell_otg_HAAR(0);
1185 langwell_otg_nsf_msg(7);
1186
1187 if (lnw->iotg.stop_host)
1188 lnw->iotg.stop_host(&lnw->iotg);
1189 else
1190 dev_dbg(lnw->dev,
1191 "host driver has been removed.\n");
1192
1193 iotg->hsm.a_bus_suspend = 0;
1194 iotg->hsm.b_bus_req = 0;
1195
1196 if (lnw->iotg.start_peripheral)
1197 lnw->iotg.start_peripheral(&lnw->iotg);
1198 else
1199 dev_dbg(lnw->dev,
1200 "client driver not loaded.\n");
1201
1202 iotg->otg.state = OTG_STATE_B_PERIPHERAL;
1203 }
1204 break;
1205
1206 case OTG_STATE_B_HOST:
1207 if (!iotg->hsm.id) {
1208 iotg->otg.default_a = 1;
1209 iotg->hsm.a_srp_det = 0;
1210
1211 langwell_otg_chrg_vbus(0);
1212
1213 if (lnw->iotg.stop_host)
1214 lnw->iotg.stop_host(&lnw->iotg);
1215 else
1216 dev_dbg(lnw->dev,
1217 "host driver has been removed.\n");
1218
1219 set_host_mode();
1220 langwell_otg_phy_low_power(1);
1221 iotg->otg.state = OTG_STATE_A_IDLE;
1222 langwell_update_transceiver();
1223 } else if (!iotg->hsm.b_sess_vld) {
1224 iotg->hsm.b_hnp_enable = 0;
1225 iotg->hsm.b_bus_req = 0;
1226
1227 langwell_otg_chrg_vbus(0);
1228 if (lnw->iotg.stop_host)
1229 lnw->iotg.stop_host(&lnw->iotg);
1230 else
1231 dev_dbg(lnw->dev,
1232 "host driver has been removed.\n");
1233
1234 set_client_mode();
1235 langwell_otg_phy_low_power(1);
1236 iotg->otg.state = OTG_STATE_B_IDLE;
1237 } else if ((!iotg->hsm.b_bus_req) ||
1238 (!iotg->hsm.a_conn)) {
1239 iotg->hsm.b_bus_req = 0;
1240 langwell_otg_loc_sof(0);
1241
1242 if (lnw->iotg.stop_host)
1243 lnw->iotg.stop_host(&lnw->iotg);
1244 else
1245 dev_dbg(lnw->dev,
1246 "host driver has been removed.\n");
1247
1248 iotg->hsm.a_bus_suspend = 0;
1249
1250 if (lnw->iotg.start_peripheral)
1251 lnw->iotg.start_peripheral(&lnw->iotg);
1252 else
1253 dev_dbg(lnw->dev,
1254 "client driver not loaded.\n");
1255
1256 iotg->otg.state = OTG_STATE_B_PERIPHERAL;
1257 }
1258 break;
1259
1260 case OTG_STATE_A_IDLE:
1261 iotg->otg.default_a = 1;
1262 if (iotg->hsm.id) {
1263 iotg->otg.default_a = 0;
1264 iotg->hsm.b_bus_req = 0;
1265 iotg->hsm.vbus_srp_up = 0;
1266
1267 langwell_otg_chrg_vbus(0);
1268 set_client_mode();
1269 langwell_otg_phy_low_power(1);
1270 iotg->otg.state = OTG_STATE_B_IDLE;
1271 langwell_update_transceiver();
1272 } else if (!iotg->hsm.a_bus_drop &&
1273 (iotg->hsm.a_srp_det || iotg->hsm.a_bus_req)) {
1274 langwell_otg_phy_low_power(0);
1275
1276 /* Turn on VBus */
1277 iotg->otg.set_vbus(&iotg->otg, true);
1278
1279 iotg->hsm.vbus_srp_up = 0;
1280 iotg->hsm.a_wait_vrise_tmout = 0;
1281 langwell_otg_add_timer(a_wait_vrise_tmr);
1282 iotg->otg.state = OTG_STATE_A_WAIT_VRISE;
1283 langwell_update_transceiver();
1284 } else if (!iotg->hsm.a_bus_drop && iotg->hsm.a_sess_vld) {
1285 iotg->hsm.vbus_srp_up = 1;
1286 } else if (!iotg->hsm.a_sess_vld && iotg->hsm.vbus_srp_up) {
1287 msleep(10);
1288 langwell_otg_phy_low_power(0);
1289
1290 /* Turn on VBus */
1291 iotg->otg.set_vbus(&iotg->otg, true);
1292 iotg->hsm.a_srp_det = 1;
1293 iotg->hsm.vbus_srp_up = 0;
1294 iotg->hsm.a_wait_vrise_tmout = 0;
1295 langwell_otg_add_timer(a_wait_vrise_tmr);
1296 iotg->otg.state = OTG_STATE_A_WAIT_VRISE;
1297 langwell_update_transceiver();
1298 } else if (!iotg->hsm.a_sess_vld &&
1299 !iotg->hsm.vbus_srp_up) {
1300 langwell_otg_phy_low_power(1);
1301 }
1302 break;
1303 case OTG_STATE_A_WAIT_VRISE:
1304 if (iotg->hsm.id) {
1305 langwell_otg_del_timer(a_wait_vrise_tmr);
1306 iotg->hsm.b_bus_req = 0;
1307 iotg->otg.default_a = 0;
1308
1309 /* Turn off VBus */
1310 iotg->otg.set_vbus(&iotg->otg, false);
1311 set_client_mode();
1312 langwell_otg_phy_low_power_wait(1);
1313 iotg->otg.state = OTG_STATE_B_IDLE;
1314 } else if (iotg->hsm.a_vbus_vld) {
1315 langwell_otg_del_timer(a_wait_vrise_tmr);
1316 iotg->hsm.b_conn = 0;
1317 if (lnw->iotg.start_host)
1318 lnw->iotg.start_host(&lnw->iotg);
1319 else {
1320 dev_dbg(lnw->dev, "host driver not loaded.\n");
1321 break;
1322 }
1323
1324 langwell_otg_add_ktimer(TA_WAIT_BCON_TMR);
1325 iotg->otg.state = OTG_STATE_A_WAIT_BCON;
1326 } else if (iotg->hsm.a_wait_vrise_tmout) {
1327 iotg->hsm.b_conn = 0;
1328 if (iotg->hsm.a_vbus_vld) {
1329 if (lnw->iotg.start_host)
1330 lnw->iotg.start_host(&lnw->iotg);
1331 else {
1332 dev_dbg(lnw->dev,
1333 "host driver not loaded.\n");
1334 break;
1335 }
1336 langwell_otg_add_ktimer(TA_WAIT_BCON_TMR);
1337 iotg->otg.state = OTG_STATE_A_WAIT_BCON;
1338 } else {
1339
1340 /* Turn off VBus */
1341 iotg->otg.set_vbus(&iotg->otg, false);
1342 langwell_otg_phy_low_power_wait(1);
1343 iotg->otg.state = OTG_STATE_A_VBUS_ERR;
1344 }
1345 }
1346 break;
1347 case OTG_STATE_A_WAIT_BCON:
1348 if (iotg->hsm.id) {
1349 /* delete hsm timer for a_wait_bcon_tmr */
1350 del_timer_sync(&lnw->hsm_timer);
1351
1352 iotg->otg.default_a = 0;
1353 iotg->hsm.b_bus_req = 0;
1354
1355 if (lnw->iotg.stop_host)
1356 lnw->iotg.stop_host(&lnw->iotg);
1357 else
1358 dev_dbg(lnw->dev,
1359 "host driver has been removed.\n");
1360
1361 /* Turn off VBus */
1362 iotg->otg.set_vbus(&iotg->otg, false);
1363 set_client_mode();
1364 langwell_otg_phy_low_power_wait(1);
1365 iotg->otg.state = OTG_STATE_B_IDLE;
1366 langwell_update_transceiver();
1367 } else if (!iotg->hsm.a_vbus_vld) {
1368 /* delete hsm timer for a_wait_bcon_tmr */
1369 del_timer_sync(&lnw->hsm_timer);
1370
1371 if (lnw->iotg.stop_host)
1372 lnw->iotg.stop_host(&lnw->iotg);
1373 else
1374 dev_dbg(lnw->dev,
1375 "host driver has been removed.\n");
1376
1377 /* Turn off VBus */
1378 iotg->otg.set_vbus(&iotg->otg, false);
1379 langwell_otg_phy_low_power_wait(1);
1380 iotg->otg.state = OTG_STATE_A_VBUS_ERR;
1381 } else if (iotg->hsm.a_bus_drop ||
1382 (iotg->hsm.a_wait_bcon_tmout &&
1383 !iotg->hsm.a_bus_req)) {
1384 /* delete hsm timer for a_wait_bcon_tmr */
1385 del_timer_sync(&lnw->hsm_timer);
1386
1387 if (lnw->iotg.stop_host)
1388 lnw->iotg.stop_host(&lnw->iotg);
1389 else
1390 dev_dbg(lnw->dev,
1391 "host driver has been removed.\n");
1392
1393 /* Turn off VBus */
1394 iotg->otg.set_vbus(&iotg->otg, false);
1395 iotg->otg.state = OTG_STATE_A_WAIT_VFALL;
1396 } else if (iotg->hsm.b_conn) {
1397 /* delete hsm timer for a_wait_bcon_tmr */
1398 del_timer_sync(&lnw->hsm_timer);
1399
1400 iotg->hsm.a_suspend_req = 0;
1401 iotg->otg.state = OTG_STATE_A_HOST;
1402 if (iotg->hsm.a_srp_det && iotg->otg.host &&
1403 !iotg->otg.host->b_hnp_enable) {
1404 /* SRP capable peripheral-only device */
1405 iotg->hsm.a_bus_req = 1;
1406 iotg->hsm.a_srp_det = 0;
1407 } else if (!iotg->hsm.a_bus_req && iotg->otg.host &&
1408 iotg->otg.host->b_hnp_enable) {
1409 /* It is not safe enough to do a fast
1410 * transistion from A_WAIT_BCON to
1411 * A_SUSPEND */
1412 msleep(10000);
1413 if (iotg->hsm.a_bus_req)
1414 break;
1415
1416 if (request_irq(pdev->irq,
1417 otg_dummy_irq, IRQF_SHARED,
1418 driver_name, iotg->base) != 0) {
1419 dev_dbg(lnw->dev,
1420 "request interrupt %d fail\n",
1421 pdev->irq);
1422 }
1423
1424 langwell_otg_HABA(1);
1425 iotg->hsm.b_bus_resume = 0;
1426 iotg->hsm.a_aidl_bdis_tmout = 0;
1427
1428 langwell_otg_loc_sof(0);
1429 /* clear PHCD to enable HW timer */
1430 langwell_otg_phy_low_power(0);
1431 langwell_otg_add_timer(a_aidl_bdis_tmr);
1432 iotg->otg.state = OTG_STATE_A_SUSPEND;
1433 } else if (!iotg->hsm.a_bus_req && iotg->otg.host &&
1434 !iotg->otg.host->b_hnp_enable) {
1435 if (lnw->iotg.stop_host)
1436 lnw->iotg.stop_host(&lnw->iotg);
1437 else
1438 dev_dbg(lnw->dev,
1439 "host driver removed.\n");
1440
1441 /* Turn off VBus */
1442 iotg->otg.set_vbus(&iotg->otg, false);
1443 iotg->otg.state = OTG_STATE_A_WAIT_VFALL;
1444 }
1445 }
1446 break;
1447 case OTG_STATE_A_HOST:
1448 if (iotg->hsm.id) {
1449 iotg->otg.default_a = 0;
1450 iotg->hsm.b_bus_req = 0;
1451
1452 if (lnw->iotg.stop_host)
1453 lnw->iotg.stop_host(&lnw->iotg);
1454 else
1455 dev_dbg(lnw->dev,
1456 "host driver has been removed.\n");
1457
1458 /* Turn off VBus */
1459 iotg->otg.set_vbus(&iotg->otg, false);
1460 set_client_mode();
1461 langwell_otg_phy_low_power_wait(1);
1462 iotg->otg.state = OTG_STATE_B_IDLE;
1463 langwell_update_transceiver();
1464 } else if (iotg->hsm.a_bus_drop ||
1465 (iotg->otg.host &&
1466 !iotg->otg.host->b_hnp_enable &&
1467 !iotg->hsm.a_bus_req)) {
1468 if (lnw->iotg.stop_host)
1469 lnw->iotg.stop_host(&lnw->iotg);
1470 else
1471 dev_dbg(lnw->dev,
1472 "host driver has been removed.\n");
1473
1474 /* Turn off VBus */
1475 iotg->otg.set_vbus(&iotg->otg, false);
1476 iotg->otg.state = OTG_STATE_A_WAIT_VFALL;
1477 } else if (!iotg->hsm.a_vbus_vld) {
1478 if (lnw->iotg.stop_host)
1479 lnw->iotg.stop_host(&lnw->iotg);
1480 else
1481 dev_dbg(lnw->dev,
1482 "host driver has been removed.\n");
1483
1484 /* Turn off VBus */
1485 iotg->otg.set_vbus(&iotg->otg, false);
1486 langwell_otg_phy_low_power_wait(1);
1487 iotg->otg.state = OTG_STATE_A_VBUS_ERR;
1488 } else if (iotg->otg.host &&
1489 iotg->otg.host->b_hnp_enable &&
1490 !iotg->hsm.a_bus_req) {
1491 /* Set HABA to enable hardware assistance to signal
1492 * A-connect after receiver B-disconnect. Hardware
1493 * will then set client mode and enable URE, SLE and
1494 * PCE after the assistance. otg_dummy_irq is used to
1495 * clean these ints when client driver is not resumed.
1496 */
1497 if (request_irq(pdev->irq, otg_dummy_irq, IRQF_SHARED,
1498 driver_name, iotg->base) != 0) {
1499 dev_dbg(lnw->dev,
1500 "request interrupt %d failed\n",
1501 pdev->irq);
1502 }
1503
1504 /* set HABA */
1505 langwell_otg_HABA(1);
1506 iotg->hsm.b_bus_resume = 0;
1507 iotg->hsm.a_aidl_bdis_tmout = 0;
1508 langwell_otg_loc_sof(0);
1509 /* clear PHCD to enable HW timer */
1510 langwell_otg_phy_low_power(0);
1511 langwell_otg_add_timer(a_aidl_bdis_tmr);
1512 iotg->otg.state = OTG_STATE_A_SUSPEND;
1513 } else if (!iotg->hsm.b_conn || !iotg->hsm.a_bus_req) {
1514 langwell_otg_add_ktimer(TA_WAIT_BCON_TMR);
1515 iotg->otg.state = OTG_STATE_A_WAIT_BCON;
1516 }
1517 break;
1518 case OTG_STATE_A_SUSPEND:
1519 if (iotg->hsm.id) {
1520 langwell_otg_del_timer(a_aidl_bdis_tmr);
1521 langwell_otg_HABA(0);
1522 free_irq(pdev->irq, iotg->base);
1523 iotg->otg.default_a = 0;
1524 iotg->hsm.b_bus_req = 0;
1525
1526 if (lnw->iotg.stop_host)
1527 lnw->iotg.stop_host(&lnw->iotg);
1528 else
1529 dev_dbg(lnw->dev,
1530 "host driver has been removed.\n");
1531
1532 /* Turn off VBus */
1533 iotg->otg.set_vbus(&iotg->otg, false);
1534 set_client_mode();
1535 langwell_otg_phy_low_power(1);
1536 iotg->otg.state = OTG_STATE_B_IDLE;
1537 langwell_update_transceiver();
1538 } else if (iotg->hsm.a_bus_req ||
1539 iotg->hsm.b_bus_resume) {
1540 langwell_otg_del_timer(a_aidl_bdis_tmr);
1541 langwell_otg_HABA(0);
1542 free_irq(pdev->irq, iotg->base);
1543 iotg->hsm.a_suspend_req = 0;
1544 langwell_otg_loc_sof(1);
1545 iotg->otg.state = OTG_STATE_A_HOST;
1546 } else if (iotg->hsm.a_aidl_bdis_tmout ||
1547 iotg->hsm.a_bus_drop) {
1548 langwell_otg_del_timer(a_aidl_bdis_tmr);
1549 langwell_otg_HABA(0);
1550 free_irq(pdev->irq, iotg->base);
1551 if (lnw->iotg.stop_host)
1552 lnw->iotg.stop_host(&lnw->iotg);
1553 else
1554 dev_dbg(lnw->dev,
1555 "host driver has been removed.\n");
1556
1557 /* Turn off VBus */
1558 iotg->otg.set_vbus(&iotg->otg, false);
1559 iotg->otg.state = OTG_STATE_A_WAIT_VFALL;
1560 } else if (!iotg->hsm.b_conn && iotg->otg.host &&
1561 iotg->otg.host->b_hnp_enable) {
1562 langwell_otg_del_timer(a_aidl_bdis_tmr);
1563 langwell_otg_HABA(0);
1564 free_irq(pdev->irq, iotg->base);
1565
1566 if (lnw->iotg.stop_host)
1567 lnw->iotg.stop_host(&lnw->iotg);
1568 else
1569 dev_dbg(lnw->dev,
1570 "host driver has been removed.\n");
1571
1572 iotg->hsm.b_bus_suspend = 0;
1573 iotg->hsm.b_bus_suspend_vld = 0;
1574
1575 /* msleep(200); */
1576 if (lnw->iotg.start_peripheral)
1577 lnw->iotg.start_peripheral(&lnw->iotg);
1578 else
1579 dev_dbg(lnw->dev,
1580 "client driver not loaded.\n");
1581
1582 langwell_otg_add_ktimer(TB_BUS_SUSPEND_TMR);
1583 iotg->otg.state = OTG_STATE_A_PERIPHERAL;
1584 break;
1585 } else if (!iotg->hsm.a_vbus_vld) {
1586 langwell_otg_del_timer(a_aidl_bdis_tmr);
1587 langwell_otg_HABA(0);
1588 free_irq(pdev->irq, iotg->base);
1589 if (lnw->iotg.stop_host)
1590 lnw->iotg.stop_host(&lnw->iotg);
1591 else
1592 dev_dbg(lnw->dev,
1593 "host driver has been removed.\n");
1594
1595 /* Turn off VBus */
1596 iotg->otg.set_vbus(&iotg->otg, false);
1597 langwell_otg_phy_low_power_wait(1);
1598 iotg->otg.state = OTG_STATE_A_VBUS_ERR;
1599 }
1600 break;
1601 case OTG_STATE_A_PERIPHERAL:
1602 if (iotg->hsm.id) {
1603 /* delete hsm timer for b_bus_suspend_tmr */
1604 del_timer_sync(&lnw->hsm_timer);
1605 iotg->otg.default_a = 0;
1606 iotg->hsm.b_bus_req = 0;
1607 if (lnw->iotg.stop_peripheral)
1608 lnw->iotg.stop_peripheral(&lnw->iotg);
1609 else
1610 dev_dbg(lnw->dev,
1611 "client driver has been removed.\n");
1612
1613 /* Turn off VBus */
1614 iotg->otg.set_vbus(&iotg->otg, false);
1615 set_client_mode();
1616 langwell_otg_phy_low_power_wait(1);
1617 iotg->otg.state = OTG_STATE_B_IDLE;
1618 langwell_update_transceiver();
1619 } else if (!iotg->hsm.a_vbus_vld) {
1620 /* delete hsm timer for b_bus_suspend_tmr */
1621 del_timer_sync(&lnw->hsm_timer);
1622
1623 if (lnw->iotg.stop_peripheral)
1624 lnw->iotg.stop_peripheral(&lnw->iotg);
1625 else
1626 dev_dbg(lnw->dev,
1627 "client driver has been removed.\n");
1628
1629 /* Turn off VBus */
1630 iotg->otg.set_vbus(&iotg->otg, false);
1631 langwell_otg_phy_low_power_wait(1);
1632 iotg->otg.state = OTG_STATE_A_VBUS_ERR;
1633 } else if (iotg->hsm.a_bus_drop) {
1634 /* delete hsm timer for b_bus_suspend_tmr */
1635 del_timer_sync(&lnw->hsm_timer);
1636
1637 if (lnw->iotg.stop_peripheral)
1638 lnw->iotg.stop_peripheral(&lnw->iotg);
1639 else
1640 dev_dbg(lnw->dev,
1641 "client driver has been removed.\n");
1642
1643 /* Turn off VBus */
1644 iotg->otg.set_vbus(&iotg->otg, false);
1645 iotg->otg.state = OTG_STATE_A_WAIT_VFALL;
1646 } else if (iotg->hsm.b_bus_suspend) {
1647 /* delete hsm timer for b_bus_suspend_tmr */
1648 del_timer_sync(&lnw->hsm_timer);
1649
1650 if (lnw->iotg.stop_peripheral)
1651 lnw->iotg.stop_peripheral(&lnw->iotg);
1652 else
1653 dev_dbg(lnw->dev,
1654 "client driver has been removed.\n");
1655
1656 if (lnw->iotg.start_host)
1657 lnw->iotg.start_host(&lnw->iotg);
1658 else
1659 dev_dbg(lnw->dev,
1660 "host driver not loaded.\n");
1661 langwell_otg_add_ktimer(TA_WAIT_BCON_TMR);
1662 iotg->otg.state = OTG_STATE_A_WAIT_BCON;
1663 } else if (iotg->hsm.b_bus_suspend_tmout) {
1664 u32 val;
1665 val = readl(lnw->iotg.base + CI_PORTSC1);
1666 if (!(val & PORTSC_SUSP))
1667 break;
1668
1669 if (lnw->iotg.stop_peripheral)
1670 lnw->iotg.stop_peripheral(&lnw->iotg);
1671 else
1672 dev_dbg(lnw->dev,
1673 "client driver has been removed.\n");
1674
1675 if (lnw->iotg.start_host)
1676 lnw->iotg.start_host(&lnw->iotg);
1677 else
1678 dev_dbg(lnw->dev,
1679 "host driver not loaded.\n");
1680 langwell_otg_add_ktimer(TA_WAIT_BCON_TMR);
1681 iotg->otg.state = OTG_STATE_A_WAIT_BCON;
1682 }
1683 break;
1684 case OTG_STATE_A_VBUS_ERR:
1685 if (iotg->hsm.id) {
1686 iotg->otg.default_a = 0;
1687 iotg->hsm.a_clr_err = 0;
1688 iotg->hsm.a_srp_det = 0;
1689 set_client_mode();
1690 langwell_otg_phy_low_power(1);
1691 iotg->otg.state = OTG_STATE_B_IDLE;
1692 langwell_update_transceiver();
1693 } else if (iotg->hsm.a_clr_err) {
1694 iotg->hsm.a_clr_err = 0;
1695 iotg->hsm.a_srp_det = 0;
1696 reset_otg();
1697 init_hsm();
1698 if (iotg->otg.state == OTG_STATE_A_IDLE)
1699 langwell_update_transceiver();
1700 } else {
1701 /* FW will clear PHCD bit when any VBus
1702 * event detected. Reset PHCD to 1 again */
1703 langwell_otg_phy_low_power(1);
1704 }
1705 break;
1706 case OTG_STATE_A_WAIT_VFALL:
1707 if (iotg->hsm.id) {
1708 iotg->otg.default_a = 0;
1709 set_client_mode();
1710 langwell_otg_phy_low_power(1);
1711 iotg->otg.state = OTG_STATE_B_IDLE;
1712 langwell_update_transceiver();
1713 } else if (iotg->hsm.a_bus_req) {
1714
1715 /* Turn on VBus */
1716 iotg->otg.set_vbus(&iotg->otg, true);
1717 iotg->hsm.a_wait_vrise_tmout = 0;
1718 langwell_otg_add_timer(a_wait_vrise_tmr);
1719 iotg->otg.state = OTG_STATE_A_WAIT_VRISE;
1720 } else if (!iotg->hsm.a_sess_vld) {
1721 iotg->hsm.a_srp_det = 0;
1722 set_host_mode();
1723 langwell_otg_phy_low_power(1);
1724 iotg->otg.state = OTG_STATE_A_IDLE;
1725 }
1726 break;
1727 default:
1728 ;
1729 }
1730
1731 dev_dbg(lnw->dev, "%s: new state = %s\n", __func__,
1732 state_string(iotg->otg.state));
1733 }
1734
1735 static ssize_t
1736 show_registers(struct device *_dev, struct device_attribute *attr, char *buf)
1737 {
1738 struct langwell_otg *lnw = the_transceiver;
1739 char *next;
1740 unsigned size, t;
1741
1742 next = buf;
1743 size = PAGE_SIZE;
1744
1745 t = scnprintf(next, size,
1746 "\n"
1747 "USBCMD = 0x%08x\n"
1748 "USBSTS = 0x%08x\n"
1749 "USBINTR = 0x%08x\n"
1750 "ASYNCLISTADDR = 0x%08x\n"
1751 "PORTSC1 = 0x%08x\n"
1752 "HOSTPC1 = 0x%08x\n"
1753 "OTGSC = 0x%08x\n"
1754 "USBMODE = 0x%08x\n",
1755 readl(lnw->iotg.base + 0x30),
1756 readl(lnw->iotg.base + 0x34),
1757 readl(lnw->iotg.base + 0x38),
1758 readl(lnw->iotg.base + 0x48),
1759 readl(lnw->iotg.base + 0x74),
1760 readl(lnw->iotg.base + 0xb4),
1761 readl(lnw->iotg.base + 0xf4),
1762 readl(lnw->iotg.base + 0xf8)
1763 );
1764 size -= t;
1765 next += t;
1766
1767 return PAGE_SIZE - size;
1768 }
1769 static DEVICE_ATTR(registers, S_IRUGO, show_registers, NULL);
1770
1771 static ssize_t
1772 show_hsm(struct device *_dev, struct device_attribute *attr, char *buf)
1773 {
1774 struct langwell_otg *lnw = the_transceiver;
1775 struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
1776 char *next;
1777 unsigned size, t;
1778
1779 next = buf;
1780 size = PAGE_SIZE;
1781
1782 if (iotg->otg.host)
1783 iotg->hsm.a_set_b_hnp_en = iotg->otg.host->b_hnp_enable;
1784
1785 if (iotg->otg.gadget)
1786 iotg->hsm.b_hnp_enable = iotg->otg.gadget->b_hnp_enable;
1787
1788 t = scnprintf(next, size,
1789 "\n"
1790 "current state = %s\n"
1791 "a_bus_resume = \t%d\n"
1792 "a_bus_suspend = \t%d\n"
1793 "a_conn = \t%d\n"
1794 "a_sess_vld = \t%d\n"
1795 "a_srp_det = \t%d\n"
1796 "a_vbus_vld = \t%d\n"
1797 "b_bus_resume = \t%d\n"
1798 "b_bus_suspend = \t%d\n"
1799 "b_conn = \t%d\n"
1800 "b_se0_srp = \t%d\n"
1801 "b_sess_end = \t%d\n"
1802 "b_sess_vld = \t%d\n"
1803 "id = \t%d\n"
1804 "a_set_b_hnp_en = \t%d\n"
1805 "b_srp_done = \t%d\n"
1806 "b_hnp_enable = \t%d\n"
1807 "a_wait_vrise_tmout = \t%d\n"
1808 "a_wait_bcon_tmout = \t%d\n"
1809 "a_aidl_bdis_tmout = \t%d\n"
1810 "b_ase0_brst_tmout = \t%d\n"
1811 "a_bus_drop = \t%d\n"
1812 "a_bus_req = \t%d\n"
1813 "a_clr_err = \t%d\n"
1814 "a_suspend_req = \t%d\n"
1815 "b_bus_req = \t%d\n"
1816 "b_bus_suspend_tmout = \t%d\n"
1817 "b_bus_suspend_vld = \t%d\n",
1818 state_string(iotg->otg.state),
1819 iotg->hsm.a_bus_resume,
1820 iotg->hsm.a_bus_suspend,
1821 iotg->hsm.a_conn,
1822 iotg->hsm.a_sess_vld,
1823 iotg->hsm.a_srp_det,
1824 iotg->hsm.a_vbus_vld,
1825 iotg->hsm.b_bus_resume,
1826 iotg->hsm.b_bus_suspend,
1827 iotg->hsm.b_conn,
1828 iotg->hsm.b_se0_srp,
1829 iotg->hsm.b_sess_end,
1830 iotg->hsm.b_sess_vld,
1831 iotg->hsm.id,
1832 iotg->hsm.a_set_b_hnp_en,
1833 iotg->hsm.b_srp_done,
1834 iotg->hsm.b_hnp_enable,
1835 iotg->hsm.a_wait_vrise_tmout,
1836 iotg->hsm.a_wait_bcon_tmout,
1837 iotg->hsm.a_aidl_bdis_tmout,
1838 iotg->hsm.b_ase0_brst_tmout,
1839 iotg->hsm.a_bus_drop,
1840 iotg->hsm.a_bus_req,
1841 iotg->hsm.a_clr_err,
1842 iotg->hsm.a_suspend_req,
1843 iotg->hsm.b_bus_req,
1844 iotg->hsm.b_bus_suspend_tmout,
1845 iotg->hsm.b_bus_suspend_vld
1846 );
1847 size -= t;
1848 next += t;
1849
1850 return PAGE_SIZE - size;
1851 }
1852 static DEVICE_ATTR(hsm, S_IRUGO, show_hsm, NULL);
1853
1854 static ssize_t
1855 get_a_bus_req(struct device *dev, struct device_attribute *attr, char *buf)
1856 {
1857 struct langwell_otg *lnw = the_transceiver;
1858 char *next;
1859 unsigned size, t;
1860
1861 next = buf;
1862 size = PAGE_SIZE;
1863
1864 t = scnprintf(next, size, "%d", lnw->iotg.hsm.a_bus_req);
1865 size -= t;
1866 next += t;
1867
1868 return PAGE_SIZE - size;
1869 }
1870
1871 static ssize_t
1872 set_a_bus_req(struct device *dev, struct device_attribute *attr,
1873 const char *buf, size_t count)
1874 {
1875 struct langwell_otg *lnw = the_transceiver;
1876 struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
1877
1878 if (!iotg->otg.default_a)
1879 return -1;
1880 if (count > 2)
1881 return -1;
1882
1883 if (buf[0] == '0') {
1884 iotg->hsm.a_bus_req = 0;
1885 dev_dbg(lnw->dev, "User request: a_bus_req = 0\n");
1886 } else if (buf[0] == '1') {
1887 /* If a_bus_drop is TRUE, a_bus_req can't be set */
1888 if (iotg->hsm.a_bus_drop)
1889 return -1;
1890 iotg->hsm.a_bus_req = 1;
1891 dev_dbg(lnw->dev, "User request: a_bus_req = 1\n");
1892 }
1893 if (spin_trylock(&lnw->wq_lock)) {
1894 langwell_update_transceiver();
1895 spin_unlock(&lnw->wq_lock);
1896 }
1897 return count;
1898 }
1899 static DEVICE_ATTR(a_bus_req, S_IRUGO | S_IWUSR, get_a_bus_req, set_a_bus_req);
1900
1901 static ssize_t
1902 get_a_bus_drop(struct device *dev, struct device_attribute *attr, char *buf)
1903 {
1904 struct langwell_otg *lnw = the_transceiver;
1905 char *next;
1906 unsigned size, t;
1907
1908 next = buf;
1909 size = PAGE_SIZE;
1910
1911 t = scnprintf(next, size, "%d", lnw->iotg.hsm.a_bus_drop);
1912 size -= t;
1913 next += t;
1914
1915 return PAGE_SIZE - size;
1916 }
1917
1918 static ssize_t
1919 set_a_bus_drop(struct device *dev, struct device_attribute *attr,
1920 const char *buf, size_t count)
1921 {
1922 struct langwell_otg *lnw = the_transceiver;
1923 struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
1924
1925 if (!iotg->otg.default_a)
1926 return -1;
1927 if (count > 2)
1928 return -1;
1929
1930 if (buf[0] == '0') {
1931 iotg->hsm.a_bus_drop = 0;
1932 dev_dbg(lnw->dev, "User request: a_bus_drop = 0\n");
1933 } else if (buf[0] == '1') {
1934 iotg->hsm.a_bus_drop = 1;
1935 iotg->hsm.a_bus_req = 0;
1936 dev_dbg(lnw->dev, "User request: a_bus_drop = 1\n");
1937 dev_dbg(lnw->dev, "User request: and a_bus_req = 0\n");
1938 }
1939 if (spin_trylock(&lnw->wq_lock)) {
1940 langwell_update_transceiver();
1941 spin_unlock(&lnw->wq_lock);
1942 }
1943 return count;
1944 }
1945 static DEVICE_ATTR(a_bus_drop, S_IRUGO | S_IWUSR, get_a_bus_drop, set_a_bus_drop);
1946
1947 static ssize_t
1948 get_b_bus_req(struct device *dev, struct device_attribute *attr, char *buf)
1949 {
1950 struct langwell_otg *lnw = the_transceiver;
1951 char *next;
1952 unsigned size, t;
1953
1954 next = buf;
1955 size = PAGE_SIZE;
1956
1957 t = scnprintf(next, size, "%d", lnw->iotg.hsm.b_bus_req);
1958 size -= t;
1959 next += t;
1960
1961 return PAGE_SIZE - size;
1962 }
1963
1964 static ssize_t
1965 set_b_bus_req(struct device *dev, struct device_attribute *attr,
1966 const char *buf, size_t count)
1967 {
1968 struct langwell_otg *lnw = the_transceiver;
1969 struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
1970
1971 if (iotg->otg.default_a)
1972 return -1;
1973
1974 if (count > 2)
1975 return -1;
1976
1977 if (buf[0] == '0') {
1978 iotg->hsm.b_bus_req = 0;
1979 dev_dbg(lnw->dev, "User request: b_bus_req = 0\n");
1980 } else if (buf[0] == '1') {
1981 iotg->hsm.b_bus_req = 1;
1982 dev_dbg(lnw->dev, "User request: b_bus_req = 1\n");
1983 }
1984 if (spin_trylock(&lnw->wq_lock)) {
1985 langwell_update_transceiver();
1986 spin_unlock(&lnw->wq_lock);
1987 }
1988 return count;
1989 }
1990 static DEVICE_ATTR(b_bus_req, S_IRUGO | S_IWUSR, get_b_bus_req, set_b_bus_req);
1991
1992 static ssize_t
1993 set_a_clr_err(struct device *dev, struct device_attribute *attr,
1994 const char *buf, size_t count)
1995 {
1996 struct langwell_otg *lnw = the_transceiver;
1997 struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
1998
1999 if (!iotg->otg.default_a)
2000 return -1;
2001 if (count > 2)
2002 return -1;
2003
2004 if (buf[0] == '1') {
2005 iotg->hsm.a_clr_err = 1;
2006 dev_dbg(lnw->dev, "User request: a_clr_err = 1\n");
2007 }
2008 if (spin_trylock(&lnw->wq_lock)) {
2009 langwell_update_transceiver();
2010 spin_unlock(&lnw->wq_lock);
2011 }
2012 return count;
2013 }
2014 static DEVICE_ATTR(a_clr_err, S_IWUSR, NULL, set_a_clr_err);
2015
2016 static struct attribute *inputs_attrs[] = {
2017 &dev_attr_a_bus_req.attr,
2018 &dev_attr_a_bus_drop.attr,
2019 &dev_attr_b_bus_req.attr,
2020 &dev_attr_a_clr_err.attr,
2021 NULL,
2022 };
2023
2024 static struct attribute_group debug_dev_attr_group = {
2025 .name = "inputs",
2026 .attrs = inputs_attrs,
2027 };
2028
2029 static int langwell_otg_probe(struct pci_dev *pdev,
2030 const struct pci_device_id *id)
2031 {
2032 unsigned long resource, len;
2033 void __iomem *base = NULL;
2034 int retval;
2035 u32 val32;
2036 struct langwell_otg *lnw;
2037 char qname[] = "langwell_otg_queue";
2038
2039 retval = 0;
2040 dev_dbg(&pdev->dev, "\notg controller is detected.\n");
2041 if (pci_enable_device(pdev) < 0) {
2042 retval = -ENODEV;
2043 goto done;
2044 }
2045
2046 lnw = kzalloc(sizeof *lnw, GFP_KERNEL);
2047 if (lnw == NULL) {
2048 retval = -ENOMEM;
2049 goto done;
2050 }
2051 the_transceiver = lnw;
2052
2053 /* control register: BAR 0 */
2054 resource = pci_resource_start(pdev, 0);
2055 len = pci_resource_len(pdev, 0);
2056 if (!request_mem_region(resource, len, driver_name)) {
2057 retval = -EBUSY;
2058 goto err;
2059 }
2060 lnw->region = 1;
2061
2062 base = ioremap_nocache(resource, len);
2063 if (base == NULL) {
2064 retval = -EFAULT;
2065 goto err;
2066 }
2067 lnw->iotg.base = base;
2068
2069 if (!request_mem_region(USBCFG_ADDR, USBCFG_LEN, driver_name)) {
2070 retval = -EBUSY;
2071 goto err;
2072 }
2073 lnw->cfg_region = 1;
2074
2075 /* For the SCCB.USBCFG register */
2076 base = ioremap_nocache(USBCFG_ADDR, USBCFG_LEN);
2077 if (base == NULL) {
2078 retval = -EFAULT;
2079 goto err;
2080 }
2081 lnw->usbcfg = base;
2082
2083 if (!pdev->irq) {
2084 dev_dbg(&pdev->dev, "No IRQ.\n");
2085 retval = -ENODEV;
2086 goto err;
2087 }
2088
2089 lnw->qwork = create_singlethread_workqueue(qname);
2090 if (!lnw->qwork) {
2091 dev_dbg(&pdev->dev, "cannot create workqueue %s\n", qname);
2092 retval = -ENOMEM;
2093 goto err;
2094 }
2095 INIT_WORK(&lnw->work, langwell_otg_work);
2096
2097 /* OTG common part */
2098 lnw->dev = &pdev->dev;
2099 lnw->iotg.otg.dev = lnw->dev;
2100 lnw->iotg.otg.label = driver_name;
2101 lnw->iotg.otg.set_host = langwell_otg_set_host;
2102 lnw->iotg.otg.set_peripheral = langwell_otg_set_peripheral;
2103 lnw->iotg.otg.set_power = langwell_otg_set_power;
2104 lnw->iotg.otg.set_vbus = langwell_otg_set_vbus;
2105 lnw->iotg.otg.start_srp = langwell_otg_start_srp;
2106 lnw->iotg.otg.state = OTG_STATE_UNDEFINED;
2107
2108 if (otg_set_transceiver(&lnw->iotg.otg)) {
2109 dev_dbg(lnw->dev, "can't set transceiver\n");
2110 retval = -EBUSY;
2111 goto err;
2112 }
2113
2114 reset_otg();
2115 init_hsm();
2116
2117 spin_lock_init(&lnw->lock);
2118 spin_lock_init(&lnw->wq_lock);
2119 INIT_LIST_HEAD(&active_timers);
2120 retval = langwell_otg_init_timers(&lnw->iotg.hsm);
2121 if (retval) {
2122 dev_dbg(&pdev->dev, "Failed to init timers\n");
2123 goto err;
2124 }
2125
2126 init_timer(&lnw->hsm_timer);
2127 ATOMIC_INIT_NOTIFIER_HEAD(&lnw->iotg.iotg_notifier);
2128
2129 lnw->iotg_notifier.notifier_call = langwell_otg_iotg_notify;
2130
2131 retval = intel_mid_otg_register_notifier(&lnw->iotg,
2132 &lnw->iotg_notifier);
2133 if (retval) {
2134 dev_dbg(lnw->dev, "Failed to register notifier\n");
2135 goto err;
2136 }
2137
2138 if (request_irq(pdev->irq, otg_irq, IRQF_SHARED,
2139 driver_name, lnw) != 0) {
2140 dev_dbg(lnw->dev, "request interrupt %d failed\n", pdev->irq);
2141 retval = -EBUSY;
2142 goto err;
2143 }
2144
2145 /* enable OTGSC int */
2146 val32 = OTGSC_DPIE | OTGSC_BSEIE | OTGSC_BSVIE |
2147 OTGSC_ASVIE | OTGSC_AVVIE | OTGSC_IDIE | OTGSC_IDPU;
2148 writel(val32, lnw->iotg.base + CI_OTGSC);
2149
2150 retval = device_create_file(&pdev->dev, &dev_attr_registers);
2151 if (retval < 0) {
2152 dev_dbg(lnw->dev,
2153 "Can't register sysfs attribute: %d\n", retval);
2154 goto err;
2155 }
2156
2157 retval = device_create_file(&pdev->dev, &dev_attr_hsm);
2158 if (retval < 0) {
2159 dev_dbg(lnw->dev, "Can't hsm sysfs attribute: %d\n", retval);
2160 goto err;
2161 }
2162
2163 retval = sysfs_create_group(&pdev->dev.kobj, &debug_dev_attr_group);
2164 if (retval < 0) {
2165 dev_dbg(lnw->dev,
2166 "Can't register sysfs attr group: %d\n", retval);
2167 goto err;
2168 }
2169
2170 if (lnw->iotg.otg.state == OTG_STATE_A_IDLE)
2171 langwell_update_transceiver();
2172
2173 return 0;
2174
2175 err:
2176 if (the_transceiver)
2177 langwell_otg_remove(pdev);
2178 done:
2179 return retval;
2180 }
2181
2182 static void langwell_otg_remove(struct pci_dev *pdev)
2183 {
2184 struct langwell_otg *lnw = the_transceiver;
2185
2186 if (lnw->qwork) {
2187 flush_workqueue(lnw->qwork);
2188 destroy_workqueue(lnw->qwork);
2189 }
2190 intel_mid_otg_unregister_notifier(&lnw->iotg, &lnw->iotg_notifier);
2191 langwell_otg_free_timers();
2192
2193 /* disable OTGSC interrupt as OTGSC doesn't change in reset */
2194 writel(0, lnw->iotg.base + CI_OTGSC);
2195
2196 if (pdev->irq)
2197 free_irq(pdev->irq, lnw);
2198 if (lnw->usbcfg)
2199 iounmap(lnw->usbcfg);
2200 if (lnw->cfg_region)
2201 release_mem_region(USBCFG_ADDR, USBCFG_LEN);
2202 if (lnw->iotg.base)
2203 iounmap(lnw->iotg.base);
2204 if (lnw->region)
2205 release_mem_region(pci_resource_start(pdev, 0),
2206 pci_resource_len(pdev, 0));
2207
2208 otg_set_transceiver(NULL);
2209 pci_disable_device(pdev);
2210 sysfs_remove_group(&pdev->dev.kobj, &debug_dev_attr_group);
2211 device_remove_file(&pdev->dev, &dev_attr_hsm);
2212 device_remove_file(&pdev->dev, &dev_attr_registers);
2213 kfree(lnw);
2214 lnw = NULL;
2215 }
2216
2217 static void transceiver_suspend(struct pci_dev *pdev)
2218 {
2219 pci_save_state(pdev);
2220 pci_set_power_state(pdev, PCI_D3hot);
2221 langwell_otg_phy_low_power(1);
2222 }
2223
2224 static int langwell_otg_suspend(struct pci_dev *pdev, pm_message_t message)
2225 {
2226 struct langwell_otg *lnw = the_transceiver;
2227 struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
2228 int ret = 0;
2229
2230 /* Disbale OTG interrupts */
2231 langwell_otg_intr(0);
2232
2233 if (pdev->irq)
2234 free_irq(pdev->irq, lnw);
2235
2236 /* Prevent more otg_work */
2237 flush_workqueue(lnw->qwork);
2238 destroy_workqueue(lnw->qwork);
2239 lnw->qwork = NULL;
2240
2241 /* start actions */
2242 switch (iotg->otg.state) {
2243 case OTG_STATE_A_WAIT_VFALL:
2244 iotg->otg.state = OTG_STATE_A_IDLE;
2245 case OTG_STATE_A_IDLE:
2246 case OTG_STATE_B_IDLE:
2247 case OTG_STATE_A_VBUS_ERR:
2248 transceiver_suspend(pdev);
2249 break;
2250 case OTG_STATE_A_WAIT_VRISE:
2251 langwell_otg_del_timer(a_wait_vrise_tmr);
2252 iotg->hsm.a_srp_det = 0;
2253
2254 /* Turn off VBus */
2255 iotg->otg.set_vbus(&iotg->otg, false);
2256 iotg->otg.state = OTG_STATE_A_IDLE;
2257 transceiver_suspend(pdev);
2258 break;
2259 case OTG_STATE_A_WAIT_BCON:
2260 del_timer_sync(&lnw->hsm_timer);
2261 if (lnw->iotg.stop_host)
2262 lnw->iotg.stop_host(&lnw->iotg);
2263 else
2264 dev_dbg(&pdev->dev, "host driver has been removed.\n");
2265
2266 iotg->hsm.a_srp_det = 0;
2267
2268 /* Turn off VBus */
2269 iotg->otg.set_vbus(&iotg->otg, false);
2270 iotg->otg.state = OTG_STATE_A_IDLE;
2271 transceiver_suspend(pdev);
2272 break;
2273 case OTG_STATE_A_HOST:
2274 if (lnw->iotg.stop_host)
2275 lnw->iotg.stop_host(&lnw->iotg);
2276 else
2277 dev_dbg(&pdev->dev, "host driver has been removed.\n");
2278
2279 iotg->hsm.a_srp_det = 0;
2280
2281 /* Turn off VBus */
2282 iotg->otg.set_vbus(&iotg->otg, false);
2283
2284 iotg->otg.state = OTG_STATE_A_IDLE;
2285 transceiver_suspend(pdev);
2286 break;
2287 case OTG_STATE_A_SUSPEND:
2288 langwell_otg_del_timer(a_aidl_bdis_tmr);
2289 langwell_otg_HABA(0);
2290 if (lnw->iotg.stop_host)
2291 lnw->iotg.stop_host(&lnw->iotg);
2292 else
2293 dev_dbg(lnw->dev, "host driver has been removed.\n");
2294 iotg->hsm.a_srp_det = 0;
2295
2296 /* Turn off VBus */
2297 iotg->otg.set_vbus(&iotg->otg, false);
2298 iotg->otg.state = OTG_STATE_A_IDLE;
2299 transceiver_suspend(pdev);
2300 break;
2301 case OTG_STATE_A_PERIPHERAL:
2302 del_timer_sync(&lnw->hsm_timer);
2303
2304 if (lnw->iotg.stop_peripheral)
2305 lnw->iotg.stop_peripheral(&lnw->iotg);
2306 else
2307 dev_dbg(&pdev->dev,
2308 "client driver has been removed.\n");
2309 iotg->hsm.a_srp_det = 0;
2310
2311 /* Turn off VBus */
2312 iotg->otg.set_vbus(&iotg->otg, false);
2313 iotg->otg.state = OTG_STATE_A_IDLE;
2314 transceiver_suspend(pdev);
2315 break;
2316 case OTG_STATE_B_HOST:
2317 if (lnw->iotg.stop_host)
2318 lnw->iotg.stop_host(&lnw->iotg);
2319 else
2320 dev_dbg(&pdev->dev, "host driver has been removed.\n");
2321 iotg->hsm.b_bus_req = 0;
2322 iotg->otg.state = OTG_STATE_B_IDLE;
2323 transceiver_suspend(pdev);
2324 break;
2325 case OTG_STATE_B_PERIPHERAL:
2326 if (lnw->iotg.stop_peripheral)
2327 lnw->iotg.stop_peripheral(&lnw->iotg);
2328 else
2329 dev_dbg(&pdev->dev,
2330 "client driver has been removed.\n");
2331 iotg->otg.state = OTG_STATE_B_IDLE;
2332 transceiver_suspend(pdev);
2333 break;
2334 case OTG_STATE_B_WAIT_ACON:
2335 /* delete hsm timer for b_ase0_brst_tmr */
2336 del_timer_sync(&lnw->hsm_timer);
2337
2338 langwell_otg_HAAR(0);
2339
2340 if (lnw->iotg.stop_host)
2341 lnw->iotg.stop_host(&lnw->iotg);
2342 else
2343 dev_dbg(&pdev->dev, "host driver has been removed.\n");
2344 iotg->hsm.b_bus_req = 0;
2345 iotg->otg.state = OTG_STATE_B_IDLE;
2346 transceiver_suspend(pdev);
2347 break;
2348 default:
2349 dev_dbg(lnw->dev, "error state before suspend\n");
2350 break;
2351 }
2352
2353 return ret;
2354 }
2355
2356 static void transceiver_resume(struct pci_dev *pdev)
2357 {
2358 pci_restore_state(pdev);
2359 pci_set_power_state(pdev, PCI_D0);
2360 }
2361
2362 static int langwell_otg_resume(struct pci_dev *pdev)
2363 {
2364 struct langwell_otg *lnw = the_transceiver;
2365 int ret = 0;
2366
2367 transceiver_resume(pdev);
2368
2369 lnw->qwork = create_singlethread_workqueue("langwell_otg_queue");
2370 if (!lnw->qwork) {
2371 dev_dbg(&pdev->dev, "cannot create langwell otg workqueuen");
2372 ret = -ENOMEM;
2373 goto error;
2374 }
2375
2376 if (request_irq(pdev->irq, otg_irq, IRQF_SHARED,
2377 driver_name, lnw) != 0) {
2378 dev_dbg(&pdev->dev, "request interrupt %d failed\n", pdev->irq);
2379 ret = -EBUSY;
2380 goto error;
2381 }
2382
2383 /* enable OTG interrupts */
2384 langwell_otg_intr(1);
2385
2386 update_hsm();
2387
2388 langwell_update_transceiver();
2389
2390 return ret;
2391 error:
2392 langwell_otg_intr(0);
2393 transceiver_suspend(pdev);
2394 return ret;
2395 }
2396
2397 static int __init langwell_otg_init(void)
2398 {
2399 return pci_register_driver(&otg_pci_driver);
2400 }
2401 module_init(langwell_otg_init);
2402
2403 static void __exit langwell_otg_cleanup(void)
2404 {
2405 pci_unregister_driver(&otg_pci_driver);
2406 }
2407 module_exit(langwell_otg_cleanup);