drivers/staging/gma500/mrst_device.c

   1 /**************************************************************************
   2  * Copyright (c) 2011, Intel Corporation.
   3  * All Rights Reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  **************************************************************************/
  19
  20 #include <linux/backlight.h>
  21 #include <drm/drmP.h>
  22 #include <drm/drm.h>
  23 #include "psb_drm.h"
  24 #include "psb_drv.h"
  25 #include "psb_reg.h"
  26 #include "psb_intel_reg.h"
  27 #include <asm/mrst.h>
  28 #include <asm/intel_scu_ipc.h>
  29 #include "mid_bios.h"
  30
  31 static const struct psb_ops oaktrail_chip_ops;
  32
  33 /* IPC message and command defines used to enable/disable mipi panel voltages */
  34 #define IPC_MSG_PANEL_ON_OFF    0xE9
  35 #define IPC_CMD_PANEL_ON        1
  36 #define IPC_CMD_PANEL_OFF       0
  37
  38 static int mrst_output_init(struct drm_device *dev)
  39 {
  40         struct drm_psb_private *dev_priv = dev->dev_private;
  41         if (dev_priv->iLVDS_enable) {
  42                 mrst_lvds_init(dev, &dev_priv->mode_dev);
  43                 return 0;
  44         }
  45         dev_err(dev->dev, "DSI is not supported\n");
  46         return -ENODEV;
  47 }
  48
  49 /*
  50  *      Provide the low level interfaces for the Moorestown backlight
  51  */
  52
  53 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
  54
  55 #define MRST_BLC_MAX_PWM_REG_FREQ           0xFFFF
  56 #define BLC_PWM_PRECISION_FACTOR 100    /* 10000000 */
  57 #define BLC_PWM_FREQ_CALC_CONSTANT 32
  58 #define MHz 1000000
  59 #define BLC_ADJUSTMENT_MAX 100
  60
  61 static struct backlight_device *mrst_backlight_device;
  62 static int mrst_brightness;
  63
  64 static int mrst_set_brightness(struct backlight_device *bd)
  65 {
  66         struct drm_device *dev = bl_get_data(mrst_backlight_device);
  67         struct drm_psb_private *dev_priv = dev->dev_private;
  68         int level = bd->props.brightness;
  69         u32 blc_pwm_ctl;
  70         u32 max_pwm_blc;
  71
  72         /* Percentage 1-100% being valid */
  73         if (level < 1)
  74                 level = 1;
  75
  76         if (gma_power_begin(dev, 0)) {
  77                 /* Calculate and set the brightness value */
  78                 max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16;
  79                 blc_pwm_ctl = level * max_pwm_blc / 100;
  80
  81                 /* Adjust the backlight level with the percent in
  82                  * dev_priv->blc_adj1;
  83                  */
  84                 blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj1;
  85                 blc_pwm_ctl = blc_pwm_ctl / 100;
  86
  87                 /* Adjust the backlight level with the percent in
  88                  * dev_priv->blc_adj2;
  89                  */
  90                 blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj2;
  91                 blc_pwm_ctl = blc_pwm_ctl / 100;
  92
  93                 /* force PWM bit on */
  94                 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));
  95                 REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) | blc_pwm_ctl);
  96                 gma_power_end(dev);
  97         }
  98         mrst_brightness = level;
  99         return 0;
 100 }
 101
 102 static int mrst_get_brightness(struct backlight_device *bd)
 103 {
 104         /* return locally cached var instead of HW read (due to DPST etc.) */
 105         /* FIXME: ideally return actual value in case firmware fiddled with
 106            it */
 107         return mrst_brightness;
 108 }
 109
 110 static int device_backlight_init(struct drm_device *dev)
 111 {
 112         struct drm_psb_private *dev_priv = dev->dev_private;
 113         unsigned long core_clock;
 114         u16 bl_max_freq;
 115         uint32_t value;
 116         uint32_t blc_pwm_precision_factor;
 117
 118         dev_priv->blc_adj1 = BLC_ADJUSTMENT_MAX;
 119         dev_priv->blc_adj2 = BLC_ADJUSTMENT_MAX;
 120         bl_max_freq = 256;
 121         /* this needs to be set elsewhere */
 122         blc_pwm_precision_factor = BLC_PWM_PRECISION_FACTOR;
 123
 124         core_clock = dev_priv->core_freq;
 125
 126         value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
 127         value *= blc_pwm_precision_factor;
 128         value /= bl_max_freq;
 129         value /= blc_pwm_precision_factor;
 130
 131         if (gma_power_begin(dev, false)) {
 132                 if (value > (unsigned long long)MRST_BLC_MAX_PWM_REG_FREQ)
 133                                 return -ERANGE;
 134                 else {
 135                         REG_WRITE(BLC_PWM_CTL2,
 136                                         (0x80000000 | REG_READ(BLC_PWM_CTL2)));
 137                         REG_WRITE(BLC_PWM_CTL, value | (value << 16));
 138                 }
 139                 gma_power_end(dev);
 140         }
 141         return 0;
 142 }
 143
 144 static const struct backlight_ops mrst_ops = {
 145         .get_brightness = mrst_get_brightness,
 146         .update_status  = mrst_set_brightness,
 147 };
 148
 149 int mrst_backlight_init(struct drm_device *dev)
 150 {
 151         struct drm_psb_private *dev_priv = dev->dev_private;
 152         int ret;
 153         struct backlight_properties props;
 154
 155         memset(&props, 0, sizeof(struct backlight_properties));
 156         props.max_brightness = 100;
 157         props.type = BACKLIGHT_PLATFORM;
 158
 159         mrst_backlight_device = backlight_device_register("mrst-bl",
 160                                         NULL, (void *)dev, &mrst_ops, &props);
 161
 162         if (IS_ERR(mrst_backlight_device))
 163                 return PTR_ERR(mrst_backlight_device);
 164
 165         ret = device_backlight_init(dev);
 166         if (ret < 0) {
 167                 backlight_device_unregister(mrst_backlight_device);
 168                 return ret;
 169         }
 170         mrst_backlight_device->props.brightness = 100;
 171         mrst_backlight_device->props.max_brightness = 100;
 172         backlight_update_status(mrst_backlight_device);
 173         dev_priv->backlight_device = mrst_backlight_device;
 174         return 0;
 175 }
 176
 177 #endif
 178
 179 /*
 180  *      Provide the Moorestown specific chip logic and low level methods
 181  *      for power management
 182  */
 183
 184 static void mrst_init_pm(struct drm_device *dev)
 185 {
 186 }
 187
 188 /**
 189  *      mrst_save_display_registers     -       save registers lost on suspend
 190  *      @dev: our DRM device
 191  *
 192  *      Save the state we need in order to be able to restore the interface
 193  *      upon resume from suspend
 194  */
 195 static int mrst_save_display_registers(struct drm_device *dev)
 196 {
 197         struct drm_psb_private *dev_priv = dev->dev_private;
 198         struct drm_crtc *crtc;
 199         struct drm_connector *connector;
 200
 201         /* Display arbitration control + watermarks */
 202         dev_priv->saveDSPARB = PSB_RVDC32(DSPARB);
 203         dev_priv->saveDSPFW1 = PSB_RVDC32(DSPFW1);
 204         dev_priv->saveDSPFW2 = PSB_RVDC32(DSPFW2);
 205         dev_priv->saveDSPFW3 = PSB_RVDC32(DSPFW3);
 206         dev_priv->saveDSPFW4 = PSB_RVDC32(DSPFW4);
 207         dev_priv->saveDSPFW5 = PSB_RVDC32(DSPFW5);
 208         dev_priv->saveDSPFW6 = PSB_RVDC32(DSPFW6);
 209         dev_priv->saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
 210
 211         /* Save crtc and output state */
 212         mutex_lock(&dev->mode_config.mutex);
 213         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 214                 if (drm_helper_crtc_in_use(crtc))
 215                         crtc->funcs->save(crtc);
 216         }
 217
 218         list_for_each_entry(connector, &dev->mode_config.connector_list, head)
 219                 connector->funcs->save(connector);
 220
 221         mutex_unlock(&dev->mode_config.mutex);
 222         return 0;
 223 }
 224
 225 /**
 226  *      mrst_restore_display_registers  -       restore lost register state
 227  *      @dev: our DRM device
 228  *
 229  *      Restore register state that was lost during suspend and resume.
 230  */
 231 static int mrst_restore_display_registers(struct drm_device *dev)
 232 {
 233         struct drm_psb_private *dev_priv = dev->dev_private;
 234         struct drm_crtc *crtc;
 235         struct drm_connector *connector;
 236         int pp_stat;
 237
 238         if (!dev_priv->iLVDS_enable) {
 239 #ifdef CONFIG_X86_MRST
 240                 intel_scu_ipc_simple_command(IPC_MSG_PANEL_ON_OFF,
 241                                                         IPC_CMD_PANEL_ON);
 242                 /* FIXME: can we avoid this delay ? */
 243                 msleep(2000); /* wait 2 seconds */
 244 #endif
 245         }
 246
 247         /* Display arbitration + watermarks */
 248         PSB_WVDC32(dev_priv->saveDSPARB, DSPARB);
 249         PSB_WVDC32(dev_priv->saveDSPFW1, DSPFW1);
 250         PSB_WVDC32(dev_priv->saveDSPFW2, DSPFW2);
 251         PSB_WVDC32(dev_priv->saveDSPFW3, DSPFW3);
 252         PSB_WVDC32(dev_priv->saveDSPFW4, DSPFW4);
 253         PSB_WVDC32(dev_priv->saveDSPFW5, DSPFW5);
 254         PSB_WVDC32(dev_priv->saveDSPFW6, DSPFW6);
 255         PSB_WVDC32(dev_priv->saveCHICKENBIT, DSPCHICKENBIT);
 256
 257         /*make sure VGA plane is off. it initializes to on after reset!*/
 258         PSB_WVDC32(0x80000000, VGACNTRL);
 259
 260         mutex_lock(&dev->mode_config.mutex);
 261         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 262                 if (drm_helper_crtc_in_use(crtc))
 263                         crtc->funcs->restore(crtc);
 264
 265         list_for_each_entry(connector, &dev->mode_config.connector_list, head)
 266                 connector->funcs->restore(connector);
 267
 268         mutex_unlock(&dev->mode_config.mutex);
 269
 270         if (dev_priv->iLVDS_enable) {
 271                 /*shutdown the panel*/
 272                 PSB_WVDC32(0, PP_CONTROL);
 273                 do {
 274                         pp_stat = PSB_RVDC32(PP_STATUS);
 275                 } while (pp_stat & 0x80000000);
 276
 277                 /* Turn off the plane */
 278                 PSB_WVDC32(0x58000000, DSPACNTR);
 279                 PSB_WVDC32(0, DSPASURF);/*trigger the plane disable*/
 280                 /* Wait ~4 ticks */
 281                 msleep(4);
 282                 /* Turn off pipe */
 283                 PSB_WVDC32(0x0, PIPEACONF);
 284                 /* Wait ~8 ticks */
 285                 msleep(8);
 286
 287                 /* Turn off PLLs */
 288                 PSB_WVDC32(0, MRST_DPLL_A);
 289         } else {
 290                 PSB_WVDC32(DPI_SHUT_DOWN, DPI_CONTROL_REG);
 291                 PSB_WVDC32(0x0, PIPEACONF);
 292                 PSB_WVDC32(0x2faf0000, BLC_PWM_CTL);
 293                 while (REG_READ(0x70008) & 0x40000000)
 294                         cpu_relax();
 295                 while ((PSB_RVDC32(GEN_FIFO_STAT_REG) & DPI_FIFO_EMPTY)
 296                         != DPI_FIFO_EMPTY)
 297                         cpu_relax();
 298                 PSB_WVDC32(0, DEVICE_READY_REG);
 299                 /* Turn off panel power */
 300 #ifdef CONFIG_X86_MRST  /* FIXME: kill define once modular */
 301                 intel_scu_ipc_simple_command(IPC_MSG_PANEL_ON_OFF,
 302                                                         IPC_CMD_PANEL_OFF);
 303 #endif
 304         }
 305         return 0;
 306 }
 307
 308 /**
 309  *      mrst_power_down -       power down the display island
 310  *      @dev: our DRM device
 311  *
 312  *      Power down the display interface of our device
 313  */
 314 static int mrst_power_down(struct drm_device *dev)
 315 {
 316         struct drm_psb_private *dev_priv = dev->dev_private;
 317         u32 pwr_mask ;
 318         u32 pwr_sts;
 319
 320         pwr_mask = PSB_PWRGT_DISPLAY_MASK;
 321         outl(pwr_mask, dev_priv->ospm_base + PSB_PM_SSC);
 322
 323         while (true) {
 324                 pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
 325                 if ((pwr_sts & pwr_mask) == pwr_mask)
 326                         break;
 327                 else
 328                         udelay(10);
 329         }
 330         return 0;
 331 }
 332
 333 /*
 334  * mrst_power_up
 335  *
 336  * Restore power to the specified island(s) (powergating)
 337  */
 338 static int mrst_power_up(struct drm_device *dev)
 339 {
 340         struct drm_psb_private *dev_priv = dev->dev_private;
 341         u32 pwr_mask = PSB_PWRGT_DISPLAY_MASK;
 342         u32 pwr_sts, pwr_cnt;
 343
 344         pwr_cnt = inl(dev_priv->ospm_base + PSB_PM_SSC);
 345         pwr_cnt &= ~pwr_mask;
 346         outl(pwr_cnt, (dev_priv->ospm_base + PSB_PM_SSC));
 347
 348         while (true) {
 349                 pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
 350                 if ((pwr_sts & pwr_mask) == 0)
 351                         break;
 352                 else
 353                         udelay(10);
 354         }
 355         return 0;
 356 }
 357
 358 static int mrst_chip_setup(struct drm_device *dev)
 359 {
 360         struct drm_psb_private *dev_priv = dev->dev_private;
 361
 362 #if defined(CONFIG_X86_MRST)
 363         if (mrst_identify_cpu())
 364                 return mid_chip_setup(dev);
 365 #endif
 366         dev_priv->ops = &oaktrail_chip_ops;
 367         /* Check - may be better to go via BIOS paths ? */
 368         return mid_chip_setup(dev);
 369 }
 370
 371 const struct psb_ops mrst_chip_ops = {
 372         .name = "Moorestown",
 373         .accel_2d = 1,
 374         .pipes = 1,
 375         .crtcs = 1,
 376         .sgx_offset = MRST_SGX_OFFSET,
 377
 378         .chip_setup = mrst_chip_setup,
 379         .crtc_helper = &mrst_helper_funcs,
 380         .crtc_funcs = &psb_intel_crtc_funcs,
 381
 382         .output_init = mrst_output_init,
 383
 384 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
 385         .backlight_init = mrst_backlight_init,
 386 #endif
 387
 388         .init_pm = mrst_init_pm,
 389         .save_regs = mrst_save_display_registers,
 390         .restore_regs = mrst_restore_display_registers,
 391         .power_down = mrst_power_down,
 392         .power_up = mrst_power_up,
 393 };
 394
 395 static const struct psb_ops oaktrail_chip_ops = {
 396         .name = "Oaktrail",
 397         .accel_2d = 1,
 398         .pipes = 2,
 399         .crtcs = 2,
 400         .sgx_offset = MRST_SGX_OFFSET,
 401
 402         .chip_setup = mid_chip_setup,
 403         .crtc_helper = &mrst_helper_funcs,
 404         .crtc_funcs = &psb_intel_crtc_funcs,
 405
 406         .output_init = mrst_output_init,
 407
 408 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
 409         .backlight_init = mrst_backlight_init,
 410 #endif
 411
 412         .init_pm = mrst_init_pm,
 413         .save_regs = mrst_save_display_registers,
 414         .restore_regs = mrst_restore_display_registers,
 415         .power_down = mrst_power_down,
 416         .power_up = mrst_power_up,
 417 };
 418