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USB: serial: fix whitespace issues
[zen-stable.git] / drivers / usb / dwc3 / gadget.c
blobfa824cfdd2eb42bf0869257303835a4305a16690
1 /**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 #include <linux/kernel.h>
40 #include <linux/delay.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/interrupt.h>
46 #include <linux/io.h>
47 #include <linux/list.h>
48 #include <linux/dma-mapping.h>
49
50 #include <linux/usb/ch9.h>
51 #include <linux/usb/gadget.h>
52
53 #include "core.h"
54 #include "gadget.h"
55 #include "io.h"
56
57 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
58
59 void dwc3_map_buffer_to_dma(struct dwc3_request *req)
60 {
61 struct dwc3 *dwc = req->dep->dwc;
62
63 if (req->request.length == 0) {
64 /* req->request.dma = dwc->setup_buf_addr; */
65 return;
66 }
67
68 if (req->request.dma == DMA_ADDR_INVALID) {
69 req->request.dma = dma_map_single(dwc->dev, req->request.buf,
70 req->request.length, req->direction
71 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
72 req->mapped = true;
73 }
74 }
75
76 void dwc3_unmap_buffer_from_dma(struct dwc3_request *req)
77 {
78 struct dwc3 *dwc = req->dep->dwc;
79
80 if (req->request.length == 0) {
81 req->request.dma = DMA_ADDR_INVALID;
82 return;
83 }
84
85 if (req->mapped) {
86 dma_unmap_single(dwc->dev, req->request.dma,
87 req->request.length, req->direction
88 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
89 req->mapped = 0;
90 req->request.dma = DMA_ADDR_INVALID;
91 }
92 }
93
94 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
95 int status)
96 {
97 struct dwc3 *dwc = dep->dwc;
98
99 if (req->queued) {
100 dep->busy_slot++;
101 /*
102 * Skip LINK TRB. We can't use req->trb and check for
103 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
104 * completed (not the LINK TRB).
105 */
106 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
107 usb_endpoint_xfer_isoc(dep->desc))
108 dep->busy_slot++;
109 }
110 list_del(&req->list);
111
112 if (req->request.status == -EINPROGRESS)
113 req->request.status = status;
114
115 dwc3_unmap_buffer_from_dma(req);
116
117 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
118 req, dep->name, req->request.actual,
119 req->request.length, status);
120
121 spin_unlock(&dwc->lock);
122 req->request.complete(&req->dep->endpoint, &req->request);
123 spin_lock(&dwc->lock);
124 }
125
126 static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
127 {
128 switch (cmd) {
129 case DWC3_DEPCMD_DEPSTARTCFG:
130 return "Start New Configuration";
131 case DWC3_DEPCMD_ENDTRANSFER:
132 return "End Transfer";
133 case DWC3_DEPCMD_UPDATETRANSFER:
134 return "Update Transfer";
135 case DWC3_DEPCMD_STARTTRANSFER:
136 return "Start Transfer";
137 case DWC3_DEPCMD_CLEARSTALL:
138 return "Clear Stall";
139 case DWC3_DEPCMD_SETSTALL:
140 return "Set Stall";
141 case DWC3_DEPCMD_GETSEQNUMBER:
142 return "Get Data Sequence Number";
143 case DWC3_DEPCMD_SETTRANSFRESOURCE:
144 return "Set Endpoint Transfer Resource";
145 case DWC3_DEPCMD_SETEPCONFIG:
146 return "Set Endpoint Configuration";
147 default:
148 return "UNKNOWN command";
149 }
150 }
151
152 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
153 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
154 {
155 struct dwc3_ep *dep = dwc->eps[ep];
156 u32 timeout = 500;
157 u32 reg;
158
159 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
160 dep->name,
161 dwc3_gadget_ep_cmd_string(cmd), params->param0,
162 params->param1, params->param2);
163
164 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
165 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
166 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
167
168 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
169 do {
170 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
171 if (!(reg & DWC3_DEPCMD_CMDACT)) {
172 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
173 DWC3_DEPCMD_STATUS(reg));
174 return 0;
175 }
176
177 /*
178 * We can't sleep here, because it is also called from
179 * interrupt context.
180 */
181 timeout--;
182 if (!timeout)
183 return -ETIMEDOUT;
184
185 udelay(1);
186 } while (1);
187 }
188
189 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
190 struct dwc3_trb_hw *trb)
191 {
192 u32 offset = (char *) trb - (char *) dep->trb_pool;
193
194 return dep->trb_pool_dma + offset;
195 }
196
197 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
198 {
199 struct dwc3 *dwc = dep->dwc;
200
201 if (dep->trb_pool)
202 return 0;
203
204 if (dep->number == 0 || dep->number == 1)
205 return 0;
206
207 dep->trb_pool = dma_alloc_coherent(dwc->dev,
208 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
209 &dep->trb_pool_dma, GFP_KERNEL);
210 if (!dep->trb_pool) {
211 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
212 dep->name);
213 return -ENOMEM;
214 }
215
216 return 0;
217 }
218
219 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
220 {
221 struct dwc3 *dwc = dep->dwc;
222
223 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
224 dep->trb_pool, dep->trb_pool_dma);
225
226 dep->trb_pool = NULL;
227 dep->trb_pool_dma = 0;
228 }
229
230 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
231 {
232 struct dwc3_gadget_ep_cmd_params params;
233 u32 cmd;
234
235 memset(&params, 0x00, sizeof(params));
236
237 if (dep->number != 1) {
238 cmd = DWC3_DEPCMD_DEPSTARTCFG;
239 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
240 if (dep->number > 1) {
241 if (dwc->start_config_issued)
242 return 0;
243 dwc->start_config_issued = true;
244 cmd |= DWC3_DEPCMD_PARAM(2);
245 }
246
247 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
248 }
249
250 return 0;
251 }
252
253 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
254 const struct usb_endpoint_descriptor *desc)
255 {
256 struct dwc3_gadget_ep_cmd_params params;
257
258 memset(&params, 0x00, sizeof(params));
259
260 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
261 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc))
262 | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst);
263
264 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
265 | DWC3_DEPCFG_XFER_NOT_READY_EN;
266
267 if (usb_endpoint_xfer_bulk(desc) && dep->endpoint.max_streams) {
268 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
269 | DWC3_DEPCFG_STREAM_EVENT_EN;
270 dep->stream_capable = true;
271 }
272
273 if (usb_endpoint_xfer_isoc(desc))
274 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
275
276 /*
277 * We are doing 1:1 mapping for endpoints, meaning
278 * Physical Endpoints 2 maps to Logical Endpoint 2 and
279 * so on. We consider the direction bit as part of the physical
280 * endpoint number. So USB endpoint 0x81 is 0x03.
281 */
282 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
283
284 /*
285 * We must use the lower 16 TX FIFOs even though
286 * HW might have more
287 */
288 if (dep->direction)
289 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
290
291 if (desc->bInterval) {
292 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
293 dep->interval = 1 << (desc->bInterval - 1);
294 }
295
296 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
297 DWC3_DEPCMD_SETEPCONFIG, &params);
298 }
299
300 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
301 {
302 struct dwc3_gadget_ep_cmd_params params;
303
304 memset(&params, 0x00, sizeof(params));
305
306 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
307
308 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
309 DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
310 }
311
312 /**
313 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
314 * @dep: endpoint to be initialized
315 * @desc: USB Endpoint Descriptor
316 *
317 * Caller should take care of locking
318 */
319 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
320 const struct usb_endpoint_descriptor *desc)
321 {
322 struct dwc3 *dwc = dep->dwc;
323 u32 reg;
324 int ret = -ENOMEM;
325
326 if (!(dep->flags & DWC3_EP_ENABLED)) {
327 ret = dwc3_gadget_start_config(dwc, dep);
328 if (ret)
329 return ret;
330 }
331
332 ret = dwc3_gadget_set_ep_config(dwc, dep, desc);
333 if (ret)
334 return ret;
335
336 if (!(dep->flags & DWC3_EP_ENABLED)) {
337 struct dwc3_trb_hw *trb_st_hw;
338 struct dwc3_trb_hw *trb_link_hw;
339 struct dwc3_trb trb_link;
340
341 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
342 if (ret)
343 return ret;
344
345 dep->desc = desc;
346 dep->type = usb_endpoint_type(desc);
347 dep->flags |= DWC3_EP_ENABLED;
348
349 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
350 reg |= DWC3_DALEPENA_EP(dep->number);
351 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
352
353 if (!usb_endpoint_xfer_isoc(desc))
354 return 0;
355
356 memset(&trb_link, 0, sizeof(trb_link));
357
358 /* Link TRB for ISOC. The HWO but is never reset */
359 trb_st_hw = &dep->trb_pool[0];
360
361 trb_link.bplh = dwc3_trb_dma_offset(dep, trb_st_hw);
362 trb_link.trbctl = DWC3_TRBCTL_LINK_TRB;
363 trb_link.hwo = true;
364
365 trb_link_hw = &dep->trb_pool[DWC3_TRB_NUM - 1];
366 dwc3_trb_to_hw(&trb_link, trb_link_hw);
367 }
368
369 return 0;
370 }
371
372 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
373 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
374 {
375 struct dwc3_request *req;
376
377 if (!list_empty(&dep->req_queued))
378 dwc3_stop_active_transfer(dwc, dep->number);
379
380 while (!list_empty(&dep->request_list)) {
381 req = next_request(&dep->request_list);
382
383 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
384 }
385 }
386
387 /**
388 * __dwc3_gadget_ep_disable - Disables a HW endpoint
389 * @dep: the endpoint to disable
390 *
391 * This function also removes requests which are currently processed ny the
392 * hardware and those which are not yet scheduled.
393 * Caller should take care of locking.
394 */
395 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
396 {
397 struct dwc3 *dwc = dep->dwc;
398 u32 reg;
399
400 dwc3_remove_requests(dwc, dep);
401
402 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
403 reg &= ~DWC3_DALEPENA_EP(dep->number);
404 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
405
406 dep->stream_capable = false;
407 dep->desc = NULL;
408 dep->type = 0;
409 dep->flags = 0;
410
411 return 0;
412 }
413
414 /* -------------------------------------------------------------------------- */
415
416 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
417 const struct usb_endpoint_descriptor *desc)
418 {
419 return -EINVAL;
420 }
421
422 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
423 {
424 return -EINVAL;
425 }
426
427 /* -------------------------------------------------------------------------- */
428
429 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
430 const struct usb_endpoint_descriptor *desc)
431 {
432 struct dwc3_ep *dep;
433 struct dwc3 *dwc;
434 unsigned long flags;
435 int ret;
436
437 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
438 pr_debug("dwc3: invalid parameters\n");
439 return -EINVAL;
440 }
441
442 if (!desc->wMaxPacketSize) {
443 pr_debug("dwc3: missing wMaxPacketSize\n");
444 return -EINVAL;
445 }
446
447 dep = to_dwc3_ep(ep);
448 dwc = dep->dwc;
449
450 switch (usb_endpoint_type(desc)) {
451 case USB_ENDPOINT_XFER_CONTROL:
452 strncat(dep->name, "-control", sizeof(dep->name));
453 break;
454 case USB_ENDPOINT_XFER_ISOC:
455 strncat(dep->name, "-isoc", sizeof(dep->name));
456 break;
457 case USB_ENDPOINT_XFER_BULK:
458 strncat(dep->name, "-bulk", sizeof(dep->name));
459 break;
460 case USB_ENDPOINT_XFER_INT:
461 strncat(dep->name, "-int", sizeof(dep->name));
462 break;
463 default:
464 dev_err(dwc->dev, "invalid endpoint transfer type\n");
465 }
466
467 if (dep->flags & DWC3_EP_ENABLED) {
468 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
469 dep->name);
470 return 0;
471 }
472
473 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
474
475 spin_lock_irqsave(&dwc->lock, flags);
476 ret = __dwc3_gadget_ep_enable(dep, desc);
477 spin_unlock_irqrestore(&dwc->lock, flags);
478
479 return ret;
480 }
481
482 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
483 {
484 struct dwc3_ep *dep;
485 struct dwc3 *dwc;
486 unsigned long flags;
487 int ret;
488
489 if (!ep) {
490 pr_debug("dwc3: invalid parameters\n");
491 return -EINVAL;
492 }
493
494 dep = to_dwc3_ep(ep);
495 dwc = dep->dwc;
496
497 if (!(dep->flags & DWC3_EP_ENABLED)) {
498 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
499 dep->name);
500 return 0;
501 }
502
503 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
504 dep->number >> 1,
505 (dep->number & 1) ? "in" : "out");
506
507 spin_lock_irqsave(&dwc->lock, flags);
508 ret = __dwc3_gadget_ep_disable(dep);
509 spin_unlock_irqrestore(&dwc->lock, flags);
510
511 return ret;
512 }
513
514 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
515 gfp_t gfp_flags)
516 {
517 struct dwc3_request *req;
518 struct dwc3_ep *dep = to_dwc3_ep(ep);
519 struct dwc3 *dwc = dep->dwc;
520
521 req = kzalloc(sizeof(*req), gfp_flags);
522 if (!req) {
523 dev_err(dwc->dev, "not enough memory\n");
524 return NULL;
525 }
526
527 req->epnum = dep->number;
528 req->dep = dep;
529 req->request.dma = DMA_ADDR_INVALID;
530
531 return &req->request;
532 }
533
534 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
535 struct usb_request *request)
536 {
537 struct dwc3_request *req = to_dwc3_request(request);
538
539 kfree(req);
540 }
541
542 /*
543 * dwc3_prepare_trbs - setup TRBs from requests
544 * @dep: endpoint for which requests are being prepared
545 * @starting: true if the endpoint is idle and no requests are queued.
546 *
547 * The functions goes through the requests list and setups TRBs for the
548 * transfers. The functions returns once there are not more TRBs available or
549 * it run out of requests.
550 */
551 static struct dwc3_request *dwc3_prepare_trbs(struct dwc3_ep *dep,
552 bool starting)
553 {
554 struct dwc3_request *req, *n, *ret = NULL;
555 struct dwc3_trb_hw *trb_hw;
556 struct dwc3_trb trb;
557 u32 trbs_left;
558
559 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
560
561 /* the first request must not be queued */
562 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
563 /*
564 * if busy & slot are equal than it is either full or empty. If we are
565 * starting to proceed requests then we are empty. Otherwise we ar
566 * full and don't do anything
567 */
568 if (!trbs_left) {
569 if (!starting)
570 return NULL;
571 trbs_left = DWC3_TRB_NUM;
572 /*
573 * In case we start from scratch, we queue the ISOC requests
574 * starting from slot 1. This is done because we use ring
575 * buffer and have no LST bit to stop us. Instead, we place
576 * IOC bit TRB_NUM/4. We try to avoid to having an interrupt
577 * after the first request so we start at slot 1 and have
578 * 7 requests proceed before we hit the first IOC.
579 * Other transfer types don't use the ring buffer and are
580 * processed from the first TRB until the last one. Since we
581 * don't wrap around we have to start at the beginning.
582 */
583 if (usb_endpoint_xfer_isoc(dep->desc)) {
584 dep->busy_slot = 1;
585 dep->free_slot = 1;
586 } else {
587 dep->busy_slot = 0;
588 dep->free_slot = 0;
589 }
590 }
591
592 /* The last TRB is a link TRB, not used for xfer */
593 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->desc))
594 return NULL;
595
596 list_for_each_entry_safe(req, n, &dep->request_list, list) {
597 unsigned int last_one = 0;
598 unsigned int cur_slot;
599
600 trb_hw = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
601 cur_slot = dep->free_slot;
602 dep->free_slot++;
603
604 /* Skip the LINK-TRB on ISOC */
605 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
606 usb_endpoint_xfer_isoc(dep->desc))
607 continue;
608
609 dwc3_gadget_move_request_queued(req);
610 memset(&trb, 0, sizeof(trb));
611 trbs_left--;
612
613 /* Is our TRB pool empty? */
614 if (!trbs_left)
615 last_one = 1;
616 /* Is this the last request? */
617 if (list_empty(&dep->request_list))
618 last_one = 1;
619
620 /*
621 * FIXME we shouldn't need to set LST bit always but we are
622 * facing some weird problem with the Hardware where it doesn't
623 * complete even though it has been previously started.
624 *
625 * While we're debugging the problem, as a workaround to
626 * multiple TRBs handling, use only one TRB at a time.
627 */
628 last_one = 1;
629
630 req->trb = trb_hw;
631 if (!ret)
632 ret = req;
633
634 trb.bplh = req->request.dma;
635
636 if (usb_endpoint_xfer_isoc(dep->desc)) {
637 trb.isp_imi = true;
638 trb.csp = true;
639 } else {
640 trb.lst = last_one;
641 }
642
643 if (usb_endpoint_xfer_bulk(dep->desc) && dep->stream_capable)
644 trb.sid_sofn = req->request.stream_id;
645
646 switch (usb_endpoint_type(dep->desc)) {
647 case USB_ENDPOINT_XFER_CONTROL:
648 trb.trbctl = DWC3_TRBCTL_CONTROL_SETUP;
649 break;
650
651 case USB_ENDPOINT_XFER_ISOC:
652 trb.trbctl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
653
654 /* IOC every DWC3_TRB_NUM / 4 so we can refill */
655 if (!(cur_slot % (DWC3_TRB_NUM / 4)))
656 trb.ioc = last_one;
657 break;
658
659 case USB_ENDPOINT_XFER_BULK:
660 case USB_ENDPOINT_XFER_INT:
661 trb.trbctl = DWC3_TRBCTL_NORMAL;
662 break;
663 default:
664 /*
665 * This is only possible with faulty memory because we
666 * checked it already :)
667 */
668 BUG();
669 }
670
671 trb.length = req->request.length;
672 trb.hwo = true;
673
674 dwc3_trb_to_hw(&trb, trb_hw);
675 req->trb_dma = dwc3_trb_dma_offset(dep, trb_hw);
676
677 if (last_one)
678 break;
679 }
680
681 return ret;
682 }
683
684 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
685 int start_new)
686 {
687 struct dwc3_gadget_ep_cmd_params params;
688 struct dwc3_request *req;
689 struct dwc3 *dwc = dep->dwc;
690 int ret;
691 u32 cmd;
692
693 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
694 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
695 return -EBUSY;
696 }
697 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
698
699 /*
700 * If we are getting here after a short-out-packet we don't enqueue any
701 * new requests as we try to set the IOC bit only on the last request.
702 */
703 if (start_new) {
704 if (list_empty(&dep->req_queued))
705 dwc3_prepare_trbs(dep, start_new);
706
707 /* req points to the first request which will be sent */
708 req = next_request(&dep->req_queued);
709 } else {
710 /*
711 * req points to the first request where HWO changed
712 * from 0 to 1
713 */
714 req = dwc3_prepare_trbs(dep, start_new);
715 }
716 if (!req) {
717 dep->flags |= DWC3_EP_PENDING_REQUEST;
718 return 0;
719 }
720
721 memset(&params, 0, sizeof(params));
722 params.param0 = upper_32_bits(req->trb_dma);
723 params.param1 = lower_32_bits(req->trb_dma);
724
725 if (start_new)
726 cmd = DWC3_DEPCMD_STARTTRANSFER;
727 else
728 cmd = DWC3_DEPCMD_UPDATETRANSFER;
729
730 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
731 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
732 if (ret < 0) {
733 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
734
735 /*
736 * FIXME we need to iterate over the list of requests
737 * here and stop, unmap, free and del each of the linked
738 * requests instead of we do now.
739 */
740 dwc3_unmap_buffer_from_dma(req);
741 list_del(&req->list);
742 return ret;
743 }
744
745 dep->flags |= DWC3_EP_BUSY;
746 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
747 dep->number);
748 if (!dep->res_trans_idx)
749 printk_once(KERN_ERR "%s() res_trans_idx is invalid\n", __func__);
750 return 0;
751 }
752
753 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
754 {
755 req->request.actual = 0;
756 req->request.status = -EINPROGRESS;
757 req->direction = dep->direction;
758 req->epnum = dep->number;
759
760 /*
761 * We only add to our list of requests now and
762 * start consuming the list once we get XferNotReady
763 * IRQ.
764 *
765 * That way, we avoid doing anything that we don't need
766 * to do now and defer it until the point we receive a
767 * particular token from the Host side.
768 *
769 * This will also avoid Host cancelling URBs due to too
770 * many NACKs.
771 */
772 dwc3_map_buffer_to_dma(req);
773 list_add_tail(&req->list, &dep->request_list);
774
775 /*
776 * There is one special case: XferNotReady with
777 * empty list of requests. We need to kick the
778 * transfer here in that situation, otherwise
779 * we will be NAKing forever.
780 *
781 * If we get XferNotReady before gadget driver
782 * has a chance to queue a request, we will ACK
783 * the IRQ but won't be able to receive the data
784 * until the next request is queued. The following
785 * code is handling exactly that.
786 */
787 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
788 int ret;
789 int start_trans;
790
791 start_trans = 1;
792 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
793 dep->flags & DWC3_EP_BUSY)
794 start_trans = 0;
795
796 ret = __dwc3_gadget_kick_transfer(dep, 0, start_trans);
797 if (ret && ret != -EBUSY) {
798 struct dwc3 *dwc = dep->dwc;
799
800 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
801 dep->name);
802 }
803 };
804
805 return 0;
806 }
807
808 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
809 gfp_t gfp_flags)
810 {
811 struct dwc3_request *req = to_dwc3_request(request);
812 struct dwc3_ep *dep = to_dwc3_ep(ep);
813 struct dwc3 *dwc = dep->dwc;
814
815 unsigned long flags;
816
817 int ret;
818
819 if (!dep->desc) {
820 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
821 request, ep->name);
822 return -ESHUTDOWN;
823 }
824
825 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
826 request, ep->name, request->length);
827
828 spin_lock_irqsave(&dwc->lock, flags);
829 ret = __dwc3_gadget_ep_queue(dep, req);
830 spin_unlock_irqrestore(&dwc->lock, flags);
831
832 return ret;
833 }
834
835 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
836 struct usb_request *request)
837 {
838 struct dwc3_request *req = to_dwc3_request(request);
839 struct dwc3_request *r = NULL;
840
841 struct dwc3_ep *dep = to_dwc3_ep(ep);
842 struct dwc3 *dwc = dep->dwc;
843
844 unsigned long flags;
845 int ret = 0;
846
847 spin_lock_irqsave(&dwc->lock, flags);
848
849 list_for_each_entry(r, &dep->request_list, list) {
850 if (r == req)
851 break;
852 }
853
854 if (r != req) {
855 list_for_each_entry(r, &dep->req_queued, list) {
856 if (r == req)
857 break;
858 }
859 if (r == req) {
860 /* wait until it is processed */
861 dwc3_stop_active_transfer(dwc, dep->number);
862 goto out0;
863 }
864 dev_err(dwc->dev, "request %p was not queued to %s\n",
865 request, ep->name);
866 ret = -EINVAL;
867 goto out0;
868 }
869
870 /* giveback the request */
871 dwc3_gadget_giveback(dep, req, -ECONNRESET);
872
873 out0:
874 spin_unlock_irqrestore(&dwc->lock, flags);
875
876 return ret;
877 }
878
879 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
880 {
881 struct dwc3_gadget_ep_cmd_params params;
882 struct dwc3 *dwc = dep->dwc;
883 int ret;
884
885 memset(&params, 0x00, sizeof(params));
886
887 if (value) {
888 if (dep->number == 0 || dep->number == 1) {
889 /*
890 * Whenever EP0 is stalled, we will restart
891 * the state machine, thus moving back to
892 * Setup Phase
893 */
894 dwc->ep0state = EP0_SETUP_PHASE;
895 }
896
897 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
898 DWC3_DEPCMD_SETSTALL, &params);
899 if (ret)
900 dev_err(dwc->dev, "failed to %s STALL on %s\n",
901 value ? "set" : "clear",
902 dep->name);
903 else
904 dep->flags |= DWC3_EP_STALL;
905 } else {
906 if (dep->flags & DWC3_EP_WEDGE)
907 return 0;
908
909 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
910 DWC3_DEPCMD_CLEARSTALL, &params);
911 if (ret)
912 dev_err(dwc->dev, "failed to %s STALL on %s\n",
913 value ? "set" : "clear",
914 dep->name);
915 else
916 dep->flags &= ~DWC3_EP_STALL;
917 }
918
919 return ret;
920 }
921
922 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
923 {
924 struct dwc3_ep *dep = to_dwc3_ep(ep);
925 struct dwc3 *dwc = dep->dwc;
926
927 unsigned long flags;
928
929 int ret;
930
931 spin_lock_irqsave(&dwc->lock, flags);
932
933 if (usb_endpoint_xfer_isoc(dep->desc)) {
934 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
935 ret = -EINVAL;
936 goto out;
937 }
938
939 ret = __dwc3_gadget_ep_set_halt(dep, value);
940 out:
941 spin_unlock_irqrestore(&dwc->lock, flags);
942
943 return ret;
944 }
945
946 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
947 {
948 struct dwc3_ep *dep = to_dwc3_ep(ep);
949
950 dep->flags |= DWC3_EP_WEDGE;
951
952 return dwc3_gadget_ep_set_halt(ep, 1);
953 }
954
955 /* -------------------------------------------------------------------------- */
956
957 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
958 .bLength = USB_DT_ENDPOINT_SIZE,
959 .bDescriptorType = USB_DT_ENDPOINT,
960 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
961 };
962
963 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
964 .enable = dwc3_gadget_ep0_enable,
965 .disable = dwc3_gadget_ep0_disable,
966 .alloc_request = dwc3_gadget_ep_alloc_request,
967 .free_request = dwc3_gadget_ep_free_request,
968 .queue = dwc3_gadget_ep0_queue,
969 .dequeue = dwc3_gadget_ep_dequeue,
970 .set_halt = dwc3_gadget_ep_set_halt,
971 .set_wedge = dwc3_gadget_ep_set_wedge,
972 };
973
974 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
975 .enable = dwc3_gadget_ep_enable,
976 .disable = dwc3_gadget_ep_disable,
977 .alloc_request = dwc3_gadget_ep_alloc_request,
978 .free_request = dwc3_gadget_ep_free_request,
979 .queue = dwc3_gadget_ep_queue,
980 .dequeue = dwc3_gadget_ep_dequeue,
981 .set_halt = dwc3_gadget_ep_set_halt,
982 .set_wedge = dwc3_gadget_ep_set_wedge,
983 };
984
985 /* -------------------------------------------------------------------------- */
986
987 static int dwc3_gadget_get_frame(struct usb_gadget *g)
988 {
989 struct dwc3 *dwc = gadget_to_dwc(g);
990 u32 reg;
991
992 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
993 return DWC3_DSTS_SOFFN(reg);
994 }
995
996 static int dwc3_gadget_wakeup(struct usb_gadget *g)
997 {
998 struct dwc3 *dwc = gadget_to_dwc(g);
999
1000 unsigned long timeout;
1001 unsigned long flags;
1002
1003 u32 reg;
1004
1005 int ret = 0;
1006
1007 u8 link_state;
1008 u8 speed;
1009
1010 spin_lock_irqsave(&dwc->lock, flags);
1011
1012 /*
1013 * According to the Databook Remote wakeup request should
1014 * be issued only when the device is in early suspend state.
1015 *
1016 * We can check that via USB Link State bits in DSTS register.
1017 */
1018 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1019
1020 speed = reg & DWC3_DSTS_CONNECTSPD;
1021 if (speed == DWC3_DSTS_SUPERSPEED) {
1022 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1023 ret = -EINVAL;
1024 goto out;
1025 }
1026
1027 link_state = DWC3_DSTS_USBLNKST(reg);
1028
1029 switch (link_state) {
1030 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1031 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1032 break;
1033 default:
1034 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1035 link_state);
1036 ret = -EINVAL;
1037 goto out;
1038 }
1039
1040 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1041
1042 /*
1043 * Switch link state to Recovery. In HS/FS/LS this means
1044 * RemoteWakeup Request
1045 */
1046 reg |= DWC3_DCTL_ULSTCHNG_RECOVERY;
1047 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1048
1049 /* wait for at least 2000us */
1050 usleep_range(2000, 2500);
1051
1052 /* write zeroes to Link Change Request */
1053 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1054 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1055
1056 /* pool until Link State change to ON */
1057 timeout = jiffies + msecs_to_jiffies(100);
1058
1059 while (!(time_after(jiffies, timeout))) {
1060 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1061
1062 /* in HS, means ON */
1063 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1064 break;
1065 }
1066
1067 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1068 dev_err(dwc->dev, "failed to send remote wakeup\n");
1069 ret = -EINVAL;
1070 }
1071
1072 out:
1073 spin_unlock_irqrestore(&dwc->lock, flags);
1074
1075 return ret;
1076 }
1077
1078 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1079 int is_selfpowered)
1080 {
1081 struct dwc3 *dwc = gadget_to_dwc(g);
1082
1083 dwc->is_selfpowered = !!is_selfpowered;
1084
1085 return 0;
1086 }
1087
1088 static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1089 {
1090 u32 reg;
1091 u32 timeout = 500;
1092
1093 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1094 if (is_on)
1095 reg |= DWC3_DCTL_RUN_STOP;
1096 else
1097 reg &= ~DWC3_DCTL_RUN_STOP;
1098
1099 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1100
1101 do {
1102 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1103 if (is_on) {
1104 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1105 break;
1106 } else {
1107 if (reg & DWC3_DSTS_DEVCTRLHLT)
1108 break;
1109 }
1110 timeout--;
1111 if (!timeout)
1112 break;
1113 udelay(1);
1114 } while (1);
1115
1116 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1117 dwc->gadget_driver
1118 ? dwc->gadget_driver->function : "no-function",
1119 is_on ? "connect" : "disconnect");
1120 }
1121
1122 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1123 {
1124 struct dwc3 *dwc = gadget_to_dwc(g);
1125 unsigned long flags;
1126
1127 is_on = !!is_on;
1128
1129 spin_lock_irqsave(&dwc->lock, flags);
1130 dwc3_gadget_run_stop(dwc, is_on);
1131 spin_unlock_irqrestore(&dwc->lock, flags);
1132
1133 return 0;
1134 }
1135
1136 static int dwc3_gadget_start(struct usb_gadget *g,
1137 struct usb_gadget_driver *driver)
1138 {
1139 struct dwc3 *dwc = gadget_to_dwc(g);
1140 struct dwc3_ep *dep;
1141 unsigned long flags;
1142 int ret = 0;
1143 u32 reg;
1144
1145 spin_lock_irqsave(&dwc->lock, flags);
1146
1147 if (dwc->gadget_driver) {
1148 dev_err(dwc->dev, "%s is already bound to %s\n",
1149 dwc->gadget.name,
1150 dwc->gadget_driver->driver.name);
1151 ret = -EBUSY;
1152 goto err0;
1153 }
1154
1155 dwc->gadget_driver = driver;
1156 dwc->gadget.dev.driver = &driver->driver;
1157
1158 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1159
1160 reg &= ~DWC3_GCTL_SCALEDOWN(3);
1161 reg &= ~DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG);
1162 reg &= ~DWC3_GCTL_DISSCRAMBLE;
1163 reg |= DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_DEVICE);
1164
1165 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams0)) {
1166 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
1167 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
1168 break;
1169 default:
1170 dev_dbg(dwc->dev, "No power optimization available\n");
1171 }
1172
1173 /*
1174 * WORKAROUND: DWC3 revisions <1.90a have a bug
1175 * when The device fails to connect at SuperSpeed
1176 * and falls back to high-speed mode which causes
1177 * the device to enter in a Connect/Disconnect loop
1178 */
1179 if (dwc->revision < DWC3_REVISION_190A)
1180 reg |= DWC3_GCTL_U2RSTECN;
1181
1182 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1183
1184 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1185 reg &= ~(DWC3_DCFG_SPEED_MASK);
1186 reg |= DWC3_DCFG_SUPERSPEED;
1187 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1188
1189 dwc->start_config_issued = false;
1190
1191 /* Start with SuperSpeed Default */
1192 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1193
1194 dep = dwc->eps[0];
1195 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1196 if (ret) {
1197 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1198 goto err0;
1199 }
1200
1201 dep = dwc->eps[1];
1202 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1203 if (ret) {
1204 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1205 goto err1;
1206 }
1207
1208 /* begin to receive SETUP packets */
1209 dwc->ep0state = EP0_SETUP_PHASE;
1210 dwc3_ep0_out_start(dwc);
1211
1212 spin_unlock_irqrestore(&dwc->lock, flags);
1213
1214 return 0;
1215
1216 err1:
1217 __dwc3_gadget_ep_disable(dwc->eps[0]);
1218
1219 err0:
1220 spin_unlock_irqrestore(&dwc->lock, flags);
1221
1222 return ret;
1223 }
1224
1225 static int dwc3_gadget_stop(struct usb_gadget *g,
1226 struct usb_gadget_driver *driver)
1227 {
1228 struct dwc3 *dwc = gadget_to_dwc(g);
1229 unsigned long flags;
1230
1231 spin_lock_irqsave(&dwc->lock, flags);
1232
1233 __dwc3_gadget_ep_disable(dwc->eps[0]);
1234 __dwc3_gadget_ep_disable(dwc->eps[1]);
1235
1236 dwc->gadget_driver = NULL;
1237 dwc->gadget.dev.driver = NULL;
1238
1239 spin_unlock_irqrestore(&dwc->lock, flags);
1240
1241 return 0;
1242 }
1243 static const struct usb_gadget_ops dwc3_gadget_ops = {
1244 .get_frame = dwc3_gadget_get_frame,
1245 .wakeup = dwc3_gadget_wakeup,
1246 .set_selfpowered = dwc3_gadget_set_selfpowered,
1247 .pullup = dwc3_gadget_pullup,
1248 .udc_start = dwc3_gadget_start,
1249 .udc_stop = dwc3_gadget_stop,
1250 };
1251
1252 /* -------------------------------------------------------------------------- */
1253
1254 static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1255 {
1256 struct dwc3_ep *dep;
1257 u8 epnum;
1258
1259 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1260
1261 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1262 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1263 if (!dep) {
1264 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1265 epnum);
1266 return -ENOMEM;
1267 }
1268
1269 dep->dwc = dwc;
1270 dep->number = epnum;
1271 dwc->eps[epnum] = dep;
1272
1273 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1274 (epnum & 1) ? "in" : "out");
1275 dep->endpoint.name = dep->name;
1276 dep->direction = (epnum & 1);
1277
1278 if (epnum == 0 || epnum == 1) {
1279 dep->endpoint.maxpacket = 512;
1280 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1281 if (!epnum)
1282 dwc->gadget.ep0 = &dep->endpoint;
1283 } else {
1284 int ret;
1285
1286 dep->endpoint.maxpacket = 1024;
1287 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1288 list_add_tail(&dep->endpoint.ep_list,
1289 &dwc->gadget.ep_list);
1290
1291 ret = dwc3_alloc_trb_pool(dep);
1292 if (ret) {
1293 dev_err(dwc->dev, "%s: failed to allocate TRB pool\n", dep->name);
1294 return ret;
1295 }
1296 }
1297 INIT_LIST_HEAD(&dep->request_list);
1298 INIT_LIST_HEAD(&dep->req_queued);
1299 }
1300
1301 return 0;
1302 }
1303
1304 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1305 {
1306 struct dwc3_ep *dep;
1307 u8 epnum;
1308
1309 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1310 dep = dwc->eps[epnum];
1311 dwc3_free_trb_pool(dep);
1312
1313 if (epnum != 0 && epnum != 1)
1314 list_del(&dep->endpoint.ep_list);
1315
1316 kfree(dep);
1317 }
1318 }
1319
1320 static void dwc3_gadget_release(struct device *dev)
1321 {
1322 dev_dbg(dev, "%s\n", __func__);
1323 }
1324
1325 /* -------------------------------------------------------------------------- */
1326 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1327 const struct dwc3_event_depevt *event, int status)
1328 {
1329 struct dwc3_request *req;
1330 struct dwc3_trb trb;
1331 unsigned int count;
1332 unsigned int s_pkt = 0;
1333
1334 do {
1335 req = next_request(&dep->req_queued);
1336 if (!req)
1337 break;
1338
1339 dwc3_trb_to_nat(req->trb, &trb);
1340
1341 if (trb.hwo && status != -ESHUTDOWN)
1342 /*
1343 * We continue despite the error. There is not much we
1344 * can do. If we don't clean in up we loop for ever. If
1345 * we skip the TRB than it gets overwritten reused after
1346 * a while since we use them in a ring buffer. a BUG()
1347 * would help. Lets hope that if this occures, someone
1348 * fixes the root cause instead of looking away :)
1349 */
1350 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1351 dep->name, req->trb);
1352 count = trb.length;
1353
1354 if (dep->direction) {
1355 if (count) {
1356 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1357 dep->name);
1358 status = -ECONNRESET;
1359 }
1360 } else {
1361 if (count && (event->status & DEPEVT_STATUS_SHORT))
1362 s_pkt = 1;
1363 }
1364
1365 /*
1366 * We assume here we will always receive the entire data block
1367 * which we should receive. Meaning, if we program RX to
1368 * receive 4K but we receive only 2K, we assume that's all we
1369 * should receive and we simply bounce the request back to the
1370 * gadget driver for further processing.
1371 */
1372 req->request.actual += req->request.length - count;
1373 dwc3_gadget_giveback(dep, req, status);
1374 if (s_pkt)
1375 break;
1376 if ((event->status & DEPEVT_STATUS_LST) && trb.lst)
1377 break;
1378 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc)
1379 break;
1380 } while (1);
1381
1382 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc)
1383 return 0;
1384 return 1;
1385 }
1386
1387 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1388 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1389 int start_new)
1390 {
1391 unsigned status = 0;
1392 int clean_busy;
1393
1394 if (event->status & DEPEVT_STATUS_BUSERR)
1395 status = -ECONNRESET;
1396
1397 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1398 if (clean_busy) {
1399 dep->flags &= ~DWC3_EP_BUSY;
1400 dep->res_trans_idx = 0;
1401 }
1402 }
1403
1404 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1405 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1406 {
1407 u32 uf;
1408
1409 if (list_empty(&dep->request_list)) {
1410 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1411 dep->name);
1412 return;
1413 }
1414
1415 if (event->parameters) {
1416 u32 mask;
1417
1418 mask = ~(dep->interval - 1);
1419 uf = event->parameters & mask;
1420 /* 4 micro frames in the future */
1421 uf += dep->interval * 4;
1422 } else {
1423 uf = 0;
1424 }
1425
1426 __dwc3_gadget_kick_transfer(dep, uf, 1);
1427 }
1428
1429 static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep,
1430 const struct dwc3_event_depevt *event)
1431 {
1432 struct dwc3 *dwc = dep->dwc;
1433 struct dwc3_event_depevt mod_ev = *event;
1434
1435 /*
1436 * We were asked to remove one requests. It is possible that this
1437 * request and a few other were started together and have the same
1438 * transfer index. Since we stopped the complete endpoint we don't
1439 * know how many requests were already completed (and not yet)
1440 * reported and how could be done (later). We purge them all until
1441 * the end of the list.
1442 */
1443 mod_ev.status = DEPEVT_STATUS_LST;
1444 dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN);
1445 dep->flags &= ~DWC3_EP_BUSY;
1446 /* pending requets are ignored and are queued on XferNotReady */
1447 }
1448
1449 static void dwc3_ep_cmd_compl(struct dwc3_ep *dep,
1450 const struct dwc3_event_depevt *event)
1451 {
1452 u32 param = event->parameters;
1453 u32 cmd_type = (param >> 8) & ((1 << 5) - 1);
1454
1455 switch (cmd_type) {
1456 case DWC3_DEPCMD_ENDTRANSFER:
1457 dwc3_process_ep_cmd_complete(dep, event);
1458 break;
1459 case DWC3_DEPCMD_STARTTRANSFER:
1460 dep->res_trans_idx = param & 0x7f;
1461 break;
1462 default:
1463 printk(KERN_ERR "%s() unknown /unexpected type: %d\n",
1464 __func__, cmd_type);
1465 break;
1466 };
1467 }
1468
1469 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1470 const struct dwc3_event_depevt *event)
1471 {
1472 struct dwc3_ep *dep;
1473 u8 epnum = event->endpoint_number;
1474
1475 dep = dwc->eps[epnum];
1476
1477 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1478 dwc3_ep_event_string(event->endpoint_event));
1479
1480 if (epnum == 0 || epnum == 1) {
1481 dwc3_ep0_interrupt(dwc, event);
1482 return;
1483 }
1484
1485 switch (event->endpoint_event) {
1486 case DWC3_DEPEVT_XFERCOMPLETE:
1487 if (usb_endpoint_xfer_isoc(dep->desc)) {
1488 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1489 dep->name);
1490 return;
1491 }
1492
1493 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1494 break;
1495 case DWC3_DEPEVT_XFERINPROGRESS:
1496 if (!usb_endpoint_xfer_isoc(dep->desc)) {
1497 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1498 dep->name);
1499 return;
1500 }
1501
1502 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1503 break;
1504 case DWC3_DEPEVT_XFERNOTREADY:
1505 if (usb_endpoint_xfer_isoc(dep->desc)) {
1506 dwc3_gadget_start_isoc(dwc, dep, event);
1507 } else {
1508 int ret;
1509
1510 dev_vdbg(dwc->dev, "%s: reason %s\n",
1511 dep->name, event->status
1512 ? "Transfer Active"
1513 : "Transfer Not Active");
1514
1515 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1516 if (!ret || ret == -EBUSY)
1517 return;
1518
1519 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1520 dep->name);
1521 }
1522
1523 break;
1524 case DWC3_DEPEVT_STREAMEVT:
1525 if (!usb_endpoint_xfer_bulk(dep->desc)) {
1526 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1527 dep->name);
1528 return;
1529 }
1530
1531 switch (event->status) {
1532 case DEPEVT_STREAMEVT_FOUND:
1533 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1534 event->parameters);
1535
1536 break;
1537 case DEPEVT_STREAMEVT_NOTFOUND:
1538 /* FALLTHROUGH */
1539 default:
1540 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1541 }
1542 break;
1543 case DWC3_DEPEVT_RXTXFIFOEVT:
1544 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1545 break;
1546 case DWC3_DEPEVT_EPCMDCMPLT:
1547 dwc3_ep_cmd_compl(dep, event);
1548 break;
1549 }
1550 }
1551
1552 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1553 {
1554 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1555 spin_unlock(&dwc->lock);
1556 dwc->gadget_driver->disconnect(&dwc->gadget);
1557 spin_lock(&dwc->lock);
1558 }
1559 }
1560
1561 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
1562 {
1563 struct dwc3_ep *dep;
1564 struct dwc3_gadget_ep_cmd_params params;
1565 u32 cmd;
1566 int ret;
1567
1568 dep = dwc->eps[epnum];
1569
1570 WARN_ON(!dep->res_trans_idx);
1571 if (dep->res_trans_idx) {
1572 cmd = DWC3_DEPCMD_ENDTRANSFER;
1573 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
1574 cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx);
1575 memset(&params, 0, sizeof(params));
1576 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1577 WARN_ON_ONCE(ret);
1578 dep->res_trans_idx = 0;
1579 }
1580 }
1581
1582 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1583 {
1584 u32 epnum;
1585
1586 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1587 struct dwc3_ep *dep;
1588
1589 dep = dwc->eps[epnum];
1590 if (!(dep->flags & DWC3_EP_ENABLED))
1591 continue;
1592
1593 dwc3_remove_requests(dwc, dep);
1594 }
1595 }
1596
1597 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
1598 {
1599 u32 epnum;
1600
1601 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1602 struct dwc3_ep *dep;
1603 struct dwc3_gadget_ep_cmd_params params;
1604 int ret;
1605
1606 dep = dwc->eps[epnum];
1607
1608 if (!(dep->flags & DWC3_EP_STALL))
1609 continue;
1610
1611 dep->flags &= ~DWC3_EP_STALL;
1612
1613 memset(&params, 0, sizeof(params));
1614 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1615 DWC3_DEPCMD_CLEARSTALL, &params);
1616 WARN_ON_ONCE(ret);
1617 }
1618 }
1619
1620 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
1621 {
1622 dev_vdbg(dwc->dev, "%s\n", __func__);
1623 #if 0
1624 XXX
1625 U1/U2 is powersave optimization. Skip it for now. Anyway we need to
1626 enable it before we can disable it.
1627
1628 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1629 reg &= ~DWC3_DCTL_INITU1ENA;
1630 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1631
1632 reg &= ~DWC3_DCTL_INITU2ENA;
1633 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1634 #endif
1635
1636 dwc3_stop_active_transfers(dwc);
1637 dwc3_disconnect_gadget(dwc);
1638 dwc->start_config_issued = false;
1639
1640 dwc->gadget.speed = USB_SPEED_UNKNOWN;
1641 }
1642
1643 static void dwc3_gadget_usb3_phy_power(struct dwc3 *dwc, int on)
1644 {
1645 u32 reg;
1646
1647 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1648
1649 if (on)
1650 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
1651 else
1652 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1653
1654 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1655 }
1656
1657 static void dwc3_gadget_usb2_phy_power(struct dwc3 *dwc, int on)
1658 {
1659 u32 reg;
1660
1661 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1662
1663 if (on)
1664 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1665 else
1666 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1667
1668 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1669 }
1670
1671 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
1672 {
1673 u32 reg;
1674
1675 dev_vdbg(dwc->dev, "%s\n", __func__);
1676
1677 /* Enable PHYs */
1678 dwc3_gadget_usb2_phy_power(dwc, true);
1679 dwc3_gadget_usb3_phy_power(dwc, true);
1680
1681 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
1682 dwc3_disconnect_gadget(dwc);
1683
1684 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1685 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
1686 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1687
1688 dwc3_stop_active_transfers(dwc);
1689 dwc3_clear_stall_all_ep(dwc);
1690 dwc->start_config_issued = false;
1691
1692 /* Reset device address to zero */
1693 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1694 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
1695 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1696 }
1697
1698 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
1699 {
1700 u32 reg;
1701 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
1702
1703 /*
1704 * We change the clock only at SS but I dunno why I would want to do
1705 * this. Maybe it becomes part of the power saving plan.
1706 */
1707
1708 if (speed != DWC3_DSTS_SUPERSPEED)
1709 return;
1710
1711 /*
1712 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
1713 * each time on Connect Done.
1714 */
1715 if (!usb30_clock)
1716 return;
1717
1718 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1719 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
1720 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1721 }
1722
1723 static void dwc3_gadget_disable_phy(struct dwc3 *dwc, u8 speed)
1724 {
1725 switch (speed) {
1726 case USB_SPEED_SUPER:
1727 dwc3_gadget_usb2_phy_power(dwc, false);
1728 break;
1729 case USB_SPEED_HIGH:
1730 case USB_SPEED_FULL:
1731 case USB_SPEED_LOW:
1732 dwc3_gadget_usb3_phy_power(dwc, false);
1733 break;
1734 }
1735 }
1736
1737 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
1738 {
1739 struct dwc3_gadget_ep_cmd_params params;
1740 struct dwc3_ep *dep;
1741 int ret;
1742 u32 reg;
1743 u8 speed;
1744
1745 dev_vdbg(dwc->dev, "%s\n", __func__);
1746
1747 memset(&params, 0x00, sizeof(params));
1748
1749 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1750 speed = reg & DWC3_DSTS_CONNECTSPD;
1751 dwc->speed = speed;
1752
1753 dwc3_update_ram_clk_sel(dwc, speed);
1754
1755 switch (speed) {
1756 case DWC3_DCFG_SUPERSPEED:
1757 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1758 dwc->gadget.ep0->maxpacket = 512;
1759 dwc->gadget.speed = USB_SPEED_SUPER;
1760 break;
1761 case DWC3_DCFG_HIGHSPEED:
1762 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
1763 dwc->gadget.ep0->maxpacket = 64;
1764 dwc->gadget.speed = USB_SPEED_HIGH;
1765 break;
1766 case DWC3_DCFG_FULLSPEED2:
1767 case DWC3_DCFG_FULLSPEED1:
1768 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
1769 dwc->gadget.ep0->maxpacket = 64;
1770 dwc->gadget.speed = USB_SPEED_FULL;
1771 break;
1772 case DWC3_DCFG_LOWSPEED:
1773 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
1774 dwc->gadget.ep0->maxpacket = 8;
1775 dwc->gadget.speed = USB_SPEED_LOW;
1776 break;
1777 }
1778
1779 /* Disable unneded PHY */
1780 dwc3_gadget_disable_phy(dwc, dwc->gadget.speed);
1781
1782 dep = dwc->eps[0];
1783 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1784 if (ret) {
1785 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1786 return;
1787 }
1788
1789 dep = dwc->eps[1];
1790 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1791 if (ret) {
1792 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1793 return;
1794 }
1795
1796 /*
1797 * Configure PHY via GUSB3PIPECTLn if required.
1798 *
1799 * Update GTXFIFOSIZn
1800 *
1801 * In both cases reset values should be sufficient.
1802 */
1803 }
1804
1805 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
1806 {
1807 dev_vdbg(dwc->dev, "%s\n", __func__);
1808
1809 /*
1810 * TODO take core out of low power mode when that's
1811 * implemented.
1812 */
1813
1814 dwc->gadget_driver->resume(&dwc->gadget);
1815 }
1816
1817 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
1818 unsigned int evtinfo)
1819 {
1820 /* The fith bit says SuperSpeed yes or no. */
1821 dwc->link_state = evtinfo & DWC3_LINK_STATE_MASK;
1822
1823 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
1824 }
1825
1826 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
1827 const struct dwc3_event_devt *event)
1828 {
1829 switch (event->type) {
1830 case DWC3_DEVICE_EVENT_DISCONNECT:
1831 dwc3_gadget_disconnect_interrupt(dwc);
1832 break;
1833 case DWC3_DEVICE_EVENT_RESET:
1834 dwc3_gadget_reset_interrupt(dwc);
1835 break;
1836 case DWC3_DEVICE_EVENT_CONNECT_DONE:
1837 dwc3_gadget_conndone_interrupt(dwc);
1838 break;
1839 case DWC3_DEVICE_EVENT_WAKEUP:
1840 dwc3_gadget_wakeup_interrupt(dwc);
1841 break;
1842 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
1843 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
1844 break;
1845 case DWC3_DEVICE_EVENT_EOPF:
1846 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
1847 break;
1848 case DWC3_DEVICE_EVENT_SOF:
1849 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
1850 break;
1851 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
1852 dev_vdbg(dwc->dev, "Erratic Error\n");
1853 break;
1854 case DWC3_DEVICE_EVENT_CMD_CMPL:
1855 dev_vdbg(dwc->dev, "Command Complete\n");
1856 break;
1857 case DWC3_DEVICE_EVENT_OVERFLOW:
1858 dev_vdbg(dwc->dev, "Overflow\n");
1859 break;
1860 default:
1861 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
1862 }
1863 }
1864
1865 static void dwc3_process_event_entry(struct dwc3 *dwc,
1866 const union dwc3_event *event)
1867 {
1868 /* Endpoint IRQ, handle it and return early */
1869 if (event->type.is_devspec == 0) {
1870 /* depevt */
1871 return dwc3_endpoint_interrupt(dwc, &event->depevt);
1872 }
1873
1874 switch (event->type.type) {
1875 case DWC3_EVENT_TYPE_DEV:
1876 dwc3_gadget_interrupt(dwc, &event->devt);
1877 break;
1878 /* REVISIT what to do with Carkit and I2C events ? */
1879 default:
1880 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
1881 }
1882 }
1883
1884 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
1885 {
1886 struct dwc3_event_buffer *evt;
1887 int left;
1888 u32 count;
1889
1890 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
1891 count &= DWC3_GEVNTCOUNT_MASK;
1892 if (!count)
1893 return IRQ_NONE;
1894
1895 evt = dwc->ev_buffs[buf];
1896 left = count;
1897
1898 while (left > 0) {
1899 union dwc3_event event;
1900
1901 memcpy(&event.raw, (evt->buf + evt->lpos), sizeof(event.raw));
1902 dwc3_process_event_entry(dwc, &event);
1903 /*
1904 * XXX we wrap around correctly to the next entry as almost all
1905 * entries are 4 bytes in size. There is one entry which has 12
1906 * bytes which is a regular entry followed by 8 bytes data. ATM
1907 * I don't know how things are organized if were get next to the
1908 * a boundary so I worry about that once we try to handle that.
1909 */
1910 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
1911 left -= 4;
1912
1913 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
1914 }
1915
1916 return IRQ_HANDLED;
1917 }
1918
1919 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
1920 {
1921 struct dwc3 *dwc = _dwc;
1922 int i;
1923 irqreturn_t ret = IRQ_NONE;
1924
1925 spin_lock(&dwc->lock);
1926
1927 for (i = 0; i < DWC3_EVENT_BUFFERS_NUM; i++) {
1928 irqreturn_t status;
1929
1930 status = dwc3_process_event_buf(dwc, i);
1931 if (status == IRQ_HANDLED)
1932 ret = status;
1933 }
1934
1935 spin_unlock(&dwc->lock);
1936
1937 return ret;
1938 }
1939
1940 /**
1941 * dwc3_gadget_init - Initializes gadget related registers
1942 * @dwc: Pointer to out controller context structure
1943 *
1944 * Returns 0 on success otherwise negative errno.
1945 */
1946 int __devinit dwc3_gadget_init(struct dwc3 *dwc)
1947 {
1948 u32 reg;
1949 int ret;
1950 int irq;
1951
1952 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
1953 &dwc->ctrl_req_addr, GFP_KERNEL);
1954 if (!dwc->ctrl_req) {
1955 dev_err(dwc->dev, "failed to allocate ctrl request\n");
1956 ret = -ENOMEM;
1957 goto err0;
1958 }
1959
1960 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
1961 &dwc->ep0_trb_addr, GFP_KERNEL);
1962 if (!dwc->ep0_trb) {
1963 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
1964 ret = -ENOMEM;
1965 goto err1;
1966 }
1967
1968 dwc->setup_buf = dma_alloc_coherent(dwc->dev,
1969 sizeof(*dwc->setup_buf) * 2,
1970 &dwc->setup_buf_addr, GFP_KERNEL);
1971 if (!dwc->setup_buf) {
1972 dev_err(dwc->dev, "failed to allocate setup buffer\n");
1973 ret = -ENOMEM;
1974 goto err2;
1975 }
1976
1977 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
1978 512, &dwc->ep0_bounce_addr, GFP_KERNEL);
1979 if (!dwc->ep0_bounce) {
1980 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
1981 ret = -ENOMEM;
1982 goto err3;
1983 }
1984
1985 dev_set_name(&dwc->gadget.dev, "gadget");
1986
1987 dwc->gadget.ops = &dwc3_gadget_ops;
1988 dwc->gadget.is_dualspeed = true;
1989 dwc->gadget.speed = USB_SPEED_UNKNOWN;
1990 dwc->gadget.dev.parent = dwc->dev;
1991
1992 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
1993
1994 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms;
1995 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask;
1996 dwc->gadget.dev.release = dwc3_gadget_release;
1997 dwc->gadget.name = "dwc3-gadget";
1998
1999 /*
2000 * REVISIT: Here we should clear all pending IRQs to be
2001 * sure we're starting from a well known location.
2002 */
2003
2004 ret = dwc3_gadget_init_endpoints(dwc);
2005 if (ret)
2006 goto err4;
2007
2008 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2009
2010 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
2011 "dwc3", dwc);
2012 if (ret) {
2013 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2014 irq, ret);
2015 goto err5;
2016 }
2017
2018 /* Enable all but Start and End of Frame IRQs */
2019 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
2020 DWC3_DEVTEN_EVNTOVERFLOWEN |
2021 DWC3_DEVTEN_CMDCMPLTEN |
2022 DWC3_DEVTEN_ERRTICERREN |
2023 DWC3_DEVTEN_WKUPEVTEN |
2024 DWC3_DEVTEN_ULSTCNGEN |
2025 DWC3_DEVTEN_CONNECTDONEEN |
2026 DWC3_DEVTEN_USBRSTEN |
2027 DWC3_DEVTEN_DISCONNEVTEN);
2028 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2029
2030 ret = device_register(&dwc->gadget.dev);
2031 if (ret) {
2032 dev_err(dwc->dev, "failed to register gadget device\n");
2033 put_device(&dwc->gadget.dev);
2034 goto err6;
2035 }
2036
2037 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2038 if (ret) {
2039 dev_err(dwc->dev, "failed to register udc\n");
2040 goto err7;
2041 }
2042
2043 return 0;
2044
2045 err7:
2046 device_unregister(&dwc->gadget.dev);
2047
2048 err6:
2049 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2050 free_irq(irq, dwc);
2051
2052 err5:
2053 dwc3_gadget_free_endpoints(dwc);
2054
2055 err4:
2056 dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce,
2057 dwc->ep0_bounce_addr);
2058
2059 err3:
2060 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
2061 dwc->setup_buf, dwc->setup_buf_addr);
2062
2063 err2:
2064 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2065 dwc->ep0_trb, dwc->ep0_trb_addr);
2066
2067 err1:
2068 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2069 dwc->ctrl_req, dwc->ctrl_req_addr);
2070
2071 err0:
2072 return ret;
2073 }
2074
2075 void dwc3_gadget_exit(struct dwc3 *dwc)
2076 {
2077 int irq;
2078 int i;
2079
2080 usb_del_gadget_udc(&dwc->gadget);
2081 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2082
2083 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2084 free_irq(irq, dwc);
2085
2086 for (i = 0; i < ARRAY_SIZE(dwc->eps); i++)
2087 __dwc3_gadget_ep_disable(dwc->eps[i]);
2088
2089 dwc3_gadget_free_endpoints(dwc);
2090
2091 dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce,
2092 dwc->ep0_bounce_addr);
2093
2094 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
2095 dwc->setup_buf, dwc->setup_buf_addr);
2096
2097 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2098 dwc->ep0_trb, dwc->ep0_trb_addr);
2099
2100 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2101 dwc->ctrl_req, dwc->ctrl_req_addr);
2102
2103 device_unregister(&dwc->gadget.dev);
2104 }