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USB: serial: fix whitespace issues
[zen-stable.git] / drivers / usb / gadget / pch_udc.c
blob550d6dcdf10454253cdb3d93f6a7d86219ce4a50
1 /*
2 * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 */
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/delay.h>
13 #include <linux/errno.h>
14 #include <linux/list.h>
15 #include <linux/interrupt.h>
16 #include <linux/usb/ch9.h>
17 #include <linux/usb/gadget.h>
18
19 /* Address offset of Registers */
20 #define UDC_EP_REG_SHIFT 0x20 /* Offset to next EP */
21
22 #define UDC_EPCTL_ADDR 0x00 /* Endpoint control */
23 #define UDC_EPSTS_ADDR 0x04 /* Endpoint status */
24 #define UDC_BUFIN_FRAMENUM_ADDR 0x08 /* buffer size in / frame number out */
25 #define UDC_BUFOUT_MAXPKT_ADDR 0x0C /* buffer size out / maxpkt in */
26 #define UDC_SUBPTR_ADDR 0x10 /* setup buffer pointer */
27 #define UDC_DESPTR_ADDR 0x14 /* Data descriptor pointer */
28 #define UDC_CONFIRM_ADDR 0x18 /* Write/Read confirmation */
29
30 #define UDC_DEVCFG_ADDR 0x400 /* Device configuration */
31 #define UDC_DEVCTL_ADDR 0x404 /* Device control */
32 #define UDC_DEVSTS_ADDR 0x408 /* Device status */
33 #define UDC_DEVIRQSTS_ADDR 0x40C /* Device irq status */
34 #define UDC_DEVIRQMSK_ADDR 0x410 /* Device irq mask */
35 #define UDC_EPIRQSTS_ADDR 0x414 /* Endpoint irq status */
36 #define UDC_EPIRQMSK_ADDR 0x418 /* Endpoint irq mask */
37 #define UDC_DEVLPM_ADDR 0x41C /* LPM control / status */
38 #define UDC_CSR_BUSY_ADDR 0x4f0 /* UDC_CSR_BUSY Status register */
39 #define UDC_SRST_ADDR 0x4fc /* SOFT RESET register */
40 #define UDC_CSR_ADDR 0x500 /* USB_DEVICE endpoint register */
41
42 /* Endpoint control register */
43 /* Bit position */
44 #define UDC_EPCTL_MRXFLUSH (1 << 12)
45 #define UDC_EPCTL_RRDY (1 << 9)
46 #define UDC_EPCTL_CNAK (1 << 8)
47 #define UDC_EPCTL_SNAK (1 << 7)
48 #define UDC_EPCTL_NAK (1 << 6)
49 #define UDC_EPCTL_P (1 << 3)
50 #define UDC_EPCTL_F (1 << 1)
51 #define UDC_EPCTL_S (1 << 0)
52 #define UDC_EPCTL_ET_SHIFT 4
53 /* Mask patern */
54 #define UDC_EPCTL_ET_MASK 0x00000030
55 /* Value for ET field */
56 #define UDC_EPCTL_ET_CONTROL 0
57 #define UDC_EPCTL_ET_ISO 1
58 #define UDC_EPCTL_ET_BULK 2
59 #define UDC_EPCTL_ET_INTERRUPT 3
60
61 /* Endpoint status register */
62 /* Bit position */
63 #define UDC_EPSTS_XFERDONE (1 << 27)
64 #define UDC_EPSTS_RSS (1 << 26)
65 #define UDC_EPSTS_RCS (1 << 25)
66 #define UDC_EPSTS_TXEMPTY (1 << 24)
67 #define UDC_EPSTS_TDC (1 << 10)
68 #define UDC_EPSTS_HE (1 << 9)
69 #define UDC_EPSTS_MRXFIFO_EMP (1 << 8)
70 #define UDC_EPSTS_BNA (1 << 7)
71 #define UDC_EPSTS_IN (1 << 6)
72 #define UDC_EPSTS_OUT_SHIFT 4
73 /* Mask patern */
74 #define UDC_EPSTS_OUT_MASK 0x00000030
75 #define UDC_EPSTS_ALL_CLR_MASK 0x1F0006F0
76 /* Value for OUT field */
77 #define UDC_EPSTS_OUT_SETUP 2
78 #define UDC_EPSTS_OUT_DATA 1
79
80 /* Device configuration register */
81 /* Bit position */
82 #define UDC_DEVCFG_CSR_PRG (1 << 17)
83 #define UDC_DEVCFG_SP (1 << 3)
84 /* SPD Valee */
85 #define UDC_DEVCFG_SPD_HS 0x0
86 #define UDC_DEVCFG_SPD_FS 0x1
87 #define UDC_DEVCFG_SPD_LS 0x2
88
89 /* Device control register */
90 /* Bit position */
91 #define UDC_DEVCTL_THLEN_SHIFT 24
92 #define UDC_DEVCTL_BRLEN_SHIFT 16
93 #define UDC_DEVCTL_CSR_DONE (1 << 13)
94 #define UDC_DEVCTL_SD (1 << 10)
95 #define UDC_DEVCTL_MODE (1 << 9)
96 #define UDC_DEVCTL_BREN (1 << 8)
97 #define UDC_DEVCTL_THE (1 << 7)
98 #define UDC_DEVCTL_DU (1 << 4)
99 #define UDC_DEVCTL_TDE (1 << 3)
100 #define UDC_DEVCTL_RDE (1 << 2)
101 #define UDC_DEVCTL_RES (1 << 0)
102
103 /* Device status register */
104 /* Bit position */
105 #define UDC_DEVSTS_TS_SHIFT 18
106 #define UDC_DEVSTS_ENUM_SPEED_SHIFT 13
107 #define UDC_DEVSTS_ALT_SHIFT 8
108 #define UDC_DEVSTS_INTF_SHIFT 4
109 #define UDC_DEVSTS_CFG_SHIFT 0
110 /* Mask patern */
111 #define UDC_DEVSTS_TS_MASK 0xfffc0000
112 #define UDC_DEVSTS_ENUM_SPEED_MASK 0x00006000
113 #define UDC_DEVSTS_ALT_MASK 0x00000f00
114 #define UDC_DEVSTS_INTF_MASK 0x000000f0
115 #define UDC_DEVSTS_CFG_MASK 0x0000000f
116 /* value for maximum speed for SPEED field */
117 #define UDC_DEVSTS_ENUM_SPEED_FULL 1
118 #define UDC_DEVSTS_ENUM_SPEED_HIGH 0
119 #define UDC_DEVSTS_ENUM_SPEED_LOW 2
120 #define UDC_DEVSTS_ENUM_SPEED_FULLX 3
121
122 /* Device irq register */
123 /* Bit position */
124 #define UDC_DEVINT_RWKP (1 << 7)
125 #define UDC_DEVINT_ENUM (1 << 6)
126 #define UDC_DEVINT_SOF (1 << 5)
127 #define UDC_DEVINT_US (1 << 4)
128 #define UDC_DEVINT_UR (1 << 3)
129 #define UDC_DEVINT_ES (1 << 2)
130 #define UDC_DEVINT_SI (1 << 1)
131 #define UDC_DEVINT_SC (1 << 0)
132 /* Mask patern */
133 #define UDC_DEVINT_MSK 0x7f
134
135 /* Endpoint irq register */
136 /* Bit position */
137 #define UDC_EPINT_IN_SHIFT 0
138 #define UDC_EPINT_OUT_SHIFT 16
139 #define UDC_EPINT_IN_EP0 (1 << 0)
140 #define UDC_EPINT_OUT_EP0 (1 << 16)
141 /* Mask patern */
142 #define UDC_EPINT_MSK_DISABLE_ALL 0xffffffff
143
144 /* UDC_CSR_BUSY Status register */
145 /* Bit position */
146 #define UDC_CSR_BUSY (1 << 0)
147
148 /* SOFT RESET register */
149 /* Bit position */
150 #define UDC_PSRST (1 << 1)
151 #define UDC_SRST (1 << 0)
152
153 /* USB_DEVICE endpoint register */
154 /* Bit position */
155 #define UDC_CSR_NE_NUM_SHIFT 0
156 #define UDC_CSR_NE_DIR_SHIFT 4
157 #define UDC_CSR_NE_TYPE_SHIFT 5
158 #define UDC_CSR_NE_CFG_SHIFT 7
159 #define UDC_CSR_NE_INTF_SHIFT 11
160 #define UDC_CSR_NE_ALT_SHIFT 15
161 #define UDC_CSR_NE_MAX_PKT_SHIFT 19
162 /* Mask patern */
163 #define UDC_CSR_NE_NUM_MASK 0x0000000f
164 #define UDC_CSR_NE_DIR_MASK 0x00000010
165 #define UDC_CSR_NE_TYPE_MASK 0x00000060
166 #define UDC_CSR_NE_CFG_MASK 0x00000780
167 #define UDC_CSR_NE_INTF_MASK 0x00007800
168 #define UDC_CSR_NE_ALT_MASK 0x00078000
169 #define UDC_CSR_NE_MAX_PKT_MASK 0x3ff80000
170
171 #define PCH_UDC_CSR(ep) (UDC_CSR_ADDR + ep*4)
172 #define PCH_UDC_EPINT(in, num)\
173 (1 << (num + (in ? UDC_EPINT_IN_SHIFT : UDC_EPINT_OUT_SHIFT)))
174
175 /* Index of endpoint */
176 #define UDC_EP0IN_IDX 0
177 #define UDC_EP0OUT_IDX 1
178 #define UDC_EPIN_IDX(ep) (ep * 2)
179 #define UDC_EPOUT_IDX(ep) (ep * 2 + 1)
180 #define PCH_UDC_EP0 0
181 #define PCH_UDC_EP1 1
182 #define PCH_UDC_EP2 2
183 #define PCH_UDC_EP3 3
184
185 /* Number of endpoint */
186 #define PCH_UDC_EP_NUM 32 /* Total number of EPs (16 IN,16 OUT) */
187 #define PCH_UDC_USED_EP_NUM 4 /* EP number of EP's really used */
188 /* Length Value */
189 #define PCH_UDC_BRLEN 0x0F /* Burst length */
190 #define PCH_UDC_THLEN 0x1F /* Threshold length */
191 /* Value of EP Buffer Size */
192 #define UDC_EP0IN_BUFF_SIZE 16
193 #define UDC_EPIN_BUFF_SIZE 256
194 #define UDC_EP0OUT_BUFF_SIZE 16
195 #define UDC_EPOUT_BUFF_SIZE 256
196 /* Value of EP maximum packet size */
197 #define UDC_EP0IN_MAX_PKT_SIZE 64
198 #define UDC_EP0OUT_MAX_PKT_SIZE 64
199 #define UDC_BULK_MAX_PKT_SIZE 512
200
201 /* DMA */
202 #define DMA_DIR_RX 1 /* DMA for data receive */
203 #define DMA_DIR_TX 2 /* DMA for data transmit */
204 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
205 #define UDC_DMA_MAXPACKET 65536 /* maximum packet size for DMA */
206
207 /**
208 * struct pch_udc_data_dma_desc - Structure to hold DMA descriptor information
209 * for data
210 * @status: Status quadlet
211 * @reserved: Reserved
212 * @dataptr: Buffer descriptor
213 * @next: Next descriptor
214 */
215 struct pch_udc_data_dma_desc {
216 u32 status;
217 u32 reserved;
218 u32 dataptr;
219 u32 next;
220 };
221
222 /**
223 * struct pch_udc_stp_dma_desc - Structure to hold DMA descriptor information
224 * for control data
225 * @status: Status
226 * @reserved: Reserved
227 * @data12: First setup word
228 * @data34: Second setup word
229 */
230 struct pch_udc_stp_dma_desc {
231 u32 status;
232 u32 reserved;
233 struct usb_ctrlrequest request;
234 } __attribute((packed));
235
236 /* DMA status definitions */
237 /* Buffer status */
238 #define PCH_UDC_BUFF_STS 0xC0000000
239 #define PCH_UDC_BS_HST_RDY 0x00000000
240 #define PCH_UDC_BS_DMA_BSY 0x40000000
241 #define PCH_UDC_BS_DMA_DONE 0x80000000
242 #define PCH_UDC_BS_HST_BSY 0xC0000000
243 /* Rx/Tx Status */
244 #define PCH_UDC_RXTX_STS 0x30000000
245 #define PCH_UDC_RTS_SUCC 0x00000000
246 #define PCH_UDC_RTS_DESERR 0x10000000
247 #define PCH_UDC_RTS_BUFERR 0x30000000
248 /* Last Descriptor Indication */
249 #define PCH_UDC_DMA_LAST 0x08000000
250 /* Number of Rx/Tx Bytes Mask */
251 #define PCH_UDC_RXTX_BYTES 0x0000ffff
252
253 /**
254 * struct pch_udc_cfg_data - Structure to hold current configuration
255 * and interface information
256 * @cur_cfg: current configuration in use
257 * @cur_intf: current interface in use
258 * @cur_alt: current alt interface in use
259 */
260 struct pch_udc_cfg_data {
261 u16 cur_cfg;
262 u16 cur_intf;
263 u16 cur_alt;
264 };
265
266 /**
267 * struct pch_udc_ep - Structure holding a PCH USB device Endpoint information
268 * @ep: embedded ep request
269 * @td_stp_phys: for setup request
270 * @td_data_phys: for data request
271 * @td_stp: for setup request
272 * @td_data: for data request
273 * @dev: reference to device struct
274 * @offset_addr: offset address of ep register
275 * @desc: for this ep
276 * @queue: queue for requests
277 * @num: endpoint number
278 * @in: endpoint is IN
279 * @halted: endpoint halted?
280 * @epsts: Endpoint status
281 */
282 struct pch_udc_ep {
283 struct usb_ep ep;
284 dma_addr_t td_stp_phys;
285 dma_addr_t td_data_phys;
286 struct pch_udc_stp_dma_desc *td_stp;
287 struct pch_udc_data_dma_desc *td_data;
288 struct pch_udc_dev *dev;
289 unsigned long offset_addr;
290 const struct usb_endpoint_descriptor *desc;
291 struct list_head queue;
292 unsigned num:5,
293 in:1,
294 halted:1;
295 unsigned long epsts;
296 };
297
298 /**
299 * struct pch_udc_dev - Structure holding complete information
300 * of the PCH USB device
301 * @gadget: gadget driver data
302 * @driver: reference to gadget driver bound
303 * @pdev: reference to the PCI device
304 * @ep: array of endpoints
305 * @lock: protects all state
306 * @active: enabled the PCI device
307 * @stall: stall requested
308 * @prot_stall: protcol stall requested
309 * @irq_registered: irq registered with system
310 * @mem_region: device memory mapped
311 * @registered: driver regsitered with system
312 * @suspended: driver in suspended state
313 * @connected: gadget driver associated
314 * @set_cfg_not_acked: pending acknowledgement 4 setup
315 * @waiting_zlp_ack: pending acknowledgement 4 ZLP
316 * @data_requests: DMA pool for data requests
317 * @stp_requests: DMA pool for setup requests
318 * @dma_addr: DMA pool for received
319 * @ep0out_buf: Buffer for DMA
320 * @setup_data: Received setup data
321 * @phys_addr: of device memory
322 * @base_addr: for mapped device memory
323 * @irq: IRQ line for the device
324 * @cfg_data: current cfg, intf, and alt in use
325 */
326 struct pch_udc_dev {
327 struct usb_gadget gadget;
328 struct usb_gadget_driver *driver;
329 struct pci_dev *pdev;
330 struct pch_udc_ep ep[PCH_UDC_EP_NUM];
331 spinlock_t lock; /* protects all state */
332 unsigned active:1,
333 stall:1,
334 prot_stall:1,
335 irq_registered:1,
336 mem_region:1,
337 registered:1,
338 suspended:1,
339 connected:1,
340 set_cfg_not_acked:1,
341 waiting_zlp_ack:1;
342 struct pci_pool *data_requests;
343 struct pci_pool *stp_requests;
344 dma_addr_t dma_addr;
345 void *ep0out_buf;
346 struct usb_ctrlrequest setup_data;
347 unsigned long phys_addr;
348 void __iomem *base_addr;
349 unsigned irq;
350 struct pch_udc_cfg_data cfg_data;
351 };
352
353 #define PCH_UDC_PCI_BAR 1
354 #define PCI_DEVICE_ID_INTEL_EG20T_UDC 0x8808
355 #define PCI_VENDOR_ID_ROHM 0x10DB
356 #define PCI_DEVICE_ID_ML7213_IOH_UDC 0x801D
357
358 static const char ep0_string[] = "ep0in";
359 static DEFINE_SPINLOCK(udc_stall_spinlock); /* stall spin lock */
360 struct pch_udc_dev *pch_udc; /* pointer to device object */
361 static int speed_fs;
362 module_param_named(speed_fs, speed_fs, bool, S_IRUGO);
363 MODULE_PARM_DESC(speed_fs, "true for Full speed operation");
364
365 /**
366 * struct pch_udc_request - Structure holding a PCH USB device request packet
367 * @req: embedded ep request
368 * @td_data_phys: phys. address
369 * @td_data: first dma desc. of chain
370 * @td_data_last: last dma desc. of chain
371 * @queue: associated queue
372 * @dma_going: DMA in progress for request
373 * @dma_mapped: DMA memory mapped for request
374 * @dma_done: DMA completed for request
375 * @chain_len: chain length
376 * @buf: Buffer memory for align adjustment
377 * @dma: DMA memory for align adjustment
378 */
379 struct pch_udc_request {
380 struct usb_request req;
381 dma_addr_t td_data_phys;
382 struct pch_udc_data_dma_desc *td_data;
383 struct pch_udc_data_dma_desc *td_data_last;
384 struct list_head queue;
385 unsigned dma_going:1,
386 dma_mapped:1,
387 dma_done:1;
388 unsigned chain_len;
389 void *buf;
390 dma_addr_t dma;
391 };
392
393 static inline u32 pch_udc_readl(struct pch_udc_dev *dev, unsigned long reg)
394 {
395 return ioread32(dev->base_addr + reg);
396 }
397
398 static inline void pch_udc_writel(struct pch_udc_dev *dev,
399 unsigned long val, unsigned long reg)
400 {
401 iowrite32(val, dev->base_addr + reg);
402 }
403
404 static inline void pch_udc_bit_set(struct pch_udc_dev *dev,
405 unsigned long reg,
406 unsigned long bitmask)
407 {
408 pch_udc_writel(dev, pch_udc_readl(dev, reg) | bitmask, reg);
409 }
410
411 static inline void pch_udc_bit_clr(struct pch_udc_dev *dev,
412 unsigned long reg,
413 unsigned long bitmask)
414 {
415 pch_udc_writel(dev, pch_udc_readl(dev, reg) & ~(bitmask), reg);
416 }
417
418 static inline u32 pch_udc_ep_readl(struct pch_udc_ep *ep, unsigned long reg)
419 {
420 return ioread32(ep->dev->base_addr + ep->offset_addr + reg);
421 }
422
423 static inline void pch_udc_ep_writel(struct pch_udc_ep *ep,
424 unsigned long val, unsigned long reg)
425 {
426 iowrite32(val, ep->dev->base_addr + ep->offset_addr + reg);
427 }
428
429 static inline void pch_udc_ep_bit_set(struct pch_udc_ep *ep,
430 unsigned long reg,
431 unsigned long bitmask)
432 {
433 pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) | bitmask, reg);
434 }
435
436 static inline void pch_udc_ep_bit_clr(struct pch_udc_ep *ep,
437 unsigned long reg,
438 unsigned long bitmask)
439 {
440 pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) & ~(bitmask), reg);
441 }
442
443 /**
444 * pch_udc_csr_busy() - Wait till idle.
445 * @dev: Reference to pch_udc_dev structure
446 */
447 static void pch_udc_csr_busy(struct pch_udc_dev *dev)
448 {
449 unsigned int count = 200;
450
451 /* Wait till idle */
452 while ((pch_udc_readl(dev, UDC_CSR_BUSY_ADDR) & UDC_CSR_BUSY)
453 && --count)
454 cpu_relax();
455 if (!count)
456 dev_err(&dev->pdev->dev, "%s: wait error\n", __func__);
457 }
458
459 /**
460 * pch_udc_write_csr() - Write the command and status registers.
461 * @dev: Reference to pch_udc_dev structure
462 * @val: value to be written to CSR register
463 * @addr: address of CSR register
464 */
465 static void pch_udc_write_csr(struct pch_udc_dev *dev, unsigned long val,
466 unsigned int ep)
467 {
468 unsigned long reg = PCH_UDC_CSR(ep);
469
470 pch_udc_csr_busy(dev); /* Wait till idle */
471 pch_udc_writel(dev, val, reg);
472 pch_udc_csr_busy(dev); /* Wait till idle */
473 }
474
475 /**
476 * pch_udc_read_csr() - Read the command and status registers.
477 * @dev: Reference to pch_udc_dev structure
478 * @addr: address of CSR register
479 *
480 * Return codes: content of CSR register
481 */
482 static u32 pch_udc_read_csr(struct pch_udc_dev *dev, unsigned int ep)
483 {
484 unsigned long reg = PCH_UDC_CSR(ep);
485
486 pch_udc_csr_busy(dev); /* Wait till idle */
487 pch_udc_readl(dev, reg); /* Dummy read */
488 pch_udc_csr_busy(dev); /* Wait till idle */
489 return pch_udc_readl(dev, reg);
490 }
491
492 /**
493 * pch_udc_rmt_wakeup() - Initiate for remote wakeup
494 * @dev: Reference to pch_udc_dev structure
495 */
496 static inline void pch_udc_rmt_wakeup(struct pch_udc_dev *dev)
497 {
498 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
499 mdelay(1);
500 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
501 }
502
503 /**
504 * pch_udc_get_frame() - Get the current frame from device status register
505 * @dev: Reference to pch_udc_dev structure
506 * Retern current frame
507 */
508 static inline int pch_udc_get_frame(struct pch_udc_dev *dev)
509 {
510 u32 frame = pch_udc_readl(dev, UDC_DEVSTS_ADDR);
511 return (frame & UDC_DEVSTS_TS_MASK) >> UDC_DEVSTS_TS_SHIFT;
512 }
513
514 /**
515 * pch_udc_clear_selfpowered() - Clear the self power control
516 * @dev: Reference to pch_udc_regs structure
517 */
518 static inline void pch_udc_clear_selfpowered(struct pch_udc_dev *dev)
519 {
520 pch_udc_bit_clr(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
521 }
522
523 /**
524 * pch_udc_set_selfpowered() - Set the self power control
525 * @dev: Reference to pch_udc_regs structure
526 */
527 static inline void pch_udc_set_selfpowered(struct pch_udc_dev *dev)
528 {
529 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
530 }
531
532 /**
533 * pch_udc_set_disconnect() - Set the disconnect status.
534 * @dev: Reference to pch_udc_regs structure
535 */
536 static inline void pch_udc_set_disconnect(struct pch_udc_dev *dev)
537 {
538 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
539 }
540
541 /**
542 * pch_udc_clear_disconnect() - Clear the disconnect status.
543 * @dev: Reference to pch_udc_regs structure
544 */
545 static void pch_udc_clear_disconnect(struct pch_udc_dev *dev)
546 {
547 /* Clear the disconnect */
548 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
549 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
550 mdelay(1);
551 /* Resume USB signalling */
552 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
553 }
554
555 /**
556 * pch_udc_vbus_session() - set or clearr the disconnect status.
557 * @dev: Reference to pch_udc_regs structure
558 * @is_active: Parameter specifying the action
559 * 0: indicating VBUS power is ending
560 * !0: indicating VBUS power is starting
561 */
562 static inline void pch_udc_vbus_session(struct pch_udc_dev *dev,
563 int is_active)
564 {
565 if (is_active)
566 pch_udc_clear_disconnect(dev);
567 else
568 pch_udc_set_disconnect(dev);
569 }
570
571 /**
572 * pch_udc_ep_set_stall() - Set the stall of endpoint
573 * @ep: Reference to structure of type pch_udc_ep_regs
574 */
575 static void pch_udc_ep_set_stall(struct pch_udc_ep *ep)
576 {
577 if (ep->in) {
578 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
579 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
580 } else {
581 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
582 }
583 }
584
585 /**
586 * pch_udc_ep_clear_stall() - Clear the stall of endpoint
587 * @ep: Reference to structure of type pch_udc_ep_regs
588 */
589 static inline void pch_udc_ep_clear_stall(struct pch_udc_ep *ep)
590 {
591 /* Clear the stall */
592 pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
593 /* Clear NAK by writing CNAK */
594 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
595 }
596
597 /**
598 * pch_udc_ep_set_trfr_type() - Set the transfer type of endpoint
599 * @ep: Reference to structure of type pch_udc_ep_regs
600 * @type: Type of endpoint
601 */
602 static inline void pch_udc_ep_set_trfr_type(struct pch_udc_ep *ep,
603 u8 type)
604 {
605 pch_udc_ep_writel(ep, ((type << UDC_EPCTL_ET_SHIFT) &
606 UDC_EPCTL_ET_MASK), UDC_EPCTL_ADDR);
607 }
608
609 /**
610 * pch_udc_ep_set_bufsz() - Set the maximum packet size for the endpoint
611 * @ep: Reference to structure of type pch_udc_ep_regs
612 * @buf_size: The buffer word size
613 */
614 static void pch_udc_ep_set_bufsz(struct pch_udc_ep *ep,
615 u32 buf_size, u32 ep_in)
616 {
617 u32 data;
618 if (ep_in) {
619 data = pch_udc_ep_readl(ep, UDC_BUFIN_FRAMENUM_ADDR);
620 data = (data & 0xffff0000) | (buf_size & 0xffff);
621 pch_udc_ep_writel(ep, data, UDC_BUFIN_FRAMENUM_ADDR);
622 } else {
623 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
624 data = (buf_size << 16) | (data & 0xffff);
625 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
626 }
627 }
628
629 /**
630 * pch_udc_ep_set_maxpkt() - Set the Max packet size for the endpoint
631 * @ep: Reference to structure of type pch_udc_ep_regs
632 * @pkt_size: The packet byte size
633 */
634 static void pch_udc_ep_set_maxpkt(struct pch_udc_ep *ep, u32 pkt_size)
635 {
636 u32 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
637 data = (data & 0xffff0000) | (pkt_size & 0xffff);
638 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
639 }
640
641 /**
642 * pch_udc_ep_set_subptr() - Set the Setup buffer pointer for the endpoint
643 * @ep: Reference to structure of type pch_udc_ep_regs
644 * @addr: Address of the register
645 */
646 static inline void pch_udc_ep_set_subptr(struct pch_udc_ep *ep, u32 addr)
647 {
648 pch_udc_ep_writel(ep, addr, UDC_SUBPTR_ADDR);
649 }
650
651 /**
652 * pch_udc_ep_set_ddptr() - Set the Data descriptor pointer for the endpoint
653 * @ep: Reference to structure of type pch_udc_ep_regs
654 * @addr: Address of the register
655 */
656 static inline void pch_udc_ep_set_ddptr(struct pch_udc_ep *ep, u32 addr)
657 {
658 pch_udc_ep_writel(ep, addr, UDC_DESPTR_ADDR);
659 }
660
661 /**
662 * pch_udc_ep_set_pd() - Set the poll demand bit for the endpoint
663 * @ep: Reference to structure of type pch_udc_ep_regs
664 */
665 static inline void pch_udc_ep_set_pd(struct pch_udc_ep *ep)
666 {
667 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_P);
668 }
669
670 /**
671 * pch_udc_ep_set_rrdy() - Set the receive ready bit for the endpoint
672 * @ep: Reference to structure of type pch_udc_ep_regs
673 */
674 static inline void pch_udc_ep_set_rrdy(struct pch_udc_ep *ep)
675 {
676 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
677 }
678
679 /**
680 * pch_udc_ep_clear_rrdy() - Clear the receive ready bit for the endpoint
681 * @ep: Reference to structure of type pch_udc_ep_regs
682 */
683 static inline void pch_udc_ep_clear_rrdy(struct pch_udc_ep *ep)
684 {
685 pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
686 }
687
688 /**
689 * pch_udc_set_dma() - Set the 'TDE' or RDE bit of device control
690 * register depending on the direction specified
691 * @dev: Reference to structure of type pch_udc_regs
692 * @dir: whether Tx or Rx
693 * DMA_DIR_RX: Receive
694 * DMA_DIR_TX: Transmit
695 */
696 static inline void pch_udc_set_dma(struct pch_udc_dev *dev, int dir)
697 {
698 if (dir == DMA_DIR_RX)
699 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
700 else if (dir == DMA_DIR_TX)
701 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
702 }
703
704 /**
705 * pch_udc_clear_dma() - Clear the 'TDE' or RDE bit of device control
706 * register depending on the direction specified
707 * @dev: Reference to structure of type pch_udc_regs
708 * @dir: Whether Tx or Rx
709 * DMA_DIR_RX: Receive
710 * DMA_DIR_TX: Transmit
711 */
712 static inline void pch_udc_clear_dma(struct pch_udc_dev *dev, int dir)
713 {
714 if (dir == DMA_DIR_RX)
715 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
716 else if (dir == DMA_DIR_TX)
717 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
718 }
719
720 /**
721 * pch_udc_set_csr_done() - Set the device control register
722 * CSR done field (bit 13)
723 * @dev: reference to structure of type pch_udc_regs
724 */
725 static inline void pch_udc_set_csr_done(struct pch_udc_dev *dev)
726 {
727 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_CSR_DONE);
728 }
729
730 /**
731 * pch_udc_disable_interrupts() - Disables the specified interrupts
732 * @dev: Reference to structure of type pch_udc_regs
733 * @mask: Mask to disable interrupts
734 */
735 static inline void pch_udc_disable_interrupts(struct pch_udc_dev *dev,
736 u32 mask)
737 {
738 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, mask);
739 }
740
741 /**
742 * pch_udc_enable_interrupts() - Enable the specified interrupts
743 * @dev: Reference to structure of type pch_udc_regs
744 * @mask: Mask to enable interrupts
745 */
746 static inline void pch_udc_enable_interrupts(struct pch_udc_dev *dev,
747 u32 mask)
748 {
749 pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR, mask);
750 }
751
752 /**
753 * pch_udc_disable_ep_interrupts() - Disable endpoint interrupts
754 * @dev: Reference to structure of type pch_udc_regs
755 * @mask: Mask to disable interrupts
756 */
757 static inline void pch_udc_disable_ep_interrupts(struct pch_udc_dev *dev,
758 u32 mask)
759 {
760 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, mask);
761 }
762
763 /**
764 * pch_udc_enable_ep_interrupts() - Enable endpoint interrupts
765 * @dev: Reference to structure of type pch_udc_regs
766 * @mask: Mask to enable interrupts
767 */
768 static inline void pch_udc_enable_ep_interrupts(struct pch_udc_dev *dev,
769 u32 mask)
770 {
771 pch_udc_bit_clr(dev, UDC_EPIRQMSK_ADDR, mask);
772 }
773
774 /**
775 * pch_udc_read_device_interrupts() - Read the device interrupts
776 * @dev: Reference to structure of type pch_udc_regs
777 * Retern The device interrupts
778 */
779 static inline u32 pch_udc_read_device_interrupts(struct pch_udc_dev *dev)
780 {
781 return pch_udc_readl(dev, UDC_DEVIRQSTS_ADDR);
782 }
783
784 /**
785 * pch_udc_write_device_interrupts() - Write device interrupts
786 * @dev: Reference to structure of type pch_udc_regs
787 * @val: The value to be written to interrupt register
788 */
789 static inline void pch_udc_write_device_interrupts(struct pch_udc_dev *dev,
790 u32 val)
791 {
792 pch_udc_writel(dev, val, UDC_DEVIRQSTS_ADDR);
793 }
794
795 /**
796 * pch_udc_read_ep_interrupts() - Read the endpoint interrupts
797 * @dev: Reference to structure of type pch_udc_regs
798 * Retern The endpoint interrupt
799 */
800 static inline u32 pch_udc_read_ep_interrupts(struct pch_udc_dev *dev)
801 {
802 return pch_udc_readl(dev, UDC_EPIRQSTS_ADDR);
803 }
804
805 /**
806 * pch_udc_write_ep_interrupts() - Clear endpoint interupts
807 * @dev: Reference to structure of type pch_udc_regs
808 * @val: The value to be written to interrupt register
809 */
810 static inline void pch_udc_write_ep_interrupts(struct pch_udc_dev *dev,
811 u32 val)
812 {
813 pch_udc_writel(dev, val, UDC_EPIRQSTS_ADDR);
814 }
815
816 /**
817 * pch_udc_read_device_status() - Read the device status
818 * @dev: Reference to structure of type pch_udc_regs
819 * Retern The device status
820 */
821 static inline u32 pch_udc_read_device_status(struct pch_udc_dev *dev)
822 {
823 return pch_udc_readl(dev, UDC_DEVSTS_ADDR);
824 }
825
826 /**
827 * pch_udc_read_ep_control() - Read the endpoint control
828 * @ep: Reference to structure of type pch_udc_ep_regs
829 * Retern The endpoint control register value
830 */
831 static inline u32 pch_udc_read_ep_control(struct pch_udc_ep *ep)
832 {
833 return pch_udc_ep_readl(ep, UDC_EPCTL_ADDR);
834 }
835
836 /**
837 * pch_udc_clear_ep_control() - Clear the endpoint control register
838 * @ep: Reference to structure of type pch_udc_ep_regs
839 * Retern The endpoint control register value
840 */
841 static inline void pch_udc_clear_ep_control(struct pch_udc_ep *ep)
842 {
843 return pch_udc_ep_writel(ep, 0, UDC_EPCTL_ADDR);
844 }
845
846 /**
847 * pch_udc_read_ep_status() - Read the endpoint status
848 * @ep: Reference to structure of type pch_udc_ep_regs
849 * Retern The endpoint status
850 */
851 static inline u32 pch_udc_read_ep_status(struct pch_udc_ep *ep)
852 {
853 return pch_udc_ep_readl(ep, UDC_EPSTS_ADDR);
854 }
855
856 /**
857 * pch_udc_clear_ep_status() - Clear the endpoint status
858 * @ep: Reference to structure of type pch_udc_ep_regs
859 * @stat: Endpoint status
860 */
861 static inline void pch_udc_clear_ep_status(struct pch_udc_ep *ep,
862 u32 stat)
863 {
864 return pch_udc_ep_writel(ep, stat, UDC_EPSTS_ADDR);
865 }
866
867 /**
868 * pch_udc_ep_set_nak() - Set the bit 7 (SNAK field)
869 * of the endpoint control register
870 * @ep: Reference to structure of type pch_udc_ep_regs
871 */
872 static inline void pch_udc_ep_set_nak(struct pch_udc_ep *ep)
873 {
874 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_SNAK);
875 }
876
877 /**
878 * pch_udc_ep_clear_nak() - Set the bit 8 (CNAK field)
879 * of the endpoint control register
880 * @ep: reference to structure of type pch_udc_ep_regs
881 */
882 static void pch_udc_ep_clear_nak(struct pch_udc_ep *ep)
883 {
884 unsigned int loopcnt = 0;
885 struct pch_udc_dev *dev = ep->dev;
886
887 if (!(pch_udc_ep_readl(ep, UDC_EPCTL_ADDR) & UDC_EPCTL_NAK))
888 return;
889 if (!ep->in) {
890 loopcnt = 10000;
891 while (!(pch_udc_read_ep_status(ep) & UDC_EPSTS_MRXFIFO_EMP) &&
892 --loopcnt)
893 udelay(5);
894 if (!loopcnt)
895 dev_err(&dev->pdev->dev, "%s: RxFIFO not Empty\n",
896 __func__);
897 }
898 loopcnt = 10000;
899 while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_NAK) && --loopcnt) {
900 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
901 udelay(5);
902 }
903 if (!loopcnt)
904 dev_err(&dev->pdev->dev, "%s: Clear NAK not set for ep%d%s\n",
905 __func__, ep->num, (ep->in ? "in" : "out"));
906 }
907
908 /**
909 * pch_udc_ep_fifo_flush() - Flush the endpoint fifo
910 * @ep: reference to structure of type pch_udc_ep_regs
911 * @dir: direction of endpoint
912 * 0: endpoint is OUT
913 * !0: endpoint is IN
914 */
915 static void pch_udc_ep_fifo_flush(struct pch_udc_ep *ep, int dir)
916 {
917 if (dir) { /* IN ep */
918 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
919 return;
920 }
921 }
922
923 /**
924 * pch_udc_ep_enable() - This api enables endpoint
925 * @regs: Reference to structure pch_udc_ep_regs
926 * @desc: endpoint descriptor
927 */
928 static void pch_udc_ep_enable(struct pch_udc_ep *ep,
929 struct pch_udc_cfg_data *cfg,
930 const struct usb_endpoint_descriptor *desc)
931 {
932 u32 val = 0;
933 u32 buff_size = 0;
934
935 pch_udc_ep_set_trfr_type(ep, desc->bmAttributes);
936 if (ep->in)
937 buff_size = UDC_EPIN_BUFF_SIZE;
938 else
939 buff_size = UDC_EPOUT_BUFF_SIZE;
940 pch_udc_ep_set_bufsz(ep, buff_size, ep->in);
941 pch_udc_ep_set_maxpkt(ep, usb_endpoint_maxp(desc));
942 pch_udc_ep_set_nak(ep);
943 pch_udc_ep_fifo_flush(ep, ep->in);
944 /* Configure the endpoint */
945 val = ep->num << UDC_CSR_NE_NUM_SHIFT | ep->in << UDC_CSR_NE_DIR_SHIFT |
946 ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) <<
947 UDC_CSR_NE_TYPE_SHIFT) |
948 (cfg->cur_cfg << UDC_CSR_NE_CFG_SHIFT) |
949 (cfg->cur_intf << UDC_CSR_NE_INTF_SHIFT) |
950 (cfg->cur_alt << UDC_CSR_NE_ALT_SHIFT) |
951 usb_endpoint_maxp(desc) << UDC_CSR_NE_MAX_PKT_SHIFT;
952
953 if (ep->in)
954 pch_udc_write_csr(ep->dev, val, UDC_EPIN_IDX(ep->num));
955 else
956 pch_udc_write_csr(ep->dev, val, UDC_EPOUT_IDX(ep->num));
957 }
958
959 /**
960 * pch_udc_ep_disable() - This api disables endpoint
961 * @regs: Reference to structure pch_udc_ep_regs
962 */
963 static void pch_udc_ep_disable(struct pch_udc_ep *ep)
964 {
965 if (ep->in) {
966 /* flush the fifo */
967 pch_udc_ep_writel(ep, UDC_EPCTL_F, UDC_EPCTL_ADDR);
968 /* set NAK */
969 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
970 pch_udc_ep_bit_set(ep, UDC_EPSTS_ADDR, UDC_EPSTS_IN);
971 } else {
972 /* set NAK */
973 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
974 }
975 /* reset desc pointer */
976 pch_udc_ep_writel(ep, 0, UDC_DESPTR_ADDR);
977 }
978
979 /**
980 * pch_udc_wait_ep_stall() - Wait EP stall.
981 * @dev: Reference to pch_udc_dev structure
982 */
983 static void pch_udc_wait_ep_stall(struct pch_udc_ep *ep)
984 {
985 unsigned int count = 10000;
986
987 /* Wait till idle */
988 while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_S) && --count)
989 udelay(5);
990 if (!count)
991 dev_err(&ep->dev->pdev->dev, "%s: wait error\n", __func__);
992 }
993
994 /**
995 * pch_udc_init() - This API initializes usb device controller
996 * @dev: Rreference to pch_udc_regs structure
997 */
998 static void pch_udc_init(struct pch_udc_dev *dev)
999 {
1000 if (NULL == dev) {
1001 pr_err("%s: Invalid address\n", __func__);
1002 return;
1003 }
1004 /* Soft Reset and Reset PHY */
1005 pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1006 pch_udc_writel(dev, UDC_SRST | UDC_PSRST, UDC_SRST_ADDR);
1007 mdelay(1);
1008 pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1009 pch_udc_writel(dev, 0x00, UDC_SRST_ADDR);
1010 mdelay(1);
1011 /* mask and clear all device interrupts */
1012 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1013 pch_udc_bit_set(dev, UDC_DEVIRQSTS_ADDR, UDC_DEVINT_MSK);
1014
1015 /* mask and clear all ep interrupts */
1016 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1017 pch_udc_bit_set(dev, UDC_EPIRQSTS_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1018
1019 /* enable dynamic CSR programmingi, self powered and device speed */
1020 if (speed_fs)
1021 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1022 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_FS);
1023 else /* defaul high speed */
1024 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1025 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_HS);
1026 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR,
1027 (PCH_UDC_THLEN << UDC_DEVCTL_THLEN_SHIFT) |
1028 (PCH_UDC_BRLEN << UDC_DEVCTL_BRLEN_SHIFT) |
1029 UDC_DEVCTL_MODE | UDC_DEVCTL_BREN |
1030 UDC_DEVCTL_THE);
1031 }
1032
1033 /**
1034 * pch_udc_exit() - This API exit usb device controller
1035 * @dev: Reference to pch_udc_regs structure
1036 */
1037 static void pch_udc_exit(struct pch_udc_dev *dev)
1038 {
1039 /* mask all device interrupts */
1040 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1041 /* mask all ep interrupts */
1042 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1043 /* put device in disconnected state */
1044 pch_udc_set_disconnect(dev);
1045 }
1046
1047 /**
1048 * pch_udc_pcd_get_frame() - This API is invoked to get the current frame number
1049 * @gadget: Reference to the gadget driver
1050 *
1051 * Return codes:
1052 * 0: Success
1053 * -EINVAL: If the gadget passed is NULL
1054 */
1055 static int pch_udc_pcd_get_frame(struct usb_gadget *gadget)
1056 {
1057 struct pch_udc_dev *dev;
1058
1059 if (!gadget)
1060 return -EINVAL;
1061 dev = container_of(gadget, struct pch_udc_dev, gadget);
1062 return pch_udc_get_frame(dev);
1063 }
1064
1065 /**
1066 * pch_udc_pcd_wakeup() - This API is invoked to initiate a remote wakeup
1067 * @gadget: Reference to the gadget driver
1068 *
1069 * Return codes:
1070 * 0: Success
1071 * -EINVAL: If the gadget passed is NULL
1072 */
1073 static int pch_udc_pcd_wakeup(struct usb_gadget *gadget)
1074 {
1075 struct pch_udc_dev *dev;
1076 unsigned long flags;
1077
1078 if (!gadget)
1079 return -EINVAL;
1080 dev = container_of(gadget, struct pch_udc_dev, gadget);
1081 spin_lock_irqsave(&dev->lock, flags);
1082 pch_udc_rmt_wakeup(dev);
1083 spin_unlock_irqrestore(&dev->lock, flags);
1084 return 0;
1085 }
1086
1087 /**
1088 * pch_udc_pcd_selfpowered() - This API is invoked to specify whether the device
1089 * is self powered or not
1090 * @gadget: Reference to the gadget driver
1091 * @value: Specifies self powered or not
1092 *
1093 * Return codes:
1094 * 0: Success
1095 * -EINVAL: If the gadget passed is NULL
1096 */
1097 static int pch_udc_pcd_selfpowered(struct usb_gadget *gadget, int value)
1098 {
1099 struct pch_udc_dev *dev;
1100
1101 if (!gadget)
1102 return -EINVAL;
1103 dev = container_of(gadget, struct pch_udc_dev, gadget);
1104 if (value)
1105 pch_udc_set_selfpowered(dev);
1106 else
1107 pch_udc_clear_selfpowered(dev);
1108 return 0;
1109 }
1110
1111 /**
1112 * pch_udc_pcd_pullup() - This API is invoked to make the device
1113 * visible/invisible to the host
1114 * @gadget: Reference to the gadget driver
1115 * @is_on: Specifies whether the pull up is made active or inactive
1116 *
1117 * Return codes:
1118 * 0: Success
1119 * -EINVAL: If the gadget passed is NULL
1120 */
1121 static int pch_udc_pcd_pullup(struct usb_gadget *gadget, int is_on)
1122 {
1123 struct pch_udc_dev *dev;
1124
1125 if (!gadget)
1126 return -EINVAL;
1127 dev = container_of(gadget, struct pch_udc_dev, gadget);
1128 pch_udc_vbus_session(dev, is_on);
1129 return 0;
1130 }
1131
1132 /**
1133 * pch_udc_pcd_vbus_session() - This API is used by a driver for an external
1134 * transceiver (or GPIO) that
1135 * detects a VBUS power session starting/ending
1136 * @gadget: Reference to the gadget driver
1137 * @is_active: specifies whether the session is starting or ending
1138 *
1139 * Return codes:
1140 * 0: Success
1141 * -EINVAL: If the gadget passed is NULL
1142 */
1143 static int pch_udc_pcd_vbus_session(struct usb_gadget *gadget, int is_active)
1144 {
1145 struct pch_udc_dev *dev;
1146
1147 if (!gadget)
1148 return -EINVAL;
1149 dev = container_of(gadget, struct pch_udc_dev, gadget);
1150 pch_udc_vbus_session(dev, is_active);
1151 return 0;
1152 }
1153
1154 /**
1155 * pch_udc_pcd_vbus_draw() - This API is used by gadget drivers during
1156 * SET_CONFIGURATION calls to
1157 * specify how much power the device can consume
1158 * @gadget: Reference to the gadget driver
1159 * @mA: specifies the current limit in 2mA unit
1160 *
1161 * Return codes:
1162 * -EINVAL: If the gadget passed is NULL
1163 * -EOPNOTSUPP:
1164 */
1165 static int pch_udc_pcd_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
1166 {
1167 return -EOPNOTSUPP;
1168 }
1169
1170 static int pch_udc_start(struct usb_gadget_driver *driver,
1171 int (*bind)(struct usb_gadget *));
1172 static int pch_udc_stop(struct usb_gadget_driver *driver);
1173 static const struct usb_gadget_ops pch_udc_ops = {
1174 .get_frame = pch_udc_pcd_get_frame,
1175 .wakeup = pch_udc_pcd_wakeup,
1176 .set_selfpowered = pch_udc_pcd_selfpowered,
1177 .pullup = pch_udc_pcd_pullup,
1178 .vbus_session = pch_udc_pcd_vbus_session,
1179 .vbus_draw = pch_udc_pcd_vbus_draw,
1180 .start = pch_udc_start,
1181 .stop = pch_udc_stop,
1182 };
1183
1184 /**
1185 * complete_req() - This API is invoked from the driver when processing
1186 * of a request is complete
1187 * @ep: Reference to the endpoint structure
1188 * @req: Reference to the request structure
1189 * @status: Indicates the success/failure of completion
1190 */
1191 static void complete_req(struct pch_udc_ep *ep, struct pch_udc_request *req,
1192 int status)
1193 {
1194 struct pch_udc_dev *dev;
1195 unsigned halted = ep->halted;
1196
1197 list_del_init(&req->queue);
1198
1199 /* set new status if pending */
1200 if (req->req.status == -EINPROGRESS)
1201 req->req.status = status;
1202 else
1203 status = req->req.status;
1204
1205 dev = ep->dev;
1206 if (req->dma_mapped) {
1207 if (req->dma == DMA_ADDR_INVALID) {
1208 if (ep->in)
1209 dma_unmap_single(&dev->pdev->dev, req->req.dma,
1210 req->req.length,
1211 DMA_TO_DEVICE);
1212 else
1213 dma_unmap_single(&dev->pdev->dev, req->req.dma,
1214 req->req.length,
1215 DMA_FROM_DEVICE);
1216 req->req.dma = DMA_ADDR_INVALID;
1217 } else {
1218 if (ep->in)
1219 dma_unmap_single(&dev->pdev->dev, req->dma,
1220 req->req.length,
1221 DMA_TO_DEVICE);
1222 else {
1223 dma_unmap_single(&dev->pdev->dev, req->dma,
1224 req->req.length,
1225 DMA_FROM_DEVICE);
1226 memcpy(req->req.buf, req->buf, req->req.length);
1227 }
1228 kfree(req->buf);
1229 req->dma = DMA_ADDR_INVALID;
1230 }
1231 req->dma_mapped = 0;
1232 }
1233 ep->halted = 1;
1234 spin_unlock(&dev->lock);
1235 if (!ep->in)
1236 pch_udc_ep_clear_rrdy(ep);
1237 req->req.complete(&ep->ep, &req->req);
1238 spin_lock(&dev->lock);
1239 ep->halted = halted;
1240 }
1241
1242 /**
1243 * empty_req_queue() - This API empties the request queue of an endpoint
1244 * @ep: Reference to the endpoint structure
1245 */
1246 static void empty_req_queue(struct pch_udc_ep *ep)
1247 {
1248 struct pch_udc_request *req;
1249
1250 ep->halted = 1;
1251 while (!list_empty(&ep->queue)) {
1252 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1253 complete_req(ep, req, -ESHUTDOWN); /* Remove from list */
1254 }
1255 }
1256
1257 /**
1258 * pch_udc_free_dma_chain() - This function frees the DMA chain created
1259 * for the request
1260 * @dev Reference to the driver structure
1261 * @req Reference to the request to be freed
1262 *
1263 * Return codes:
1264 * 0: Success
1265 */
1266 static void pch_udc_free_dma_chain(struct pch_udc_dev *dev,
1267 struct pch_udc_request *req)
1268 {
1269 struct pch_udc_data_dma_desc *td = req->td_data;
1270 unsigned i = req->chain_len;
1271
1272 dma_addr_t addr2;
1273 dma_addr_t addr = (dma_addr_t)td->next;
1274 td->next = 0x00;
1275 for (; i > 1; --i) {
1276 /* do not free first desc., will be done by free for request */
1277 td = phys_to_virt(addr);
1278 addr2 = (dma_addr_t)td->next;
1279 pci_pool_free(dev->data_requests, td, addr);
1280 td->next = 0x00;
1281 addr = addr2;
1282 }
1283 req->chain_len = 1;
1284 }
1285
1286 /**
1287 * pch_udc_create_dma_chain() - This function creates or reinitializes
1288 * a DMA chain
1289 * @ep: Reference to the endpoint structure
1290 * @req: Reference to the request
1291 * @buf_len: The buffer length
1292 * @gfp_flags: Flags to be used while mapping the data buffer
1293 *
1294 * Return codes:
1295 * 0: success,
1296 * -ENOMEM: pci_pool_alloc invocation fails
1297 */
1298 static int pch_udc_create_dma_chain(struct pch_udc_ep *ep,
1299 struct pch_udc_request *req,
1300 unsigned long buf_len,
1301 gfp_t gfp_flags)
1302 {
1303 struct pch_udc_data_dma_desc *td = req->td_data, *last;
1304 unsigned long bytes = req->req.length, i = 0;
1305 dma_addr_t dma_addr;
1306 unsigned len = 1;
1307
1308 if (req->chain_len > 1)
1309 pch_udc_free_dma_chain(ep->dev, req);
1310
1311 if (req->dma == DMA_ADDR_INVALID)
1312 td->dataptr = req->req.dma;
1313 else
1314 td->dataptr = req->dma;
1315
1316 td->status = PCH_UDC_BS_HST_BSY;
1317 for (; ; bytes -= buf_len, ++len) {
1318 td->status = PCH_UDC_BS_HST_BSY | min(buf_len, bytes);
1319 if (bytes <= buf_len)
1320 break;
1321 last = td;
1322 td = pci_pool_alloc(ep->dev->data_requests, gfp_flags,
1323 &dma_addr);
1324 if (!td)
1325 goto nomem;
1326 i += buf_len;
1327 td->dataptr = req->td_data->dataptr + i;
1328 last->next = dma_addr;
1329 }
1330
1331 req->td_data_last = td;
1332 td->status |= PCH_UDC_DMA_LAST;
1333 td->next = req->td_data_phys;
1334 req->chain_len = len;
1335 return 0;
1336
1337 nomem:
1338 if (len > 1) {
1339 req->chain_len = len;
1340 pch_udc_free_dma_chain(ep->dev, req);
1341 }
1342 req->chain_len = 1;
1343 return -ENOMEM;
1344 }
1345
1346 /**
1347 * prepare_dma() - This function creates and initializes the DMA chain
1348 * for the request
1349 * @ep: Reference to the endpoint structure
1350 * @req: Reference to the request
1351 * @gfp: Flag to be used while mapping the data buffer
1352 *
1353 * Return codes:
1354 * 0: Success
1355 * Other 0: linux error number on failure
1356 */
1357 static int prepare_dma(struct pch_udc_ep *ep, struct pch_udc_request *req,
1358 gfp_t gfp)
1359 {
1360 int retval;
1361
1362 /* Allocate and create a DMA chain */
1363 retval = pch_udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
1364 if (retval) {
1365 pr_err("%s: could not create DMA chain:%d\n", __func__, retval);
1366 return retval;
1367 }
1368 if (ep->in)
1369 req->td_data->status = (req->td_data->status &
1370 ~PCH_UDC_BUFF_STS) | PCH_UDC_BS_HST_RDY;
1371 return 0;
1372 }
1373
1374 /**
1375 * process_zlp() - This function process zero length packets
1376 * from the gadget driver
1377 * @ep: Reference to the endpoint structure
1378 * @req: Reference to the request
1379 */
1380 static void process_zlp(struct pch_udc_ep *ep, struct pch_udc_request *req)
1381 {
1382 struct pch_udc_dev *dev = ep->dev;
1383
1384 /* IN zlp's are handled by hardware */
1385 complete_req(ep, req, 0);
1386
1387 /* if set_config or set_intf is waiting for ack by zlp
1388 * then set CSR_DONE
1389 */
1390 if (dev->set_cfg_not_acked) {
1391 pch_udc_set_csr_done(dev);
1392 dev->set_cfg_not_acked = 0;
1393 }
1394 /* setup command is ACK'ed now by zlp */
1395 if (!dev->stall && dev->waiting_zlp_ack) {
1396 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
1397 dev->waiting_zlp_ack = 0;
1398 }
1399 }
1400
1401 /**
1402 * pch_udc_start_rxrequest() - This function starts the receive requirement.
1403 * @ep: Reference to the endpoint structure
1404 * @req: Reference to the request structure
1405 */
1406 static void pch_udc_start_rxrequest(struct pch_udc_ep *ep,
1407 struct pch_udc_request *req)
1408 {
1409 struct pch_udc_data_dma_desc *td_data;
1410
1411 pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
1412 td_data = req->td_data;
1413 /* Set the status bits for all descriptors */
1414 while (1) {
1415 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
1416 PCH_UDC_BS_HST_RDY;
1417 if ((td_data->status & PCH_UDC_DMA_LAST) == PCH_UDC_DMA_LAST)
1418 break;
1419 td_data = phys_to_virt(td_data->next);
1420 }
1421 /* Write the descriptor pointer */
1422 pch_udc_ep_set_ddptr(ep, req->td_data_phys);
1423 req->dma_going = 1;
1424 pch_udc_enable_ep_interrupts(ep->dev, UDC_EPINT_OUT_EP0 << ep->num);
1425 pch_udc_set_dma(ep->dev, DMA_DIR_RX);
1426 pch_udc_ep_clear_nak(ep);
1427 pch_udc_ep_set_rrdy(ep);
1428 }
1429
1430 /**
1431 * pch_udc_pcd_ep_enable() - This API enables the endpoint. It is called
1432 * from gadget driver
1433 * @usbep: Reference to the USB endpoint structure
1434 * @desc: Reference to the USB endpoint descriptor structure
1435 *
1436 * Return codes:
1437 * 0: Success
1438 * -EINVAL:
1439 * -ESHUTDOWN:
1440 */
1441 static int pch_udc_pcd_ep_enable(struct usb_ep *usbep,
1442 const struct usb_endpoint_descriptor *desc)
1443 {
1444 struct pch_udc_ep *ep;
1445 struct pch_udc_dev *dev;
1446 unsigned long iflags;
1447
1448 if (!usbep || (usbep->name == ep0_string) || !desc ||
1449 (desc->bDescriptorType != USB_DT_ENDPOINT) || !desc->wMaxPacketSize)
1450 return -EINVAL;
1451
1452 ep = container_of(usbep, struct pch_udc_ep, ep);
1453 dev = ep->dev;
1454 if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1455 return -ESHUTDOWN;
1456 spin_lock_irqsave(&dev->lock, iflags);
1457 ep->desc = desc;
1458 ep->halted = 0;
1459 pch_udc_ep_enable(ep, &ep->dev->cfg_data, desc);
1460 ep->ep.maxpacket = usb_endpoint_maxp(desc);
1461 pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1462 spin_unlock_irqrestore(&dev->lock, iflags);
1463 return 0;
1464 }
1465
1466 /**
1467 * pch_udc_pcd_ep_disable() - This API disables endpoint and is called
1468 * from gadget driver
1469 * @usbep Reference to the USB endpoint structure
1470 *
1471 * Return codes:
1472 * 0: Success
1473 * -EINVAL:
1474 */
1475 static int pch_udc_pcd_ep_disable(struct usb_ep *usbep)
1476 {
1477 struct pch_udc_ep *ep;
1478 struct pch_udc_dev *dev;
1479 unsigned long iflags;
1480
1481 if (!usbep)
1482 return -EINVAL;
1483
1484 ep = container_of(usbep, struct pch_udc_ep, ep);
1485 dev = ep->dev;
1486 if ((usbep->name == ep0_string) || !ep->desc)
1487 return -EINVAL;
1488
1489 spin_lock_irqsave(&ep->dev->lock, iflags);
1490 empty_req_queue(ep);
1491 ep->halted = 1;
1492 pch_udc_ep_disable(ep);
1493 pch_udc_disable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1494 ep->desc = NULL;
1495 INIT_LIST_HEAD(&ep->queue);
1496 spin_unlock_irqrestore(&ep->dev->lock, iflags);
1497 return 0;
1498 }
1499
1500 /**
1501 * pch_udc_alloc_request() - This function allocates request structure.
1502 * It is called by gadget driver
1503 * @usbep: Reference to the USB endpoint structure
1504 * @gfp: Flag to be used while allocating memory
1505 *
1506 * Return codes:
1507 * NULL: Failure
1508 * Allocated address: Success
1509 */
1510 static struct usb_request *pch_udc_alloc_request(struct usb_ep *usbep,
1511 gfp_t gfp)
1512 {
1513 struct pch_udc_request *req;
1514 struct pch_udc_ep *ep;
1515 struct pch_udc_data_dma_desc *dma_desc;
1516 struct pch_udc_dev *dev;
1517
1518 if (!usbep)
1519 return NULL;
1520 ep = container_of(usbep, struct pch_udc_ep, ep);
1521 dev = ep->dev;
1522 req = kzalloc(sizeof *req, gfp);
1523 if (!req)
1524 return NULL;
1525 req->req.dma = DMA_ADDR_INVALID;
1526 req->dma = DMA_ADDR_INVALID;
1527 INIT_LIST_HEAD(&req->queue);
1528 if (!ep->dev->dma_addr)
1529 return &req->req;
1530 /* ep0 in requests are allocated from data pool here */
1531 dma_desc = pci_pool_alloc(ep->dev->data_requests, gfp,
1532 &req->td_data_phys);
1533 if (NULL == dma_desc) {
1534 kfree(req);
1535 return NULL;
1536 }
1537 /* prevent from using desc. - set HOST BUSY */
1538 dma_desc->status |= PCH_UDC_BS_HST_BSY;
1539 dma_desc->dataptr = __constant_cpu_to_le32(DMA_ADDR_INVALID);
1540 req->td_data = dma_desc;
1541 req->td_data_last = dma_desc;
1542 req->chain_len = 1;
1543 return &req->req;
1544 }
1545
1546 /**
1547 * pch_udc_free_request() - This function frees request structure.
1548 * It is called by gadget driver
1549 * @usbep: Reference to the USB endpoint structure
1550 * @usbreq: Reference to the USB request
1551 */
1552 static void pch_udc_free_request(struct usb_ep *usbep,
1553 struct usb_request *usbreq)
1554 {
1555 struct pch_udc_ep *ep;
1556 struct pch_udc_request *req;
1557 struct pch_udc_dev *dev;
1558
1559 if (!usbep || !usbreq)
1560 return;
1561 ep = container_of(usbep, struct pch_udc_ep, ep);
1562 req = container_of(usbreq, struct pch_udc_request, req);
1563 dev = ep->dev;
1564 if (!list_empty(&req->queue))
1565 dev_err(&dev->pdev->dev, "%s: %s req=0x%p queue not empty\n",
1566 __func__, usbep->name, req);
1567 if (req->td_data != NULL) {
1568 if (req->chain_len > 1)
1569 pch_udc_free_dma_chain(ep->dev, req);
1570 pci_pool_free(ep->dev->data_requests, req->td_data,
1571 req->td_data_phys);
1572 }
1573 kfree(req);
1574 }
1575
1576 /**
1577 * pch_udc_pcd_queue() - This function queues a request packet. It is called
1578 * by gadget driver
1579 * @usbep: Reference to the USB endpoint structure
1580 * @usbreq: Reference to the USB request
1581 * @gfp: Flag to be used while mapping the data buffer
1582 *
1583 * Return codes:
1584 * 0: Success
1585 * linux error number: Failure
1586 */
1587 static int pch_udc_pcd_queue(struct usb_ep *usbep, struct usb_request *usbreq,
1588 gfp_t gfp)
1589 {
1590 int retval = 0;
1591 struct pch_udc_ep *ep;
1592 struct pch_udc_dev *dev;
1593 struct pch_udc_request *req;
1594 unsigned long iflags;
1595
1596 if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf)
1597 return -EINVAL;
1598 ep = container_of(usbep, struct pch_udc_ep, ep);
1599 dev = ep->dev;
1600 if (!ep->desc && ep->num)
1601 return -EINVAL;
1602 req = container_of(usbreq, struct pch_udc_request, req);
1603 if (!list_empty(&req->queue))
1604 return -EINVAL;
1605 if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1606 return -ESHUTDOWN;
1607 spin_lock_irqsave(&dev->lock, iflags);
1608 /* map the buffer for dma */
1609 if (usbreq->length &&
1610 ((usbreq->dma == DMA_ADDR_INVALID) || !usbreq->dma)) {
1611 if (!((unsigned long)(usbreq->buf) & 0x03)) {
1612 if (ep->in)
1613 usbreq->dma = dma_map_single(&dev->pdev->dev,
1614 usbreq->buf,
1615 usbreq->length,
1616 DMA_TO_DEVICE);
1617 else
1618 usbreq->dma = dma_map_single(&dev->pdev->dev,
1619 usbreq->buf,
1620 usbreq->length,
1621 DMA_FROM_DEVICE);
1622 } else {
1623 req->buf = kzalloc(usbreq->length, GFP_ATOMIC);
1624 if (!req->buf) {
1625 retval = -ENOMEM;
1626 goto probe_end;
1627 }
1628 if (ep->in) {
1629 memcpy(req->buf, usbreq->buf, usbreq->length);
1630 req->dma = dma_map_single(&dev->pdev->dev,
1631 req->buf,
1632 usbreq->length,
1633 DMA_TO_DEVICE);
1634 } else
1635 req->dma = dma_map_single(&dev->pdev->dev,
1636 req->buf,
1637 usbreq->length,
1638 DMA_FROM_DEVICE);
1639 }
1640 req->dma_mapped = 1;
1641 }
1642 if (usbreq->length > 0) {
1643 retval = prepare_dma(ep, req, GFP_ATOMIC);
1644 if (retval)
1645 goto probe_end;
1646 }
1647 usbreq->actual = 0;
1648 usbreq->status = -EINPROGRESS;
1649 req->dma_done = 0;
1650 if (list_empty(&ep->queue) && !ep->halted) {
1651 /* no pending transfer, so start this req */
1652 if (!usbreq->length) {
1653 process_zlp(ep, req);
1654 retval = 0;
1655 goto probe_end;
1656 }
1657 if (!ep->in) {
1658 pch_udc_start_rxrequest(ep, req);
1659 } else {
1660 /*
1661 * For IN trfr the descriptors will be programmed and
1662 * P bit will be set when
1663 * we get an IN token
1664 */
1665 pch_udc_wait_ep_stall(ep);
1666 pch_udc_ep_clear_nak(ep);
1667 pch_udc_enable_ep_interrupts(ep->dev, (1 << ep->num));
1668 }
1669 }
1670 /* Now add this request to the ep's pending requests */
1671 if (req != NULL)
1672 list_add_tail(&req->queue, &ep->queue);
1673
1674 probe_end:
1675 spin_unlock_irqrestore(&dev->lock, iflags);
1676 return retval;
1677 }
1678
1679 /**
1680 * pch_udc_pcd_dequeue() - This function de-queues a request packet.
1681 * It is called by gadget driver
1682 * @usbep: Reference to the USB endpoint structure
1683 * @usbreq: Reference to the USB request
1684 *
1685 * Return codes:
1686 * 0: Success
1687 * linux error number: Failure
1688 */
1689 static int pch_udc_pcd_dequeue(struct usb_ep *usbep,
1690 struct usb_request *usbreq)
1691 {
1692 struct pch_udc_ep *ep;
1693 struct pch_udc_request *req;
1694 struct pch_udc_dev *dev;
1695 unsigned long flags;
1696 int ret = -EINVAL;
1697
1698 ep = container_of(usbep, struct pch_udc_ep, ep);
1699 dev = ep->dev;
1700 if (!usbep || !usbreq || (!ep->desc && ep->num))
1701 return ret;
1702 req = container_of(usbreq, struct pch_udc_request, req);
1703 spin_lock_irqsave(&ep->dev->lock, flags);
1704 /* make sure it's still queued on this endpoint */
1705 list_for_each_entry(req, &ep->queue, queue) {
1706 if (&req->req == usbreq) {
1707 pch_udc_ep_set_nak(ep);
1708 if (!list_empty(&req->queue))
1709 complete_req(ep, req, -ECONNRESET);
1710 ret = 0;
1711 break;
1712 }
1713 }
1714 spin_unlock_irqrestore(&ep->dev->lock, flags);
1715 return ret;
1716 }
1717
1718 /**
1719 * pch_udc_pcd_set_halt() - This function Sets or clear the endpoint halt
1720 * feature
1721 * @usbep: Reference to the USB endpoint structure
1722 * @halt: Specifies whether to set or clear the feature
1723 *
1724 * Return codes:
1725 * 0: Success
1726 * linux error number: Failure
1727 */
1728 static int pch_udc_pcd_set_halt(struct usb_ep *usbep, int halt)
1729 {
1730 struct pch_udc_ep *ep;
1731 struct pch_udc_dev *dev;
1732 unsigned long iflags;
1733 int ret;
1734
1735 if (!usbep)
1736 return -EINVAL;
1737 ep = container_of(usbep, struct pch_udc_ep, ep);
1738 dev = ep->dev;
1739 if (!ep->desc && !ep->num)
1740 return -EINVAL;
1741 if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
1742 return -ESHUTDOWN;
1743 spin_lock_irqsave(&udc_stall_spinlock, iflags);
1744 if (list_empty(&ep->queue)) {
1745 if (halt) {
1746 if (ep->num == PCH_UDC_EP0)
1747 ep->dev->stall = 1;
1748 pch_udc_ep_set_stall(ep);
1749 pch_udc_enable_ep_interrupts(ep->dev,
1750 PCH_UDC_EPINT(ep->in,
1751 ep->num));
1752 } else {
1753 pch_udc_ep_clear_stall(ep);
1754 }
1755 ret = 0;
1756 } else {
1757 ret = -EAGAIN;
1758 }
1759 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1760 return ret;
1761 }
1762
1763 /**
1764 * pch_udc_pcd_set_wedge() - This function Sets or clear the endpoint
1765 * halt feature
1766 * @usbep: Reference to the USB endpoint structure
1767 * @halt: Specifies whether to set or clear the feature
1768 *
1769 * Return codes:
1770 * 0: Success
1771 * linux error number: Failure
1772 */
1773 static int pch_udc_pcd_set_wedge(struct usb_ep *usbep)
1774 {
1775 struct pch_udc_ep *ep;
1776 struct pch_udc_dev *dev;
1777 unsigned long iflags;
1778 int ret;
1779
1780 if (!usbep)
1781 return -EINVAL;
1782 ep = container_of(usbep, struct pch_udc_ep, ep);
1783 dev = ep->dev;
1784 if (!ep->desc && !ep->num)
1785 return -EINVAL;
1786 if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
1787 return -ESHUTDOWN;
1788 spin_lock_irqsave(&udc_stall_spinlock, iflags);
1789 if (!list_empty(&ep->queue)) {
1790 ret = -EAGAIN;
1791 } else {
1792 if (ep->num == PCH_UDC_EP0)
1793 ep->dev->stall = 1;
1794 pch_udc_ep_set_stall(ep);
1795 pch_udc_enable_ep_interrupts(ep->dev,
1796 PCH_UDC_EPINT(ep->in, ep->num));
1797 ep->dev->prot_stall = 1;
1798 ret = 0;
1799 }
1800 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1801 return ret;
1802 }
1803
1804 /**
1805 * pch_udc_pcd_fifo_flush() - This function Flush the FIFO of specified endpoint
1806 * @usbep: Reference to the USB endpoint structure
1807 */
1808 static void pch_udc_pcd_fifo_flush(struct usb_ep *usbep)
1809 {
1810 struct pch_udc_ep *ep;
1811
1812 if (!usbep)
1813 return;
1814
1815 ep = container_of(usbep, struct pch_udc_ep, ep);
1816 if (ep->desc || !ep->num)
1817 pch_udc_ep_fifo_flush(ep, ep->in);
1818 }
1819
1820 static const struct usb_ep_ops pch_udc_ep_ops = {
1821 .enable = pch_udc_pcd_ep_enable,
1822 .disable = pch_udc_pcd_ep_disable,
1823 .alloc_request = pch_udc_alloc_request,
1824 .free_request = pch_udc_free_request,
1825 .queue = pch_udc_pcd_queue,
1826 .dequeue = pch_udc_pcd_dequeue,
1827 .set_halt = pch_udc_pcd_set_halt,
1828 .set_wedge = pch_udc_pcd_set_wedge,
1829 .fifo_status = NULL,
1830 .fifo_flush = pch_udc_pcd_fifo_flush,
1831 };
1832
1833 /**
1834 * pch_udc_init_setup_buff() - This function initializes the SETUP buffer
1835 * @td_stp: Reference to the SETP buffer structure
1836 */
1837 static void pch_udc_init_setup_buff(struct pch_udc_stp_dma_desc *td_stp)
1838 {
1839 static u32 pky_marker;
1840
1841 if (!td_stp)
1842 return;
1843 td_stp->reserved = ++pky_marker;
1844 memset(&td_stp->request, 0xFF, sizeof td_stp->request);
1845 td_stp->status = PCH_UDC_BS_HST_RDY;
1846 }
1847
1848 /**
1849 * pch_udc_start_next_txrequest() - This function starts
1850 * the next transmission requirement
1851 * @ep: Reference to the endpoint structure
1852 */
1853 static void pch_udc_start_next_txrequest(struct pch_udc_ep *ep)
1854 {
1855 struct pch_udc_request *req;
1856 struct pch_udc_data_dma_desc *td_data;
1857
1858 if (pch_udc_read_ep_control(ep) & UDC_EPCTL_P)
1859 return;
1860
1861 if (list_empty(&ep->queue))
1862 return;
1863
1864 /* next request */
1865 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1866 if (req->dma_going)
1867 return;
1868 if (!req->td_data)
1869 return;
1870 pch_udc_wait_ep_stall(ep);
1871 req->dma_going = 1;
1872 pch_udc_ep_set_ddptr(ep, 0);
1873 td_data = req->td_data;
1874 while (1) {
1875 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
1876 PCH_UDC_BS_HST_RDY;
1877 if ((td_data->status & PCH_UDC_DMA_LAST) == PCH_UDC_DMA_LAST)
1878 break;
1879 td_data = phys_to_virt(td_data->next);
1880 }
1881 pch_udc_ep_set_ddptr(ep, req->td_data_phys);
1882 pch_udc_set_dma(ep->dev, DMA_DIR_TX);
1883 pch_udc_ep_set_pd(ep);
1884 pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1885 pch_udc_ep_clear_nak(ep);
1886 }
1887
1888 /**
1889 * pch_udc_complete_transfer() - This function completes a transfer
1890 * @ep: Reference to the endpoint structure
1891 */
1892 static void pch_udc_complete_transfer(struct pch_udc_ep *ep)
1893 {
1894 struct pch_udc_request *req;
1895 struct pch_udc_dev *dev = ep->dev;
1896
1897 if (list_empty(&ep->queue))
1898 return;
1899 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1900 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
1901 PCH_UDC_BS_DMA_DONE)
1902 return;
1903 if ((req->td_data_last->status & PCH_UDC_RXTX_STS) !=
1904 PCH_UDC_RTS_SUCC) {
1905 dev_err(&dev->pdev->dev, "Invalid RXTX status (0x%08x) "
1906 "epstatus=0x%08x\n",
1907 (req->td_data_last->status & PCH_UDC_RXTX_STS),
1908 (int)(ep->epsts));
1909 return;
1910 }
1911
1912 req->req.actual = req->req.length;
1913 req->td_data_last->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
1914 req->td_data->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
1915 complete_req(ep, req, 0);
1916 req->dma_going = 0;
1917 if (!list_empty(&ep->queue)) {
1918 pch_udc_wait_ep_stall(ep);
1919 pch_udc_ep_clear_nak(ep);
1920 pch_udc_enable_ep_interrupts(ep->dev,
1921 PCH_UDC_EPINT(ep->in, ep->num));
1922 } else {
1923 pch_udc_disable_ep_interrupts(ep->dev,
1924 PCH_UDC_EPINT(ep->in, ep->num));
1925 }
1926 }
1927
1928 /**
1929 * pch_udc_complete_receiver() - This function completes a receiver
1930 * @ep: Reference to the endpoint structure
1931 */
1932 static void pch_udc_complete_receiver(struct pch_udc_ep *ep)
1933 {
1934 struct pch_udc_request *req;
1935 struct pch_udc_dev *dev = ep->dev;
1936 unsigned int count;
1937 struct pch_udc_data_dma_desc *td;
1938 dma_addr_t addr;
1939
1940 if (list_empty(&ep->queue))
1941 return;
1942 /* next request */
1943 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1944 pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
1945 pch_udc_ep_set_ddptr(ep, 0);
1946 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) ==
1947 PCH_UDC_BS_DMA_DONE)
1948 td = req->td_data_last;
1949 else
1950 td = req->td_data;
1951
1952 while (1) {
1953 if ((td->status & PCH_UDC_RXTX_STS) != PCH_UDC_RTS_SUCC) {
1954 dev_err(&dev->pdev->dev, "Invalid RXTX status=0x%08x "
1955 "epstatus=0x%08x\n",
1956 (req->td_data->status & PCH_UDC_RXTX_STS),
1957 (int)(ep->epsts));
1958 return;
1959 }
1960 if ((td->status & PCH_UDC_BUFF_STS) == PCH_UDC_BS_DMA_DONE)
1961 if (td->status | PCH_UDC_DMA_LAST) {
1962 count = td->status & PCH_UDC_RXTX_BYTES;
1963 break;
1964 }
1965 if (td == req->td_data_last) {
1966 dev_err(&dev->pdev->dev, "Not complete RX descriptor");
1967 return;
1968 }
1969 addr = (dma_addr_t)td->next;
1970 td = phys_to_virt(addr);
1971 }
1972 /* on 64k packets the RXBYTES field is zero */
1973 if (!count && (req->req.length == UDC_DMA_MAXPACKET))
1974 count = UDC_DMA_MAXPACKET;
1975 req->td_data->status |= PCH_UDC_DMA_LAST;
1976 td->status |= PCH_UDC_BS_HST_BSY;
1977
1978 req->dma_going = 0;
1979 req->req.actual = count;
1980 complete_req(ep, req, 0);
1981 /* If there is a new/failed requests try that now */
1982 if (!list_empty(&ep->queue)) {
1983 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1984 pch_udc_start_rxrequest(ep, req);
1985 }
1986 }
1987
1988 /**
1989 * pch_udc_svc_data_in() - This function process endpoint interrupts
1990 * for IN endpoints
1991 * @dev: Reference to the device structure
1992 * @ep_num: Endpoint that generated the interrupt
1993 */
1994 static void pch_udc_svc_data_in(struct pch_udc_dev *dev, int ep_num)
1995 {
1996 u32 epsts;
1997 struct pch_udc_ep *ep;
1998
1999 ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2000 epsts = ep->epsts;
2001 ep->epsts = 0;
2002
2003 if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA | UDC_EPSTS_HE |
2004 UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
2005 UDC_EPSTS_RSS | UDC_EPSTS_XFERDONE)))
2006 return;
2007 if ((epsts & UDC_EPSTS_BNA))
2008 return;
2009 if (epsts & UDC_EPSTS_HE)
2010 return;
2011 if (epsts & UDC_EPSTS_RSS) {
2012 pch_udc_ep_set_stall(ep);
2013 pch_udc_enable_ep_interrupts(ep->dev,
2014 PCH_UDC_EPINT(ep->in, ep->num));
2015 }
2016 if (epsts & UDC_EPSTS_RCS) {
2017 if (!dev->prot_stall) {
2018 pch_udc_ep_clear_stall(ep);
2019 } else {
2020 pch_udc_ep_set_stall(ep);
2021 pch_udc_enable_ep_interrupts(ep->dev,
2022 PCH_UDC_EPINT(ep->in, ep->num));
2023 }
2024 }
2025 if (epsts & UDC_EPSTS_TDC)
2026 pch_udc_complete_transfer(ep);
2027 /* On IN interrupt, provide data if we have any */
2028 if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_RSS) &&
2029 !(epsts & UDC_EPSTS_TDC) && !(epsts & UDC_EPSTS_TXEMPTY))
2030 pch_udc_start_next_txrequest(ep);
2031 }
2032
2033 /**
2034 * pch_udc_svc_data_out() - Handles interrupts from OUT endpoint
2035 * @dev: Reference to the device structure
2036 * @ep_num: Endpoint that generated the interrupt
2037 */
2038 static void pch_udc_svc_data_out(struct pch_udc_dev *dev, int ep_num)
2039 {
2040 u32 epsts;
2041 struct pch_udc_ep *ep;
2042 struct pch_udc_request *req = NULL;
2043
2044 ep = &dev->ep[UDC_EPOUT_IDX(ep_num)];
2045 epsts = ep->epsts;
2046 ep->epsts = 0;
2047
2048 if ((epsts & UDC_EPSTS_BNA) && (!list_empty(&ep->queue))) {
2049 /* next request */
2050 req = list_entry(ep->queue.next, struct pch_udc_request,
2051 queue);
2052 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
2053 PCH_UDC_BS_DMA_DONE) {
2054 if (!req->dma_going)
2055 pch_udc_start_rxrequest(ep, req);
2056 return;
2057 }
2058 }
2059 if (epsts & UDC_EPSTS_HE)
2060 return;
2061 if (epsts & UDC_EPSTS_RSS) {
2062 pch_udc_ep_set_stall(ep);
2063 pch_udc_enable_ep_interrupts(ep->dev,
2064 PCH_UDC_EPINT(ep->in, ep->num));
2065 }
2066 if (epsts & UDC_EPSTS_RCS) {
2067 if (!dev->prot_stall) {
2068 pch_udc_ep_clear_stall(ep);
2069 } else {
2070 pch_udc_ep_set_stall(ep);
2071 pch_udc_enable_ep_interrupts(ep->dev,
2072 PCH_UDC_EPINT(ep->in, ep->num));
2073 }
2074 }
2075 if (((epsts & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2076 UDC_EPSTS_OUT_DATA) {
2077 if (ep->dev->prot_stall == 1) {
2078 pch_udc_ep_set_stall(ep);
2079 pch_udc_enable_ep_interrupts(ep->dev,
2080 PCH_UDC_EPINT(ep->in, ep->num));
2081 } else {
2082 pch_udc_complete_receiver(ep);
2083 }
2084 }
2085 if (list_empty(&ep->queue))
2086 pch_udc_set_dma(dev, DMA_DIR_RX);
2087 }
2088
2089 /**
2090 * pch_udc_svc_control_in() - Handle Control IN endpoint interrupts
2091 * @dev: Reference to the device structure
2092 */
2093 static void pch_udc_svc_control_in(struct pch_udc_dev *dev)
2094 {
2095 u32 epsts;
2096 struct pch_udc_ep *ep;
2097 struct pch_udc_ep *ep_out;
2098
2099 ep = &dev->ep[UDC_EP0IN_IDX];
2100 ep_out = &dev->ep[UDC_EP0OUT_IDX];
2101 epsts = ep->epsts;
2102 ep->epsts = 0;
2103
2104 if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA | UDC_EPSTS_HE |
2105 UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
2106 UDC_EPSTS_XFERDONE)))
2107 return;
2108 if ((epsts & UDC_EPSTS_BNA))
2109 return;
2110 if (epsts & UDC_EPSTS_HE)
2111 return;
2112 if ((epsts & UDC_EPSTS_TDC) && (!dev->stall)) {
2113 pch_udc_complete_transfer(ep);
2114 pch_udc_clear_dma(dev, DMA_DIR_RX);
2115 ep_out->td_data->status = (ep_out->td_data->status &
2116 ~PCH_UDC_BUFF_STS) |
2117 PCH_UDC_BS_HST_RDY;
2118 pch_udc_ep_clear_nak(ep_out);
2119 pch_udc_set_dma(dev, DMA_DIR_RX);
2120 pch_udc_ep_set_rrdy(ep_out);
2121 }
2122 /* On IN interrupt, provide data if we have any */
2123 if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_TDC) &&
2124 !(epsts & UDC_EPSTS_TXEMPTY))
2125 pch_udc_start_next_txrequest(ep);
2126 }
2127
2128 /**
2129 * pch_udc_svc_control_out() - Routine that handle Control
2130 * OUT endpoint interrupts
2131 * @dev: Reference to the device structure
2132 */
2133 static void pch_udc_svc_control_out(struct pch_udc_dev *dev)
2134 {
2135 u32 stat;
2136 int setup_supported;
2137 struct pch_udc_ep *ep;
2138
2139 ep = &dev->ep[UDC_EP0OUT_IDX];
2140 stat = ep->epsts;
2141 ep->epsts = 0;
2142
2143 /* If setup data */
2144 if (((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2145 UDC_EPSTS_OUT_SETUP) {
2146 dev->stall = 0;
2147 dev->ep[UDC_EP0IN_IDX].halted = 0;
2148 dev->ep[UDC_EP0OUT_IDX].halted = 0;
2149 dev->setup_data = ep->td_stp->request;
2150 pch_udc_init_setup_buff(ep->td_stp);
2151 pch_udc_clear_dma(dev, DMA_DIR_RX);
2152 pch_udc_ep_fifo_flush(&(dev->ep[UDC_EP0IN_IDX]),
2153 dev->ep[UDC_EP0IN_IDX].in);
2154 if ((dev->setup_data.bRequestType & USB_DIR_IN))
2155 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2156 else /* OUT */
2157 dev->gadget.ep0 = &ep->ep;
2158 spin_unlock(&dev->lock);
2159 /* If Mass storage Reset */
2160 if ((dev->setup_data.bRequestType == 0x21) &&
2161 (dev->setup_data.bRequest == 0xFF))
2162 dev->prot_stall = 0;
2163 /* call gadget with setup data received */
2164 setup_supported = dev->driver->setup(&dev->gadget,
2165 &dev->setup_data);
2166 spin_lock(&dev->lock);
2167
2168 if (dev->setup_data.bRequestType & USB_DIR_IN) {
2169 ep->td_data->status = (ep->td_data->status &
2170 ~PCH_UDC_BUFF_STS) |
2171 PCH_UDC_BS_HST_RDY;
2172 pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2173 }
2174 /* ep0 in returns data on IN phase */
2175 if (setup_supported >= 0 && setup_supported <
2176 UDC_EP0IN_MAX_PKT_SIZE) {
2177 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
2178 /* Gadget would have queued a request when
2179 * we called the setup */
2180 if (!(dev->setup_data.bRequestType & USB_DIR_IN)) {
2181 pch_udc_set_dma(dev, DMA_DIR_RX);
2182 pch_udc_ep_clear_nak(ep);
2183 }
2184 } else if (setup_supported < 0) {
2185 /* if unsupported request, then stall */
2186 pch_udc_ep_set_stall(&(dev->ep[UDC_EP0IN_IDX]));
2187 pch_udc_enable_ep_interrupts(ep->dev,
2188 PCH_UDC_EPINT(ep->in, ep->num));
2189 dev->stall = 0;
2190 pch_udc_set_dma(dev, DMA_DIR_RX);
2191 } else {
2192 dev->waiting_zlp_ack = 1;
2193 }
2194 } else if ((((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2195 UDC_EPSTS_OUT_DATA) && !dev->stall) {
2196 pch_udc_clear_dma(dev, DMA_DIR_RX);
2197 pch_udc_ep_set_ddptr(ep, 0);
2198 if (!list_empty(&ep->queue)) {
2199 ep->epsts = stat;
2200 pch_udc_svc_data_out(dev, PCH_UDC_EP0);
2201 }
2202 pch_udc_set_dma(dev, DMA_DIR_RX);
2203 }
2204 pch_udc_ep_set_rrdy(ep);
2205 }
2206
2207
2208 /**
2209 * pch_udc_postsvc_epinters() - This function enables end point interrupts
2210 * and clears NAK status
2211 * @dev: Reference to the device structure
2212 * @ep_num: End point number
2213 */
2214 static void pch_udc_postsvc_epinters(struct pch_udc_dev *dev, int ep_num)
2215 {
2216 struct pch_udc_ep *ep;
2217 struct pch_udc_request *req;
2218
2219 ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2220 if (!list_empty(&ep->queue)) {
2221 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2222 pch_udc_enable_ep_interrupts(ep->dev,
2223 PCH_UDC_EPINT(ep->in, ep->num));
2224 pch_udc_ep_clear_nak(ep);
2225 }
2226 }
2227
2228 /**
2229 * pch_udc_read_all_epstatus() - This function read all endpoint status
2230 * @dev: Reference to the device structure
2231 * @ep_intr: Status of endpoint interrupt
2232 */
2233 static void pch_udc_read_all_epstatus(struct pch_udc_dev *dev, u32 ep_intr)
2234 {
2235 int i;
2236 struct pch_udc_ep *ep;
2237
2238 for (i = 0; i < PCH_UDC_USED_EP_NUM; i++) {
2239 /* IN */
2240 if (ep_intr & (0x1 << i)) {
2241 ep = &dev->ep[UDC_EPIN_IDX(i)];
2242 ep->epsts = pch_udc_read_ep_status(ep);
2243 pch_udc_clear_ep_status(ep, ep->epsts);
2244 }
2245 /* OUT */
2246 if (ep_intr & (0x10000 << i)) {
2247 ep = &dev->ep[UDC_EPOUT_IDX(i)];
2248 ep->epsts = pch_udc_read_ep_status(ep);
2249 pch_udc_clear_ep_status(ep, ep->epsts);
2250 }
2251 }
2252 }
2253
2254 /**
2255 * pch_udc_activate_control_ep() - This function enables the control endpoints
2256 * for traffic after a reset
2257 * @dev: Reference to the device structure
2258 */
2259 static void pch_udc_activate_control_ep(struct pch_udc_dev *dev)
2260 {
2261 struct pch_udc_ep *ep;
2262 u32 val;
2263
2264 /* Setup the IN endpoint */
2265 ep = &dev->ep[UDC_EP0IN_IDX];
2266 pch_udc_clear_ep_control(ep);
2267 pch_udc_ep_fifo_flush(ep, ep->in);
2268 pch_udc_ep_set_bufsz(ep, UDC_EP0IN_BUFF_SIZE, ep->in);
2269 pch_udc_ep_set_maxpkt(ep, UDC_EP0IN_MAX_PKT_SIZE);
2270 /* Initialize the IN EP Descriptor */
2271 ep->td_data = NULL;
2272 ep->td_stp = NULL;
2273 ep->td_data_phys = 0;
2274 ep->td_stp_phys = 0;
2275
2276 /* Setup the OUT endpoint */
2277 ep = &dev->ep[UDC_EP0OUT_IDX];
2278 pch_udc_clear_ep_control(ep);
2279 pch_udc_ep_fifo_flush(ep, ep->in);
2280 pch_udc_ep_set_bufsz(ep, UDC_EP0OUT_BUFF_SIZE, ep->in);
2281 pch_udc_ep_set_maxpkt(ep, UDC_EP0OUT_MAX_PKT_SIZE);
2282 val = UDC_EP0OUT_MAX_PKT_SIZE << UDC_CSR_NE_MAX_PKT_SHIFT;
2283 pch_udc_write_csr(ep->dev, val, UDC_EP0OUT_IDX);
2284
2285 /* Initialize the SETUP buffer */
2286 pch_udc_init_setup_buff(ep->td_stp);
2287 /* Write the pointer address of dma descriptor */
2288 pch_udc_ep_set_subptr(ep, ep->td_stp_phys);
2289 /* Write the pointer address of Setup descriptor */
2290 pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2291
2292 /* Initialize the dma descriptor */
2293 ep->td_data->status = PCH_UDC_DMA_LAST;
2294 ep->td_data->dataptr = dev->dma_addr;
2295 ep->td_data->next = ep->td_data_phys;
2296
2297 pch_udc_ep_clear_nak(ep);
2298 }
2299
2300
2301 /**
2302 * pch_udc_svc_ur_interrupt() - This function handles a USB reset interrupt
2303 * @dev: Reference to driver structure
2304 */
2305 static void pch_udc_svc_ur_interrupt(struct pch_udc_dev *dev)
2306 {
2307 struct pch_udc_ep *ep;
2308 int i;
2309
2310 pch_udc_clear_dma(dev, DMA_DIR_TX);
2311 pch_udc_clear_dma(dev, DMA_DIR_RX);
2312 /* Mask all endpoint interrupts */
2313 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2314 /* clear all endpoint interrupts */
2315 pch_udc_write_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2316
2317 for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2318 ep = &dev->ep[i];
2319 pch_udc_clear_ep_status(ep, UDC_EPSTS_ALL_CLR_MASK);
2320 pch_udc_clear_ep_control(ep);
2321 pch_udc_ep_set_ddptr(ep, 0);
2322 pch_udc_write_csr(ep->dev, 0x00, i);
2323 }
2324 dev->stall = 0;
2325 dev->prot_stall = 0;
2326 dev->waiting_zlp_ack = 0;
2327 dev->set_cfg_not_acked = 0;
2328
2329 /* disable ep to empty req queue. Skip the control EP's */
2330 for (i = 0; i < (PCH_UDC_USED_EP_NUM*2); i++) {
2331 ep = &dev->ep[i];
2332 pch_udc_ep_set_nak(ep);
2333 pch_udc_ep_fifo_flush(ep, ep->in);
2334 /* Complete request queue */
2335 empty_req_queue(ep);
2336 }
2337 if (dev->driver && dev->driver->disconnect)
2338 dev->driver->disconnect(&dev->gadget);
2339 }
2340
2341 /**
2342 * pch_udc_svc_enum_interrupt() - This function handles a USB speed enumeration
2343 * done interrupt
2344 * @dev: Reference to driver structure
2345 */
2346 static void pch_udc_svc_enum_interrupt(struct pch_udc_dev *dev)
2347 {
2348 u32 dev_stat, dev_speed;
2349 u32 speed = USB_SPEED_FULL;
2350
2351 dev_stat = pch_udc_read_device_status(dev);
2352 dev_speed = (dev_stat & UDC_DEVSTS_ENUM_SPEED_MASK) >>
2353 UDC_DEVSTS_ENUM_SPEED_SHIFT;
2354 switch (dev_speed) {
2355 case UDC_DEVSTS_ENUM_SPEED_HIGH:
2356 speed = USB_SPEED_HIGH;
2357 break;
2358 case UDC_DEVSTS_ENUM_SPEED_FULL:
2359 speed = USB_SPEED_FULL;
2360 break;
2361 case UDC_DEVSTS_ENUM_SPEED_LOW:
2362 speed = USB_SPEED_LOW;
2363 break;
2364 default:
2365 BUG();
2366 }
2367 dev->gadget.speed = speed;
2368 pch_udc_activate_control_ep(dev);
2369 pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 | UDC_EPINT_OUT_EP0);
2370 pch_udc_set_dma(dev, DMA_DIR_TX);
2371 pch_udc_set_dma(dev, DMA_DIR_RX);
2372 pch_udc_ep_set_rrdy(&(dev->ep[UDC_EP0OUT_IDX]));
2373 }
2374
2375 /**
2376 * pch_udc_svc_intf_interrupt() - This function handles a set interface
2377 * interrupt
2378 * @dev: Reference to driver structure
2379 */
2380 static void pch_udc_svc_intf_interrupt(struct pch_udc_dev *dev)
2381 {
2382 u32 reg, dev_stat = 0;
2383 int i, ret;
2384
2385 dev_stat = pch_udc_read_device_status(dev);
2386 dev->cfg_data.cur_intf = (dev_stat & UDC_DEVSTS_INTF_MASK) >>
2387 UDC_DEVSTS_INTF_SHIFT;
2388 dev->cfg_data.cur_alt = (dev_stat & UDC_DEVSTS_ALT_MASK) >>
2389 UDC_DEVSTS_ALT_SHIFT;
2390 dev->set_cfg_not_acked = 1;
2391 /* Construct the usb request for gadget driver and inform it */
2392 memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2393 dev->setup_data.bRequest = USB_REQ_SET_INTERFACE;
2394 dev->setup_data.bRequestType = USB_RECIP_INTERFACE;
2395 dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_alt);
2396 dev->setup_data.wIndex = cpu_to_le16(dev->cfg_data.cur_intf);
2397 /* programm the Endpoint Cfg registers */
2398 /* Only one end point cfg register */
2399 reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2400 reg = (reg & ~UDC_CSR_NE_INTF_MASK) |
2401 (dev->cfg_data.cur_intf << UDC_CSR_NE_INTF_SHIFT);
2402 reg = (reg & ~UDC_CSR_NE_ALT_MASK) |
2403 (dev->cfg_data.cur_alt << UDC_CSR_NE_ALT_SHIFT);
2404 pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2405 for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2406 /* clear stall bits */
2407 pch_udc_ep_clear_stall(&(dev->ep[i]));
2408 dev->ep[i].halted = 0;
2409 }
2410 dev->stall = 0;
2411 spin_unlock(&dev->lock);
2412 ret = dev->driver->setup(&dev->gadget, &dev->setup_data);
2413 spin_lock(&dev->lock);
2414 }
2415
2416 /**
2417 * pch_udc_svc_cfg_interrupt() - This function handles a set configuration
2418 * interrupt
2419 * @dev: Reference to driver structure
2420 */
2421 static void pch_udc_svc_cfg_interrupt(struct pch_udc_dev *dev)
2422 {
2423 int i, ret;
2424 u32 reg, dev_stat = 0;
2425
2426 dev_stat = pch_udc_read_device_status(dev);
2427 dev->set_cfg_not_acked = 1;
2428 dev->cfg_data.cur_cfg = (dev_stat & UDC_DEVSTS_CFG_MASK) >>
2429 UDC_DEVSTS_CFG_SHIFT;
2430 /* make usb request for gadget driver */
2431 memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2432 dev->setup_data.bRequest = USB_REQ_SET_CONFIGURATION;
2433 dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_cfg);
2434 /* program the NE registers */
2435 /* Only one end point cfg register */
2436 reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2437 reg = (reg & ~UDC_CSR_NE_CFG_MASK) |
2438 (dev->cfg_data.cur_cfg << UDC_CSR_NE_CFG_SHIFT);
2439 pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2440 for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2441 /* clear stall bits */
2442 pch_udc_ep_clear_stall(&(dev->ep[i]));
2443 dev->ep[i].halted = 0;
2444 }
2445 dev->stall = 0;
2446
2447 /* call gadget zero with setup data received */
2448 spin_unlock(&dev->lock);
2449 ret = dev->driver->setup(&dev->gadget, &dev->setup_data);
2450 spin_lock(&dev->lock);
2451 }
2452
2453 /**
2454 * pch_udc_dev_isr() - This function services device interrupts
2455 * by invoking appropriate routines.
2456 * @dev: Reference to the device structure
2457 * @dev_intr: The Device interrupt status.
2458 */
2459 static void pch_udc_dev_isr(struct pch_udc_dev *dev, u32 dev_intr)
2460 {
2461 /* USB Reset Interrupt */
2462 if (dev_intr & UDC_DEVINT_UR)
2463 pch_udc_svc_ur_interrupt(dev);
2464 /* Enumeration Done Interrupt */
2465 if (dev_intr & UDC_DEVINT_ENUM)
2466 pch_udc_svc_enum_interrupt(dev);
2467 /* Set Interface Interrupt */
2468 if (dev_intr & UDC_DEVINT_SI)
2469 pch_udc_svc_intf_interrupt(dev);
2470 /* Set Config Interrupt */
2471 if (dev_intr & UDC_DEVINT_SC)
2472 pch_udc_svc_cfg_interrupt(dev);
2473 /* USB Suspend interrupt */
2474 if (dev_intr & UDC_DEVINT_US)
2475 dev_dbg(&dev->pdev->dev, "USB_SUSPEND\n");
2476 /* Clear the SOF interrupt, if enabled */
2477 if (dev_intr & UDC_DEVINT_SOF)
2478 dev_dbg(&dev->pdev->dev, "SOF\n");
2479 /* ES interrupt, IDLE > 3ms on the USB */
2480 if (dev_intr & UDC_DEVINT_ES)
2481 dev_dbg(&dev->pdev->dev, "ES\n");
2482 /* RWKP interrupt */
2483 if (dev_intr & UDC_DEVINT_RWKP)
2484 dev_dbg(&dev->pdev->dev, "RWKP\n");
2485 }
2486
2487 /**
2488 * pch_udc_isr() - This function handles interrupts from the PCH USB Device
2489 * @irq: Interrupt request number
2490 * @dev: Reference to the device structure
2491 */
2492 static irqreturn_t pch_udc_isr(int irq, void *pdev)
2493 {
2494 struct pch_udc_dev *dev = (struct pch_udc_dev *) pdev;
2495 u32 dev_intr, ep_intr;
2496 int i;
2497
2498 dev_intr = pch_udc_read_device_interrupts(dev);
2499 ep_intr = pch_udc_read_ep_interrupts(dev);
2500
2501 if (dev_intr)
2502 /* Clear device interrupts */
2503 pch_udc_write_device_interrupts(dev, dev_intr);
2504 if (ep_intr)
2505 /* Clear ep interrupts */
2506 pch_udc_write_ep_interrupts(dev, ep_intr);
2507 if (!dev_intr && !ep_intr)
2508 return IRQ_NONE;
2509 spin_lock(&dev->lock);
2510 if (dev_intr)
2511 pch_udc_dev_isr(dev, dev_intr);
2512 if (ep_intr) {
2513 pch_udc_read_all_epstatus(dev, ep_intr);
2514 /* Process Control In interrupts, if present */
2515 if (ep_intr & UDC_EPINT_IN_EP0) {
2516 pch_udc_svc_control_in(dev);
2517 pch_udc_postsvc_epinters(dev, 0);
2518 }
2519 /* Process Control Out interrupts, if present */
2520 if (ep_intr & UDC_EPINT_OUT_EP0)
2521 pch_udc_svc_control_out(dev);
2522 /* Process data in end point interrupts */
2523 for (i = 1; i < PCH_UDC_USED_EP_NUM; i++) {
2524 if (ep_intr & (1 << i)) {
2525 pch_udc_svc_data_in(dev, i);
2526 pch_udc_postsvc_epinters(dev, i);
2527 }
2528 }
2529 /* Process data out end point interrupts */
2530 for (i = UDC_EPINT_OUT_SHIFT + 1; i < (UDC_EPINT_OUT_SHIFT +
2531 PCH_UDC_USED_EP_NUM); i++)
2532 if (ep_intr & (1 << i))
2533 pch_udc_svc_data_out(dev, i -
2534 UDC_EPINT_OUT_SHIFT);
2535 }
2536 spin_unlock(&dev->lock);
2537 return IRQ_HANDLED;
2538 }
2539
2540 /**
2541 * pch_udc_setup_ep0() - This function enables control endpoint for traffic
2542 * @dev: Reference to the device structure
2543 */
2544 static void pch_udc_setup_ep0(struct pch_udc_dev *dev)
2545 {
2546 /* enable ep0 interrupts */
2547 pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 |
2548 UDC_EPINT_OUT_EP0);
2549 /* enable device interrupts */
2550 pch_udc_enable_interrupts(dev, UDC_DEVINT_UR | UDC_DEVINT_US |
2551 UDC_DEVINT_ES | UDC_DEVINT_ENUM |
2552 UDC_DEVINT_SI | UDC_DEVINT_SC);
2553 }
2554
2555 /**
2556 * gadget_release() - Free the gadget driver private data
2557 * @pdev reference to struct pci_dev
2558 */
2559 static void gadget_release(struct device *pdev)
2560 {
2561 struct pch_udc_dev *dev = dev_get_drvdata(pdev);
2562
2563 kfree(dev);
2564 }
2565
2566 /**
2567 * pch_udc_pcd_reinit() - This API initializes the endpoint structures
2568 * @dev: Reference to the driver structure
2569 */
2570 static void pch_udc_pcd_reinit(struct pch_udc_dev *dev)
2571 {
2572 const char *const ep_string[] = {
2573 ep0_string, "ep0out", "ep1in", "ep1out", "ep2in", "ep2out",
2574 "ep3in", "ep3out", "ep4in", "ep4out", "ep5in", "ep5out",
2575 "ep6in", "ep6out", "ep7in", "ep7out", "ep8in", "ep8out",
2576 "ep9in", "ep9out", "ep10in", "ep10out", "ep11in", "ep11out",
2577 "ep12in", "ep12out", "ep13in", "ep13out", "ep14in", "ep14out",
2578 "ep15in", "ep15out",
2579 };
2580 int i;
2581
2582 dev->gadget.speed = USB_SPEED_UNKNOWN;
2583 INIT_LIST_HEAD(&dev->gadget.ep_list);
2584
2585 /* Initialize the endpoints structures */
2586 memset(dev->ep, 0, sizeof dev->ep);
2587 for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2588 struct pch_udc_ep *ep = &dev->ep[i];
2589 ep->dev = dev;
2590 ep->halted = 1;
2591 ep->num = i / 2;
2592 ep->in = ~i & 1;
2593 ep->ep.name = ep_string[i];
2594 ep->ep.ops = &pch_udc_ep_ops;
2595 if (ep->in)
2596 ep->offset_addr = ep->num * UDC_EP_REG_SHIFT;
2597 else
2598 ep->offset_addr = (UDC_EPINT_OUT_SHIFT + ep->num) *
2599 UDC_EP_REG_SHIFT;
2600 /* need to set ep->ep.maxpacket and set Default Configuration?*/
2601 ep->ep.maxpacket = UDC_BULK_MAX_PKT_SIZE;
2602 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
2603 INIT_LIST_HEAD(&ep->queue);
2604 }
2605 dev->ep[UDC_EP0IN_IDX].ep.maxpacket = UDC_EP0IN_MAX_PKT_SIZE;
2606 dev->ep[UDC_EP0OUT_IDX].ep.maxpacket = UDC_EP0OUT_MAX_PKT_SIZE;
2607
2608 /* remove ep0 in and out from the list. They have own pointer */
2609 list_del_init(&dev->ep[UDC_EP0IN_IDX].ep.ep_list);
2610 list_del_init(&dev->ep[UDC_EP0OUT_IDX].ep.ep_list);
2611
2612 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2613 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
2614 }
2615
2616 /**
2617 * pch_udc_pcd_init() - This API initializes the driver structure
2618 * @dev: Reference to the driver structure
2619 *
2620 * Return codes:
2621 * 0: Success
2622 */
2623 static int pch_udc_pcd_init(struct pch_udc_dev *dev)
2624 {
2625 pch_udc_init(dev);
2626 pch_udc_pcd_reinit(dev);
2627 return 0;
2628 }
2629
2630 /**
2631 * init_dma_pools() - create dma pools during initialization
2632 * @pdev: reference to struct pci_dev
2633 */
2634 static int init_dma_pools(struct pch_udc_dev *dev)
2635 {
2636 struct pch_udc_stp_dma_desc *td_stp;
2637 struct pch_udc_data_dma_desc *td_data;
2638
2639 /* DMA setup */
2640 dev->data_requests = pci_pool_create("data_requests", dev->pdev,
2641 sizeof(struct pch_udc_data_dma_desc), 0, 0);
2642 if (!dev->data_requests) {
2643 dev_err(&dev->pdev->dev, "%s: can't get request data pool\n",
2644 __func__);
2645 return -ENOMEM;
2646 }
2647
2648 /* dma desc for setup data */
2649 dev->stp_requests = pci_pool_create("setup requests", dev->pdev,
2650 sizeof(struct pch_udc_stp_dma_desc), 0, 0);
2651 if (!dev->stp_requests) {
2652 dev_err(&dev->pdev->dev, "%s: can't get setup request pool\n",
2653 __func__);
2654 return -ENOMEM;
2655 }
2656 /* setup */
2657 td_stp = pci_pool_alloc(dev->stp_requests, GFP_KERNEL,
2658 &dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
2659 if (!td_stp) {
2660 dev_err(&dev->pdev->dev,
2661 "%s: can't allocate setup dma descriptor\n", __func__);
2662 return -ENOMEM;
2663 }
2664 dev->ep[UDC_EP0OUT_IDX].td_stp = td_stp;
2665
2666 /* data: 0 packets !? */
2667 td_data = pci_pool_alloc(dev->data_requests, GFP_KERNEL,
2668 &dev->ep[UDC_EP0OUT_IDX].td_data_phys);
2669 if (!td_data) {
2670 dev_err(&dev->pdev->dev,
2671 "%s: can't allocate data dma descriptor\n", __func__);
2672 return -ENOMEM;
2673 }
2674 dev->ep[UDC_EP0OUT_IDX].td_data = td_data;
2675 dev->ep[UDC_EP0IN_IDX].td_stp = NULL;
2676 dev->ep[UDC_EP0IN_IDX].td_stp_phys = 0;
2677 dev->ep[UDC_EP0IN_IDX].td_data = NULL;
2678 dev->ep[UDC_EP0IN_IDX].td_data_phys = 0;
2679
2680 dev->ep0out_buf = kzalloc(UDC_EP0OUT_BUFF_SIZE * 4, GFP_KERNEL);
2681 if (!dev->ep0out_buf)
2682 return -ENOMEM;
2683 dev->dma_addr = dma_map_single(&dev->pdev->dev, dev->ep0out_buf,
2684 UDC_EP0OUT_BUFF_SIZE * 4,
2685 DMA_FROM_DEVICE);
2686 return 0;
2687 }
2688
2689 static int pch_udc_start(struct usb_gadget_driver *driver,
2690 int (*bind)(struct usb_gadget *))
2691 {
2692 struct pch_udc_dev *dev = pch_udc;
2693 int retval;
2694
2695 if (!driver || (driver->speed == USB_SPEED_UNKNOWN) || !bind ||
2696 !driver->setup || !driver->unbind || !driver->disconnect) {
2697 dev_err(&dev->pdev->dev,
2698 "%s: invalid driver parameter\n", __func__);
2699 return -EINVAL;
2700 }
2701
2702 if (!dev)
2703 return -ENODEV;
2704
2705 if (dev->driver) {
2706 dev_err(&dev->pdev->dev, "%s: already bound\n", __func__);
2707 return -EBUSY;
2708 }
2709 driver->driver.bus = NULL;
2710 dev->driver = driver;
2711 dev->gadget.dev.driver = &driver->driver;
2712
2713 /* Invoke the bind routine of the gadget driver */
2714 retval = bind(&dev->gadget);
2715
2716 if (retval) {
2717 dev_err(&dev->pdev->dev, "%s: binding to %s returning %d\n",
2718 __func__, driver->driver.name, retval);
2719 dev->driver = NULL;
2720 dev->gadget.dev.driver = NULL;
2721 return retval;
2722 }
2723 /* get ready for ep0 traffic */
2724 pch_udc_setup_ep0(dev);
2725
2726 /* clear SD */
2727 pch_udc_clear_disconnect(dev);
2728
2729 dev->connected = 1;
2730 return 0;
2731 }
2732
2733 static int pch_udc_stop(struct usb_gadget_driver *driver)
2734 {
2735 struct pch_udc_dev *dev = pch_udc;
2736
2737 if (!dev)
2738 return -ENODEV;
2739
2740 if (!driver || (driver != dev->driver)) {
2741 dev_err(&dev->pdev->dev,
2742 "%s: invalid driver parameter\n", __func__);
2743 return -EINVAL;
2744 }
2745
2746 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
2747
2748 /* Assures that there are no pending requests with this driver */
2749 driver->disconnect(&dev->gadget);
2750 driver->unbind(&dev->gadget);
2751 dev->gadget.dev.driver = NULL;
2752 dev->driver = NULL;
2753 dev->connected = 0;
2754
2755 /* set SD */
2756 pch_udc_set_disconnect(dev);
2757 return 0;
2758 }
2759
2760 static void pch_udc_shutdown(struct pci_dev *pdev)
2761 {
2762 struct pch_udc_dev *dev = pci_get_drvdata(pdev);
2763
2764 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
2765 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2766
2767 /* disable the pullup so the host will think we're gone */
2768 pch_udc_set_disconnect(dev);
2769 }
2770
2771 static void pch_udc_remove(struct pci_dev *pdev)
2772 {
2773 struct pch_udc_dev *dev = pci_get_drvdata(pdev);
2774
2775 usb_del_gadget_udc(&dev->gadget);
2776
2777 /* gadget driver must not be registered */
2778 if (dev->driver)
2779 dev_err(&pdev->dev,
2780 "%s: gadget driver still bound!!!\n", __func__);
2781 /* dma pool cleanup */
2782 if (dev->data_requests)
2783 pci_pool_destroy(dev->data_requests);
2784
2785 if (dev->stp_requests) {
2786 /* cleanup DMA desc's for ep0in */
2787 if (dev->ep[UDC_EP0OUT_IDX].td_stp) {
2788 pci_pool_free(dev->stp_requests,
2789 dev->ep[UDC_EP0OUT_IDX].td_stp,
2790 dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
2791 }
2792 if (dev->ep[UDC_EP0OUT_IDX].td_data) {
2793 pci_pool_free(dev->stp_requests,
2794 dev->ep[UDC_EP0OUT_IDX].td_data,
2795 dev->ep[UDC_EP0OUT_IDX].td_data_phys);
2796 }
2797 pci_pool_destroy(dev->stp_requests);
2798 }
2799
2800 if (dev->dma_addr)
2801 dma_unmap_single(&dev->pdev->dev, dev->dma_addr,
2802 UDC_EP0OUT_BUFF_SIZE * 4, DMA_FROM_DEVICE);
2803 kfree(dev->ep0out_buf);
2804
2805 pch_udc_exit(dev);
2806
2807 if (dev->irq_registered)
2808 free_irq(pdev->irq, dev);
2809 if (dev->base_addr)
2810 iounmap(dev->base_addr);
2811 if (dev->mem_region)
2812 release_mem_region(dev->phys_addr,
2813 pci_resource_len(pdev, PCH_UDC_PCI_BAR));
2814 if (dev->active)
2815 pci_disable_device(pdev);
2816 if (dev->registered)
2817 device_unregister(&dev->gadget.dev);
2818 kfree(dev);
2819 pci_set_drvdata(pdev, NULL);
2820 }
2821
2822 #ifdef CONFIG_PM
2823 static int pch_udc_suspend(struct pci_dev *pdev, pm_message_t state)
2824 {
2825 struct pch_udc_dev *dev = pci_get_drvdata(pdev);
2826
2827 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
2828 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2829
2830 pci_disable_device(pdev);
2831 pci_enable_wake(pdev, PCI_D3hot, 0);
2832
2833 if (pci_save_state(pdev)) {
2834 dev_err(&pdev->dev,
2835 "%s: could not save PCI config state\n", __func__);
2836 return -ENOMEM;
2837 }
2838 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2839 return 0;
2840 }
2841
2842 static int pch_udc_resume(struct pci_dev *pdev)
2843 {
2844 int ret;
2845
2846 pci_set_power_state(pdev, PCI_D0);
2847 pci_restore_state(pdev);
2848 ret = pci_enable_device(pdev);
2849 if (ret) {
2850 dev_err(&pdev->dev, "%s: pci_enable_device failed\n", __func__);
2851 return ret;
2852 }
2853 pci_enable_wake(pdev, PCI_D3hot, 0);
2854 return 0;
2855 }
2856 #else
2857 #define pch_udc_suspend NULL
2858 #define pch_udc_resume NULL
2859 #endif /* CONFIG_PM */
2860
2861 static int pch_udc_probe(struct pci_dev *pdev,
2862 const struct pci_device_id *id)
2863 {
2864 unsigned long resource;
2865 unsigned long len;
2866 int retval;
2867 struct pch_udc_dev *dev;
2868
2869 /* one udc only */
2870 if (pch_udc) {
2871 pr_err("%s: already probed\n", __func__);
2872 return -EBUSY;
2873 }
2874 /* init */
2875 dev = kzalloc(sizeof *dev, GFP_KERNEL);
2876 if (!dev) {
2877 pr_err("%s: no memory for device structure\n", __func__);
2878 return -ENOMEM;
2879 }
2880 /* pci setup */
2881 if (pci_enable_device(pdev) < 0) {
2882 kfree(dev);
2883 pr_err("%s: pci_enable_device failed\n", __func__);
2884 return -ENODEV;
2885 }
2886 dev->active = 1;
2887 pci_set_drvdata(pdev, dev);
2888
2889 /* PCI resource allocation */
2890 resource = pci_resource_start(pdev, 1);
2891 len = pci_resource_len(pdev, 1);
2892
2893 if (!request_mem_region(resource, len, KBUILD_MODNAME)) {
2894 dev_err(&pdev->dev, "%s: pci device used already\n", __func__);
2895 retval = -EBUSY;
2896 goto finished;
2897 }
2898 dev->phys_addr = resource;
2899 dev->mem_region = 1;
2900
2901 dev->base_addr = ioremap_nocache(resource, len);
2902 if (!dev->base_addr) {
2903 pr_err("%s: device memory cannot be mapped\n", __func__);
2904 retval = -ENOMEM;
2905 goto finished;
2906 }
2907 if (!pdev->irq) {
2908 dev_err(&pdev->dev, "%s: irq not set\n", __func__);
2909 retval = -ENODEV;
2910 goto finished;
2911 }
2912 pch_udc = dev;
2913 /* initialize the hardware */
2914 if (pch_udc_pcd_init(dev))
2915 goto finished;
2916 if (request_irq(pdev->irq, pch_udc_isr, IRQF_SHARED, KBUILD_MODNAME,
2917 dev)) {
2918 dev_err(&pdev->dev, "%s: request_irq(%d) fail\n", __func__,
2919 pdev->irq);
2920 retval = -ENODEV;
2921 goto finished;
2922 }
2923 dev->irq = pdev->irq;
2924 dev->irq_registered = 1;
2925
2926 pci_set_master(pdev);
2927 pci_try_set_mwi(pdev);
2928
2929 /* device struct setup */
2930 spin_lock_init(&dev->lock);
2931 dev->pdev = pdev;
2932 dev->gadget.ops = &pch_udc_ops;
2933
2934 retval = init_dma_pools(dev);
2935 if (retval)
2936 goto finished;
2937
2938 dev_set_name(&dev->gadget.dev, "gadget");
2939 dev->gadget.dev.parent = &pdev->dev;
2940 dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
2941 dev->gadget.dev.release = gadget_release;
2942 dev->gadget.name = KBUILD_MODNAME;
2943 dev->gadget.is_dualspeed = 1;
2944
2945 retval = device_register(&dev->gadget.dev);
2946 if (retval)
2947 goto finished;
2948 dev->registered = 1;
2949
2950 /* Put the device in disconnected state till a driver is bound */
2951 pch_udc_set_disconnect(dev);
2952 retval = usb_add_gadget_udc(&pdev->dev, &dev->gadget);
2953 if (retval)
2954 goto finished;
2955 return 0;
2956
2957 finished:
2958 pch_udc_remove(pdev);
2959 return retval;
2960 }
2961
2962 static DEFINE_PCI_DEVICE_TABLE(pch_udc_pcidev_id) = {
2963 {
2964 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EG20T_UDC),
2965 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
2966 .class_mask = 0xffffffff,
2967 },
2968 {
2969 PCI_DEVICE(PCI_VENDOR_ID_ROHM, PCI_DEVICE_ID_ML7213_IOH_UDC),
2970 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
2971 .class_mask = 0xffffffff,
2972 },
2973 { 0 },
2974 };
2975
2976 MODULE_DEVICE_TABLE(pci, pch_udc_pcidev_id);
2977
2978
2979 static struct pci_driver pch_udc_driver = {
2980 .name = KBUILD_MODNAME,
2981 .id_table = pch_udc_pcidev_id,
2982 .probe = pch_udc_probe,
2983 .remove = pch_udc_remove,
2984 .suspend = pch_udc_suspend,
2985 .resume = pch_udc_resume,
2986 .shutdown = pch_udc_shutdown,
2987 };
2988
2989 static int __init pch_udc_pci_init(void)
2990 {
2991 return pci_register_driver(&pch_udc_driver);
2992 }
2993 module_init(pch_udc_pci_init);
2994
2995 static void __exit pch_udc_pci_exit(void)
2996 {
2997 pci_unregister_driver(&pch_udc_driver);
2998 }
2999 module_exit(pch_udc_pci_exit);
3000
3001 MODULE_DESCRIPTION("Intel EG20T USB Device Controller");
3002 MODULE_AUTHOR("OKI SEMICONDUCTOR, <toshiharu-linux@dsn.okisemi.com>");
3003 MODULE_LICENSE("GPL");