drivers/usb/host/uhci-hcd.h

   1 #ifndef __LINUX_UHCI_HCD_H
   2 #define __LINUX_UHCI_HCD_H
   3
   4 #include <linux/list.h>
   5 #include <linux/usb.h>
   6
   7 #define usb_packetid(pipe)      (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT)
   8 #define PIPE_DEVEP_MASK         0x0007ff00
   9
  10
  11 /*
  12  * Universal Host Controller Interface data structures and defines
  13  */
  14
  15 /* Command register */
  16 #define USBCMD          0
  17 #define   USBCMD_RS             0x0001  /* Run/Stop */
  18 #define   USBCMD_HCRESET        0x0002  /* Host reset */
  19 #define   USBCMD_GRESET         0x0004  /* Global reset */
  20 #define   USBCMD_EGSM           0x0008  /* Global Suspend Mode */
  21 #define   USBCMD_FGR            0x0010  /* Force Global Resume */
  22 #define   USBCMD_SWDBG          0x0020  /* SW Debug mode */
  23 #define   USBCMD_CF             0x0040  /* Config Flag (sw only) */
  24 #define   USBCMD_MAXP           0x0080  /* Max Packet (0 = 32, 1 = 64) */
  25
  26 /* Status register */
  27 #define USBSTS          2
  28 #define   USBSTS_USBINT         0x0001  /* Interrupt due to IOC */
  29 #define   USBSTS_ERROR          0x0002  /* Interrupt due to error */
  30 #define   USBSTS_RD             0x0004  /* Resume Detect */
  31 #define   USBSTS_HSE            0x0008  /* Host System Error: PCI problems */
  32 #define   USBSTS_HCPE           0x0010  /* Host Controller Process Error:
  33                                          * the schedule is buggy */
  34 #define   USBSTS_HCH            0x0020  /* HC Halted */
  35
  36 /* Interrupt enable register */
  37 #define USBINTR         4
  38 #define   USBINTR_TIMEOUT       0x0001  /* Timeout/CRC error enable */
  39 #define   USBINTR_RESUME        0x0002  /* Resume interrupt enable */
  40 #define   USBINTR_IOC           0x0004  /* Interrupt On Complete enable */
  41 #define   USBINTR_SP            0x0008  /* Short packet interrupt enable */
  42
  43 #define USBFRNUM        6
  44 #define USBFLBASEADD    8
  45 #define USBSOF          12
  46 #define   USBSOF_DEFAULT        64      /* Frame length is exactly 1 ms */
  47
  48 /* USB port status and control registers */
  49 #define USBPORTSC1      16
  50 #define USBPORTSC2      18
  51 #define   USBPORTSC_CCS         0x0001  /* Current Connect Status
  52                                          * ("device present") */
  53 #define   USBPORTSC_CSC         0x0002  /* Connect Status Change */
  54 #define   USBPORTSC_PE          0x0004  /* Port Enable */
  55 #define   USBPORTSC_PEC         0x0008  /* Port Enable Change */
  56 #define   USBPORTSC_DPLUS       0x0010  /* D+ high (line status) */
  57 #define   USBPORTSC_DMINUS      0x0020  /* D- high (line status) */
  58 #define   USBPORTSC_RD          0x0040  /* Resume Detect */
  59 #define   USBPORTSC_RES1        0x0080  /* reserved, always 1 */
  60 #define   USBPORTSC_LSDA        0x0100  /* Low Speed Device Attached */
  61 #define   USBPORTSC_PR          0x0200  /* Port Reset */
  62 /* OC and OCC from Intel 430TX and later (not UHCI 1.1d spec) */
  63 #define   USBPORTSC_OC          0x0400  /* Over Current condition */
  64 #define   USBPORTSC_OCC         0x0800  /* Over Current Change R/WC */
  65 #define   USBPORTSC_SUSP        0x1000  /* Suspend */
  66 #define   USBPORTSC_RES2        0x2000  /* reserved, write zeroes */
  67 #define   USBPORTSC_RES3        0x4000  /* reserved, write zeroes */
  68 #define   USBPORTSC_RES4        0x8000  /* reserved, write zeroes */
  69
  70 /* PCI legacy support register */
  71 #define USBLEGSUP               0xc0
  72 #define   USBLEGSUP_DEFAULT     0x2000  /* only PIRQ enable set */
  73 #define   USBLEGSUP_RWC         0x8f00  /* the R/WC bits */
  74 #define   USBLEGSUP_RO          0x5040  /* R/O and reserved bits */
  75
  76 /* PCI Intel-specific resume-enable register */
  77 #define USBRES_INTEL            0xc4
  78 #define   USBPORT1EN            0x01
  79 #define   USBPORT2EN            0x02
  80
  81 #define UHCI_PTR_BITS(uhci)     cpu_to_hc32((uhci), 0x000F)
  82 #define UHCI_PTR_TERM(uhci)     cpu_to_hc32((uhci), 0x0001)
  83 #define UHCI_PTR_QH(uhci)       cpu_to_hc32((uhci), 0x0002)
  84 #define UHCI_PTR_DEPTH(uhci)    cpu_to_hc32((uhci), 0x0004)
  85 #define UHCI_PTR_BREADTH(uhci)  cpu_to_hc32((uhci), 0x0000)
  86
  87 #define UHCI_NUMFRAMES          1024    /* in the frame list [array] */
  88 #define UHCI_MAX_SOF_NUMBER     2047    /* in an SOF packet */
  89 #define CAN_SCHEDULE_FRAMES     1000    /* how far in the future frames
  90                                          * can be scheduled */
  91 #define MAX_PHASE               32      /* Periodic scheduling length */
  92
  93 /* When no queues need Full-Speed Bandwidth Reclamation,
  94  * delay this long before turning FSBR off */
  95 #define FSBR_OFF_DELAY          msecs_to_jiffies(10)
  96
  97 /* If a queue hasn't advanced after this much time, assume it is stuck */
  98 #define QH_WAIT_TIMEOUT         msecs_to_jiffies(200)
  99
 100
 101 /*
 102  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
 103  * __leXX (normally) or __beXX (given UHCI_BIG_ENDIAN_DESC), depending on
 104  * the host controller implementation.
 105  *
 106  * To facilitate the strongest possible byte-order checking from "sparse"
 107  * and so on, we use __leXX unless that's not practical.
 108  */
 109 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_DESC
 110 typedef __u32 __bitwise __hc32;
 111 typedef __u16 __bitwise __hc16;
 112 #else
 113 #define __hc32  __le32
 114 #define __hc16  __le16
 115 #endif
 116
 117 /*
 118  *      Queue Headers
 119  */
 120
 121 /*
 122  * One role of a QH is to hold a queue of TDs for some endpoint.  One QH goes
 123  * with each endpoint, and qh->element (updated by the HC) is either:
 124  *   - the next unprocessed TD in the endpoint's queue, or
 125  *   - UHCI_PTR_TERM (when there's no more traffic for this endpoint).
 126  *
 127  * The other role of a QH is to serve as a "skeleton" framelist entry, so we
 128  * can easily splice a QH for some endpoint into the schedule at the right
 129  * place.  Then qh->element is UHCI_PTR_TERM.
 130  *
 131  * In the schedule, qh->link maintains a list of QHs seen by the HC:
 132  *     skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ...
 133  *
 134  * qh->node is the software equivalent of qh->link.  The differences
 135  * are that the software list is doubly-linked and QHs in the UNLINKING
 136  * state are on the software list but not the hardware schedule.
 137  *
 138  * For bookkeeping purposes we maintain QHs even for Isochronous endpoints,
 139  * but they never get added to the hardware schedule.
 140  */
 141 #define QH_STATE_IDLE           1       /* QH is not being used */
 142 #define QH_STATE_UNLINKING      2       /* QH has been removed from the
 143                                          * schedule but the hardware may
 144                                          * still be using it */
 145 #define QH_STATE_ACTIVE         3       /* QH is on the schedule */
 146
 147 struct uhci_qh {
 148         /* Hardware fields */
 149         __hc32 link;                    /* Next QH in the schedule */
 150         __hc32 element;                 /* Queue element (TD) pointer */
 151
 152         /* Software fields */
 153         dma_addr_t dma_handle;
 154
 155         struct list_head node;          /* Node in the list of QHs */
 156         struct usb_host_endpoint *hep;  /* Endpoint information */
 157         struct usb_device *udev;
 158         struct list_head queue;         /* Queue of urbps for this QH */
 159         struct uhci_td *dummy_td;       /* Dummy TD to end the queue */
 160         struct uhci_td *post_td;        /* Last TD completed */
 161
 162         struct usb_iso_packet_descriptor *iso_packet_desc;
 163                                         /* Next urb->iso_frame_desc entry */
 164         unsigned long advance_jiffies;  /* Time of last queue advance */
 165         unsigned int unlink_frame;      /* When the QH was unlinked */
 166         unsigned int period;            /* For Interrupt and Isochronous QHs */
 167         short phase;                    /* Between 0 and period-1 */
 168         short load;                     /* Periodic time requirement, in us */
 169         unsigned int iso_frame;         /* Frame # for iso_packet_desc */
 170
 171         int state;                      /* QH_STATE_xxx; see above */
 172         int type;                       /* Queue type (control, bulk, etc) */
 173         int skel;                       /* Skeleton queue number */
 174
 175         unsigned int initial_toggle:1;  /* Endpoint's current toggle value */
 176         unsigned int needs_fixup:1;     /* Must fix the TD toggle values */
 177         unsigned int is_stopped:1;      /* Queue was stopped by error/unlink */
 178         unsigned int wait_expired:1;    /* QH_WAIT_TIMEOUT has expired */
 179         unsigned int bandwidth_reserved:1;      /* Periodic bandwidth has
 180                                                  * been allocated */
 181 } __attribute__((aligned(16)));
 182
 183 /*
 184  * We need a special accessor for the element pointer because it is
 185  * subject to asynchronous updates by the controller.
 186  */
 187 #define qh_element(qh)          ACCESS_ONCE((qh)->element)
 188
 189 #define LINK_TO_QH(uhci, qh)    (UHCI_PTR_QH((uhci)) | \
 190                                 cpu_to_hc32((uhci), (qh)->dma_handle))
 191
 192
 193 /*
 194  *      Transfer Descriptors
 195  */
 196
 197 /*
 198  * for TD <status>:
 199  */
 200 #define TD_CTRL_SPD             (1 << 29)       /* Short Packet Detect */
 201 #define TD_CTRL_C_ERR_MASK      (3 << 27)       /* Error Counter bits */
 202 #define TD_CTRL_C_ERR_SHIFT     27
 203 #define TD_CTRL_LS              (1 << 26)       /* Low Speed Device */
 204 #define TD_CTRL_IOS             (1 << 25)       /* Isochronous Select */
 205 #define TD_CTRL_IOC             (1 << 24)       /* Interrupt on Complete */
 206 #define TD_CTRL_ACTIVE          (1 << 23)       /* TD Active */
 207 #define TD_CTRL_STALLED         (1 << 22)       /* TD Stalled */
 208 #define TD_CTRL_DBUFERR         (1 << 21)       /* Data Buffer Error */
 209 #define TD_CTRL_BABBLE          (1 << 20)       /* Babble Detected */
 210 #define TD_CTRL_NAK             (1 << 19)       /* NAK Received */
 211 #define TD_CTRL_CRCTIMEO        (1 << 18)       /* CRC/Time Out Error */
 212 #define TD_CTRL_BITSTUFF        (1 << 17)       /* Bit Stuff Error */
 213 #define TD_CTRL_ACTLEN_MASK     0x7FF   /* actual length, encoded as n - 1 */
 214
 215 #define TD_CTRL_ANY_ERROR       (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
 216                                  TD_CTRL_BABBLE | TD_CTRL_CRCTIME | \
 217                                  TD_CTRL_BITSTUFF)
 218
 219 #define uhci_maxerr(err)                ((err) << TD_CTRL_C_ERR_SHIFT)
 220 #define uhci_status_bits(ctrl_sts)      ((ctrl_sts) & 0xF60000)
 221 #define uhci_actual_length(ctrl_sts)    (((ctrl_sts) + 1) & \
 222                         TD_CTRL_ACTLEN_MASK)    /* 1-based */
 223
 224 /*
 225  * for TD <info>: (a.k.a. Token)
 226  */
 227 #define td_token(uhci, td)      hc32_to_cpu((uhci), (td)->token)
 228 #define TD_TOKEN_DEVADDR_SHIFT  8
 229 #define TD_TOKEN_TOGGLE_SHIFT   19
 230 #define TD_TOKEN_TOGGLE         (1 << 19)
 231 #define TD_TOKEN_EXPLEN_SHIFT   21
 232 #define TD_TOKEN_EXPLEN_MASK    0x7FF   /* expected length, encoded as n-1 */
 233 #define TD_TOKEN_PID_MASK       0xFF
 234
 235 #define uhci_explen(len)        ((((len) - 1) & TD_TOKEN_EXPLEN_MASK) << \
 236                                         TD_TOKEN_EXPLEN_SHIFT)
 237
 238 #define uhci_expected_length(token) ((((token) >> TD_TOKEN_EXPLEN_SHIFT) + \
 239                                         1) & TD_TOKEN_EXPLEN_MASK)
 240 #define uhci_toggle(token)      (((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1)
 241 #define uhci_endpoint(token)    (((token) >> 15) & 0xf)
 242 #define uhci_devaddr(token)     (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f)
 243 #define uhci_devep(token)       (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff)
 244 #define uhci_packetid(token)    ((token) & TD_TOKEN_PID_MASK)
 245 #define uhci_packetout(token)   (uhci_packetid(token) != USB_PID_IN)
 246 #define uhci_packetin(token)    (uhci_packetid(token) == USB_PID_IN)
 247
 248 /*
 249  * The documentation says "4 words for hardware, 4 words for software".
 250  *
 251  * That's silly, the hardware doesn't care. The hardware only cares that
 252  * the hardware words are 16-byte aligned, and we can have any amount of
 253  * sw space after the TD entry.
 254  *
 255  * td->link points to either another TD (not necessarily for the same urb or
 256  * even the same endpoint), or nothing (PTR_TERM), or a QH.
 257  */
 258 struct uhci_td {
 259         /* Hardware fields */
 260         __hc32 link;
 261         __hc32 status;
 262         __hc32 token;
 263         __hc32 buffer;
 264
 265         /* Software fields */
 266         dma_addr_t dma_handle;
 267
 268         struct list_head list;
 269
 270         int frame;                      /* for iso: what frame? */
 271         struct list_head fl_list;
 272 } __attribute__((aligned(16)));
 273
 274 /*
 275  * We need a special accessor for the control/status word because it is
 276  * subject to asynchronous updates by the controller.
 277  */
 278 #define td_status(uhci, td)             hc32_to_cpu((uhci), \
 279                                                 ACCESS_ONCE((td)->status))
 280
 281 #define LINK_TO_TD(uhci, td)            (cpu_to_hc32((uhci), (td)->dma_handle))
 282
 283
 284 /*
 285  *      Skeleton Queue Headers
 286  */
 287
 288 /*
 289  * The UHCI driver uses QHs with Interrupt, Control and Bulk URBs for
 290  * automatic queuing. To make it easy to insert entries into the schedule,
 291  * we have a skeleton of QHs for each predefined Interrupt latency.
 292  * Asynchronous QHs (low-speed control, full-speed control, and bulk)
 293  * go onto the period-1 interrupt list, since they all get accessed on
 294  * every frame.
 295  *
 296  * When we want to add a new QH, we add it to the list starting from the
 297  * appropriate skeleton QH.  For instance, the schedule can look like this:
 298  *
 299  * skel int128 QH
 300  * dev 1 interrupt QH
 301  * dev 5 interrupt QH
 302  * skel int64 QH
 303  * skel int32 QH
 304  * ...
 305  * skel int1 + async QH
 306  * dev 5 low-speed control QH
 307  * dev 1 bulk QH
 308  * dev 2 bulk QH
 309  *
 310  * There is a special terminating QH used to keep full-speed bandwidth
 311  * reclamation active when no full-speed control or bulk QHs are linked
 312  * into the schedule.  It has an inactive TD (to work around a PIIX bug,
 313  * see the Intel errata) and it points back to itself.
 314  *
 315  * There's a special skeleton QH for Isochronous QHs which never appears
 316  * on the schedule.  Isochronous TDs go on the schedule before the
 317  * the skeleton QHs.  The hardware accesses them directly rather than
 318  * through their QH, which is used only for bookkeeping purposes.
 319  * While the UHCI spec doesn't forbid the use of QHs for Isochronous,
 320  * it doesn't use them either.  And the spec says that queues never
 321  * advance on an error completion status, which makes them totally
 322  * unsuitable for Isochronous transfers.
 323  *
 324  * There's also a special skeleton QH used for QHs which are in the process
 325  * of unlinking and so may still be in use by the hardware.  It too never
 326  * appears on the schedule.
 327  */
 328
 329 #define UHCI_NUM_SKELQH         11
 330 #define SKEL_UNLINK             0
 331 #define skel_unlink_qh          skelqh[SKEL_UNLINK]
 332 #define SKEL_ISO                1
 333 #define skel_iso_qh             skelqh[SKEL_ISO]
 334         /* int128, int64, ..., int1 = 2, 3, ..., 9 */
 335 #define SKEL_INDEX(exponent)    (9 - exponent)
 336 #define SKEL_ASYNC              9
 337 #define skel_async_qh           skelqh[SKEL_ASYNC]
 338 #define SKEL_TERM               10
 339 #define skel_term_qh            skelqh[SKEL_TERM]
 340
 341 /* The following entries refer to sublists of skel_async_qh */
 342 #define SKEL_LS_CONTROL         20
 343 #define SKEL_FS_CONTROL         21
 344 #define SKEL_FSBR               SKEL_FS_CONTROL
 345 #define SKEL_BULK               22
 346
 347 /*
 348  *      The UHCI controller and root hub
 349  */
 350
 351 /*
 352  * States for the root hub:
 353  *
 354  * To prevent "bouncing" in the presence of electrical noise,
 355  * when there are no devices attached we delay for 1 second in the
 356  * RUNNING_NODEVS state before switching to the AUTO_STOPPED state.
 357  *
 358  * (Note that the AUTO_STOPPED state won't be necessary once the hub
 359  * driver learns to autosuspend.)
 360  */
 361 enum uhci_rh_state {
 362         /* In the following states the HC must be halted.
 363          * These two must come first. */
 364         UHCI_RH_RESET,
 365         UHCI_RH_SUSPENDED,
 366
 367         UHCI_RH_AUTO_STOPPED,
 368         UHCI_RH_RESUMING,
 369
 370         /* In this state the HC changes from running to halted,
 371          * so it can legally appear either way. */
 372         UHCI_RH_SUSPENDING,
 373
 374         /* In the following states it's an error if the HC is halted.
 375          * These two must come last. */
 376         UHCI_RH_RUNNING,                /* The normal state */
 377         UHCI_RH_RUNNING_NODEVS,         /* Running with no devices attached */
 378 };
 379
 380 /*
 381  * The full UHCI controller information:
 382  */
 383 struct uhci_hcd {
 384
 385         /* debugfs */
 386         struct dentry *dentry;
 387
 388         /* Grabbed from PCI */
 389         unsigned long io_addr;
 390
 391         /* Used when registers are memory mapped */
 392         void __iomem *regs;
 393
 394         struct dma_pool *qh_pool;
 395         struct dma_pool *td_pool;
 396
 397         struct uhci_td *term_td;        /* Terminating TD, see UHCI bug */
 398         struct uhci_qh *skelqh[UHCI_NUM_SKELQH];        /* Skeleton QHs */
 399         struct uhci_qh *next_qh;        /* Next QH to scan */
 400
 401         spinlock_t lock;
 402
 403         dma_addr_t frame_dma_handle;    /* Hardware frame list */
 404         __hc32 *frame;
 405         void **frame_cpu;               /* CPU's frame list */
 406
 407         enum uhci_rh_state rh_state;
 408         unsigned long auto_stop_time;           /* When to AUTO_STOP */
 409
 410         unsigned int frame_number;              /* As of last check */
 411         unsigned int is_stopped;
 412 #define UHCI_IS_STOPPED         9999            /* Larger than a frame # */
 413         unsigned int last_iso_frame;            /* Frame of last scan */
 414         unsigned int cur_iso_frame;             /* Frame for current scan */
 415
 416         unsigned int scan_in_progress:1;        /* Schedule scan is running */
 417         unsigned int need_rescan:1;             /* Redo the schedule scan */
 418         unsigned int dead:1;                    /* Controller has died */
 419         unsigned int RD_enable:1;               /* Suspended root hub with
 420                                                    Resume-Detect interrupts
 421                                                    enabled */
 422         unsigned int is_initialized:1;          /* Data structure is usable */
 423         unsigned int fsbr_is_on:1;              /* FSBR is turned on */
 424         unsigned int fsbr_is_wanted:1;          /* Does any URB want FSBR? */
 425         unsigned int fsbr_expiring:1;           /* FSBR is timing out */
 426
 427         struct timer_list fsbr_timer;           /* For turning off FBSR */
 428
 429         /* Silicon quirks */
 430         unsigned int oc_low:1;                  /* OverCurrent bit active low */
 431         unsigned int wait_for_hp:1;             /* Wait for HP port reset */
 432         unsigned int big_endian_mmio:1;         /* Big endian registers */
 433         unsigned int big_endian_desc:1;         /* Big endian descriptors */
 434
 435         /* Support for port suspend/resume/reset */
 436         unsigned long port_c_suspend;           /* Bit-arrays of ports */
 437         unsigned long resuming_ports;
 438         unsigned long ports_timeout;            /* Time to stop signalling */
 439
 440         struct list_head idle_qh_list;          /* Where the idle QHs live */
 441
 442         int rh_numports;                        /* Number of root-hub ports */
 443
 444         wait_queue_head_t waitqh;               /* endpoint_disable waiters */
 445         int num_waiting;                        /* Number of waiters */
 446
 447         int total_load;                         /* Sum of array values */
 448         short load[MAX_PHASE];                  /* Periodic allocations */
 449
 450         /* Reset host controller */
 451         void    (*reset_hc) (struct uhci_hcd *uhci);
 452         int     (*check_and_reset_hc) (struct uhci_hcd *uhci);
 453         /* configure_hc should perform arch specific settings, if needed */
 454         void    (*configure_hc) (struct uhci_hcd *uhci);
 455         /* Check for broken resume detect interrupts */
 456         int     (*resume_detect_interrupts_are_broken) (struct uhci_hcd *uhci);
 457         /* Check for broken global suspend */
 458         int     (*global_suspend_mode_is_broken) (struct uhci_hcd *uhci);
 459 };
 460
 461 /* Convert between a usb_hcd pointer and the corresponding uhci_hcd */
 462 static inline struct uhci_hcd *hcd_to_uhci(struct usb_hcd *hcd)
 463 {
 464         return (struct uhci_hcd *) (hcd->hcd_priv);
 465 }
 466 static inline struct usb_hcd *uhci_to_hcd(struct uhci_hcd *uhci)
 467 {
 468         return container_of((void *) uhci, struct usb_hcd, hcd_priv);
 469 }
 470
 471 #define uhci_dev(u)     (uhci_to_hcd(u)->self.controller)
 472
 473 /* Utility macro for comparing frame numbers */
 474 #define uhci_frame_before_eq(f1, f2)    (0 <= (int) ((f2) - (f1)))
 475
 476
 477 /*
 478  *      Private per-URB data
 479  */
 480 struct urb_priv {
 481         struct list_head node;          /* Node in the QH's urbp list */
 482
 483         struct urb *urb;
 484
 485         struct uhci_qh *qh;             /* QH for this URB */
 486         struct list_head td_list;
 487
 488         unsigned fsbr:1;                /* URB wants FSBR */
 489 };
 490
 491
 492 /* Some special IDs */
 493
 494 #define PCI_VENDOR_ID_GENESYS           0x17a0
 495 #define PCI_DEVICE_ID_GL880S_UHCI       0x8083
 496
 497 /*
 498  * Functions used to access controller registers. The UCHI spec says that host
 499  * controller I/O registers are mapped into PCI I/O space. For non-PCI hosts
 500  * we use memory mapped registers.
 501  */
 502
 503 #ifndef CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC
 504 /* Support PCI only */
 505 static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg)
 506 {
 507         return inl(uhci->io_addr + reg);
 508 }
 509
 510 static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg)
 511 {
 512         outl(val, uhci->io_addr + reg);
 513 }
 514
 515 static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg)
 516 {
 517         return inw(uhci->io_addr + reg);
 518 }
 519
 520 static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg)
 521 {
 522         outw(val, uhci->io_addr + reg);
 523 }
 524
 525 static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg)
 526 {
 527         return inb(uhci->io_addr + reg);
 528 }
 529
 530 static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg)
 531 {
 532         outb(val, uhci->io_addr + reg);
 533 }
 534
 535 #else
 536 /* Support non-PCI host controllers */
 537 #ifdef CONFIG_PCI
 538 /* Support PCI and non-PCI host controllers */
 539 #define uhci_has_pci_registers(u)       ((u)->io_addr != 0)
 540 #else
 541 /* Support non-PCI host controllers only */
 542 #define uhci_has_pci_registers(u)       0
 543 #endif
 544
 545 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
 546 /* Support (non-PCI) big endian host controllers */
 547 #define uhci_big_endian_mmio(u)         ((u)->big_endian_mmio)
 548 #else
 549 #define uhci_big_endian_mmio(u)         0
 550 #endif
 551
 552 static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg)
 553 {
 554         if (uhci_has_pci_registers(uhci))
 555                 return inl(uhci->io_addr + reg);
 556 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
 557         else if (uhci_big_endian_mmio(uhci))
 558                 return readl_be(uhci->regs + reg);
 559 #endif
 560         else
 561                 return readl(uhci->regs + reg);
 562 }
 563
 564 static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg)
 565 {
 566         if (uhci_has_pci_registers(uhci))
 567                 outl(val, uhci->io_addr + reg);
 568 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
 569         else if (uhci_big_endian_mmio(uhci))
 570                 writel_be(val, uhci->regs + reg);
 571 #endif
 572         else
 573                 writel(val, uhci->regs + reg);
 574 }
 575
 576 static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg)
 577 {
 578         if (uhci_has_pci_registers(uhci))
 579                 return inw(uhci->io_addr + reg);
 580 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
 581         else if (uhci_big_endian_mmio(uhci))
 582                 return readw_be(uhci->regs + reg);
 583 #endif
 584         else
 585                 return readw(uhci->regs + reg);
 586 }
 587
 588 static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg)
 589 {
 590         if (uhci_has_pci_registers(uhci))
 591                 outw(val, uhci->io_addr + reg);
 592 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
 593         else if (uhci_big_endian_mmio(uhci))
 594                 writew_be(val, uhci->regs + reg);
 595 #endif
 596         else
 597                 writew(val, uhci->regs + reg);
 598 }
 599
 600 static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg)
 601 {
 602         if (uhci_has_pci_registers(uhci))
 603                 return inb(uhci->io_addr + reg);
 604 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
 605         else if (uhci_big_endian_mmio(uhci))
 606                 return readb_be(uhci->regs + reg);
 607 #endif
 608         else
 609                 return readb(uhci->regs + reg);
 610 }
 611
 612 static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg)
 613 {
 614         if (uhci_has_pci_registers(uhci))
 615                 outb(val, uhci->io_addr + reg);
 616 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
 617         else if (uhci_big_endian_mmio(uhci))
 618                 writeb_be(val, uhci->regs + reg);
 619 #endif
 620         else
 621                 writeb(val, uhci->regs + reg);
 622 }
 623 #endif /* CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC */
 624
 625 /*
 626  * The GRLIB GRUSBHC controller can use big endian format for its descriptors.
 627  *
 628  * UHCI controllers accessed through PCI work normally (little-endian
 629  * everywhere), so we don't bother supporting a BE-only mode.
 630  */
 631 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_DESC
 632 #define uhci_big_endian_desc(u)         ((u)->big_endian_desc)
 633
 634 /* cpu to uhci */
 635 static inline __hc32 cpu_to_hc32(const struct uhci_hcd *uhci, const u32 x)
 636 {
 637         return uhci_big_endian_desc(uhci)
 638                 ? (__force __hc32)cpu_to_be32(x)
 639                 : (__force __hc32)cpu_to_le32(x);
 640 }
 641
 642 /* uhci to cpu */
 643 static inline u32 hc32_to_cpu(const struct uhci_hcd *uhci, const __hc32 x)
 644 {
 645         return uhci_big_endian_desc(uhci)
 646                 ? be32_to_cpu((__force __be32)x)
 647                 : le32_to_cpu((__force __le32)x);
 648 }
 649
 650 #else
 651 /* cpu to uhci */
 652 static inline __hc32 cpu_to_hc32(const struct uhci_hcd *uhci, const u32 x)
 653 {
 654         return cpu_to_le32(x);
 655 }
 656
 657 /* uhci to cpu */
 658 static inline u32 hc32_to_cpu(const struct uhci_hcd *uhci, const __hc32 x)
 659 {
 660         return le32_to_cpu(x);
 661 }
 662 #endif
 663
 664 #endif