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USB: convert sound/* to use module_usb_driver()
[zen-stable.git] / drivers / media / video / cx25840 / cx25840-core.c
blobcd9976408ab33050498633ee5c8c3e87a8d2f24c
1 /* cx25840 - Conexant CX25840 audio/video decoder driver
2 *
3 * Copyright (C) 2004 Ulf Eklund
4 *
5 * Based on the saa7115 driver and on the first version of Chris Kennedy's
6 * cx25840 driver.
7 *
8 * Changes by Tyler Trafford <tatrafford@comcast.net>
9 * - cleanup/rewrite for V4L2 API (2005)
10 *
11 * VBI support by Hans Verkuil <hverkuil@xs4all.nl>.
12 *
13 * NTSC sliced VBI support by Christopher Neufeld <television@cneufeld.ca>
14 * with additional fixes by Hans Verkuil <hverkuil@xs4all.nl>.
15 *
16 * CX23885 support by Steven Toth <stoth@linuxtv.org>.
17 *
18 * CX2388[578] IRQ handling, IO Pin mux configuration and other small fixes are
19 * Copyright (C) 2010 Andy Walls <awalls@md.metrocast.net>
20 *
21 * This program is free software; you can redistribute it and/or
22 * modify it under the terms of the GNU General Public License
23 * as published by the Free Software Foundation; either version 2
24 * of the License, or (at your option) any later version.
25 *
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
30 *
31 * You should have received a copy of the GNU General Public License
32 * along with this program; if not, write to the Free Software
33 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
34 */
35
36
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/slab.h>
40 #include <linux/videodev2.h>
41 #include <linux/i2c.h>
42 #include <linux/delay.h>
43 #include <media/v4l2-common.h>
44 #include <media/v4l2-chip-ident.h>
45 #include <media/cx25840.h>
46
47 #include "cx25840-core.h"
48
49 MODULE_DESCRIPTION("Conexant CX25840 audio/video decoder driver");
50 MODULE_AUTHOR("Ulf Eklund, Chris Kennedy, Hans Verkuil, Tyler Trafford");
51 MODULE_LICENSE("GPL");
52
53 #define CX25840_VID_INT_STAT_REG 0x410
54 #define CX25840_VID_INT_STAT_BITS 0x0000ffff
55 #define CX25840_VID_INT_MASK_BITS 0xffff0000
56 #define CX25840_VID_INT_MASK_SHFT 16
57 #define CX25840_VID_INT_MASK_REG 0x412
58
59 #define CX23885_AUD_MC_INT_MASK_REG 0x80c
60 #define CX23885_AUD_MC_INT_STAT_BITS 0xffff0000
61 #define CX23885_AUD_MC_INT_CTRL_BITS 0x0000ffff
62 #define CX23885_AUD_MC_INT_STAT_SHFT 16
63
64 #define CX25840_AUD_INT_CTRL_REG 0x812
65 #define CX25840_AUD_INT_STAT_REG 0x813
66
67 #define CX23885_PIN_CTRL_IRQ_REG 0x123
68 #define CX23885_PIN_CTRL_IRQ_IR_STAT 0x40
69 #define CX23885_PIN_CTRL_IRQ_AUD_STAT 0x20
70 #define CX23885_PIN_CTRL_IRQ_VID_STAT 0x10
71
72 #define CX25840_IR_STATS_REG 0x210
73 #define CX25840_IR_IRQEN_REG 0x214
74
75 static int cx25840_debug;
76
77 module_param_named(debug,cx25840_debug, int, 0644);
78
79 MODULE_PARM_DESC(debug, "Debugging messages [0=Off (default) 1=On]");
80
81
82 /* ----------------------------------------------------------------------- */
83
84 int cx25840_write(struct i2c_client *client, u16 addr, u8 value)
85 {
86 u8 buffer[3];
87 buffer[0] = addr >> 8;
88 buffer[1] = addr & 0xff;
89 buffer[2] = value;
90 return i2c_master_send(client, buffer, 3);
91 }
92
93 int cx25840_write4(struct i2c_client *client, u16 addr, u32 value)
94 {
95 u8 buffer[6];
96 buffer[0] = addr >> 8;
97 buffer[1] = addr & 0xff;
98 buffer[2] = value & 0xff;
99 buffer[3] = (value >> 8) & 0xff;
100 buffer[4] = (value >> 16) & 0xff;
101 buffer[5] = value >> 24;
102 return i2c_master_send(client, buffer, 6);
103 }
104
105 u8 cx25840_read(struct i2c_client * client, u16 addr)
106 {
107 struct i2c_msg msgs[2];
108 u8 tx_buf[2], rx_buf[1];
109
110 /* Write register address */
111 tx_buf[0] = addr >> 8;
112 tx_buf[1] = addr & 0xff;
113 msgs[0].addr = client->addr;
114 msgs[0].flags = 0;
115 msgs[0].len = 2;
116 msgs[0].buf = (char *) tx_buf;
117
118 /* Read data from register */
119 msgs[1].addr = client->addr;
120 msgs[1].flags = I2C_M_RD;
121 msgs[1].len = 1;
122 msgs[1].buf = (char *) rx_buf;
123
124 if (i2c_transfer(client->adapter, msgs, 2) < 2)
125 return 0;
126
127 return rx_buf[0];
128 }
129
130 u32 cx25840_read4(struct i2c_client * client, u16 addr)
131 {
132 struct i2c_msg msgs[2];
133 u8 tx_buf[2], rx_buf[4];
134
135 /* Write register address */
136 tx_buf[0] = addr >> 8;
137 tx_buf[1] = addr & 0xff;
138 msgs[0].addr = client->addr;
139 msgs[0].flags = 0;
140 msgs[0].len = 2;
141 msgs[0].buf = (char *) tx_buf;
142
143 /* Read data from registers */
144 msgs[1].addr = client->addr;
145 msgs[1].flags = I2C_M_RD;
146 msgs[1].len = 4;
147 msgs[1].buf = (char *) rx_buf;
148
149 if (i2c_transfer(client->adapter, msgs, 2) < 2)
150 return 0;
151
152 return (rx_buf[3] << 24) | (rx_buf[2] << 16) | (rx_buf[1] << 8) |
153 rx_buf[0];
154 }
155
156 int cx25840_and_or(struct i2c_client *client, u16 addr, unsigned and_mask,
157 u8 or_value)
158 {
159 return cx25840_write(client, addr,
160 (cx25840_read(client, addr) & and_mask) |
161 or_value);
162 }
163
164 int cx25840_and_or4(struct i2c_client *client, u16 addr, u32 and_mask,
165 u32 or_value)
166 {
167 return cx25840_write4(client, addr,
168 (cx25840_read4(client, addr) & and_mask) |
169 or_value);
170 }
171
172 /* ----------------------------------------------------------------------- */
173
174 static int set_input(struct i2c_client *client, enum cx25840_video_input vid_input,
175 enum cx25840_audio_input aud_input);
176
177 /* ----------------------------------------------------------------------- */
178
179 static int cx23885_s_io_pin_config(struct v4l2_subdev *sd, size_t n,
180 struct v4l2_subdev_io_pin_config *p)
181 {
182 struct i2c_client *client = v4l2_get_subdevdata(sd);
183 int i;
184 u32 pin_ctrl;
185 u8 gpio_oe, gpio_data, strength;
186
187 pin_ctrl = cx25840_read4(client, 0x120);
188 gpio_oe = cx25840_read(client, 0x160);
189 gpio_data = cx25840_read(client, 0x164);
190
191 for (i = 0; i < n; i++) {
192 strength = p[i].strength;
193 if (strength > CX25840_PIN_DRIVE_FAST)
194 strength = CX25840_PIN_DRIVE_FAST;
195
196 switch (p[i].pin) {
197 case CX23885_PIN_IRQ_N_GPIO16:
198 if (p[i].function != CX23885_PAD_IRQ_N) {
199 /* GPIO16 */
200 pin_ctrl &= ~(0x1 << 25);
201 } else {
202 /* IRQ_N */
203 if (p[i].flags &
204 (V4L2_SUBDEV_IO_PIN_DISABLE |
205 V4L2_SUBDEV_IO_PIN_INPUT)) {
206 pin_ctrl &= ~(0x1 << 25);
207 } else {
208 pin_ctrl |= (0x1 << 25);
209 }
210 if (p[i].flags &
211 V4L2_SUBDEV_IO_PIN_ACTIVE_LOW) {
212 pin_ctrl &= ~(0x1 << 24);
213 } else {
214 pin_ctrl |= (0x1 << 24);
215 }
216 }
217 break;
218 case CX23885_PIN_IR_RX_GPIO19:
219 if (p[i].function != CX23885_PAD_GPIO19) {
220 /* IR_RX */
221 gpio_oe |= (0x1 << 0);
222 pin_ctrl &= ~(0x3 << 18);
223 pin_ctrl |= (strength << 18);
224 } else {
225 /* GPIO19 */
226 gpio_oe &= ~(0x1 << 0);
227 if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
228 gpio_data &= ~(0x1 << 0);
229 gpio_data |= ((p[i].value & 0x1) << 0);
230 }
231 pin_ctrl &= ~(0x3 << 12);
232 pin_ctrl |= (strength << 12);
233 }
234 break;
235 case CX23885_PIN_IR_TX_GPIO20:
236 if (p[i].function != CX23885_PAD_GPIO20) {
237 /* IR_TX */
238 gpio_oe |= (0x1 << 1);
239 if (p[i].flags & V4L2_SUBDEV_IO_PIN_DISABLE)
240 pin_ctrl &= ~(0x1 << 10);
241 else
242 pin_ctrl |= (0x1 << 10);
243 pin_ctrl &= ~(0x3 << 18);
244 pin_ctrl |= (strength << 18);
245 } else {
246 /* GPIO20 */
247 gpio_oe &= ~(0x1 << 1);
248 if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
249 gpio_data &= ~(0x1 << 1);
250 gpio_data |= ((p[i].value & 0x1) << 1);
251 }
252 pin_ctrl &= ~(0x3 << 12);
253 pin_ctrl |= (strength << 12);
254 }
255 break;
256 case CX23885_PIN_I2S_SDAT_GPIO21:
257 if (p[i].function != CX23885_PAD_GPIO21) {
258 /* I2S_SDAT */
259 /* TODO: Input or Output config */
260 gpio_oe |= (0x1 << 2);
261 pin_ctrl &= ~(0x3 << 22);
262 pin_ctrl |= (strength << 22);
263 } else {
264 /* GPIO21 */
265 gpio_oe &= ~(0x1 << 2);
266 if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
267 gpio_data &= ~(0x1 << 2);
268 gpio_data |= ((p[i].value & 0x1) << 2);
269 }
270 pin_ctrl &= ~(0x3 << 12);
271 pin_ctrl |= (strength << 12);
272 }
273 break;
274 case CX23885_PIN_I2S_WCLK_GPIO22:
275 if (p[i].function != CX23885_PAD_GPIO22) {
276 /* I2S_WCLK */
277 /* TODO: Input or Output config */
278 gpio_oe |= (0x1 << 3);
279 pin_ctrl &= ~(0x3 << 22);
280 pin_ctrl |= (strength << 22);
281 } else {
282 /* GPIO22 */
283 gpio_oe &= ~(0x1 << 3);
284 if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
285 gpio_data &= ~(0x1 << 3);
286 gpio_data |= ((p[i].value & 0x1) << 3);
287 }
288 pin_ctrl &= ~(0x3 << 12);
289 pin_ctrl |= (strength << 12);
290 }
291 break;
292 case CX23885_PIN_I2S_BCLK_GPIO23:
293 if (p[i].function != CX23885_PAD_GPIO23) {
294 /* I2S_BCLK */
295 /* TODO: Input or Output config */
296 gpio_oe |= (0x1 << 4);
297 pin_ctrl &= ~(0x3 << 22);
298 pin_ctrl |= (strength << 22);
299 } else {
300 /* GPIO23 */
301 gpio_oe &= ~(0x1 << 4);
302 if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
303 gpio_data &= ~(0x1 << 4);
304 gpio_data |= ((p[i].value & 0x1) << 4);
305 }
306 pin_ctrl &= ~(0x3 << 12);
307 pin_ctrl |= (strength << 12);
308 }
309 break;
310 }
311 }
312
313 cx25840_write(client, 0x164, gpio_data);
314 cx25840_write(client, 0x160, gpio_oe);
315 cx25840_write4(client, 0x120, pin_ctrl);
316 return 0;
317 }
318
319 static int common_s_io_pin_config(struct v4l2_subdev *sd, size_t n,
320 struct v4l2_subdev_io_pin_config *pincfg)
321 {
322 struct cx25840_state *state = to_state(sd);
323
324 if (is_cx2388x(state))
325 return cx23885_s_io_pin_config(sd, n, pincfg);
326 return 0;
327 }
328
329 /* ----------------------------------------------------------------------- */
330
331 static void init_dll1(struct i2c_client *client)
332 {
333 /* This is the Hauppauge sequence used to
334 * initialize the Delay Lock Loop 1 (ADC DLL). */
335 cx25840_write(client, 0x159, 0x23);
336 cx25840_write(client, 0x15a, 0x87);
337 cx25840_write(client, 0x15b, 0x06);
338 udelay(10);
339 cx25840_write(client, 0x159, 0xe1);
340 udelay(10);
341 cx25840_write(client, 0x15a, 0x86);
342 cx25840_write(client, 0x159, 0xe0);
343 cx25840_write(client, 0x159, 0xe1);
344 cx25840_write(client, 0x15b, 0x10);
345 }
346
347 static void init_dll2(struct i2c_client *client)
348 {
349 /* This is the Hauppauge sequence used to
350 * initialize the Delay Lock Loop 2 (ADC DLL). */
351 cx25840_write(client, 0x15d, 0xe3);
352 cx25840_write(client, 0x15e, 0x86);
353 cx25840_write(client, 0x15f, 0x06);
354 udelay(10);
355 cx25840_write(client, 0x15d, 0xe1);
356 cx25840_write(client, 0x15d, 0xe0);
357 cx25840_write(client, 0x15d, 0xe1);
358 }
359
360 static void cx25836_initialize(struct i2c_client *client)
361 {
362 /* reset configuration is described on page 3-77 of the CX25836 datasheet */
363 /* 2. */
364 cx25840_and_or(client, 0x000, ~0x01, 0x01);
365 cx25840_and_or(client, 0x000, ~0x01, 0x00);
366 /* 3a. */
367 cx25840_and_or(client, 0x15a, ~0x70, 0x00);
368 /* 3b. */
369 cx25840_and_or(client, 0x15b, ~0x1e, 0x06);
370 /* 3c. */
371 cx25840_and_or(client, 0x159, ~0x02, 0x02);
372 /* 3d. */
373 udelay(10);
374 /* 3e. */
375 cx25840_and_or(client, 0x159, ~0x02, 0x00);
376 /* 3f. */
377 cx25840_and_or(client, 0x159, ~0xc0, 0xc0);
378 /* 3g. */
379 cx25840_and_or(client, 0x159, ~0x01, 0x00);
380 cx25840_and_or(client, 0x159, ~0x01, 0x01);
381 /* 3h. */
382 cx25840_and_or(client, 0x15b, ~0x1e, 0x10);
383 }
384
385 static void cx25840_work_handler(struct work_struct *work)
386 {
387 struct cx25840_state *state = container_of(work, struct cx25840_state, fw_work);
388 cx25840_loadfw(state->c);
389 wake_up(&state->fw_wait);
390 }
391
392 static void cx25840_initialize(struct i2c_client *client)
393 {
394 DEFINE_WAIT(wait);
395 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
396 struct workqueue_struct *q;
397
398 /* datasheet startup in numbered steps, refer to page 3-77 */
399 /* 2. */
400 cx25840_and_or(client, 0x803, ~0x10, 0x00);
401 /* The default of this register should be 4, but I get 0 instead.
402 * Set this register to 4 manually. */
403 cx25840_write(client, 0x000, 0x04);
404 /* 3. */
405 init_dll1(client);
406 init_dll2(client);
407 cx25840_write(client, 0x136, 0x0a);
408 /* 4. */
409 cx25840_write(client, 0x13c, 0x01);
410 cx25840_write(client, 0x13c, 0x00);
411 /* 5. */
412 /* Do the firmware load in a work handler to prevent.
413 Otherwise the kernel is blocked waiting for the
414 bit-banging i2c interface to finish uploading the
415 firmware. */
416 INIT_WORK(&state->fw_work, cx25840_work_handler);
417 init_waitqueue_head(&state->fw_wait);
418 q = create_singlethread_workqueue("cx25840_fw");
419 prepare_to_wait(&state->fw_wait, &wait, TASK_UNINTERRUPTIBLE);
420 queue_work(q, &state->fw_work);
421 schedule();
422 finish_wait(&state->fw_wait, &wait);
423 destroy_workqueue(q);
424
425 /* 6. */
426 cx25840_write(client, 0x115, 0x8c);
427 cx25840_write(client, 0x116, 0x07);
428 cx25840_write(client, 0x118, 0x02);
429 /* 7. */
430 cx25840_write(client, 0x4a5, 0x80);
431 cx25840_write(client, 0x4a5, 0x00);
432 cx25840_write(client, 0x402, 0x00);
433 /* 8. */
434 cx25840_and_or(client, 0x401, ~0x18, 0);
435 cx25840_and_or(client, 0x4a2, ~0x10, 0x10);
436 /* steps 8c and 8d are done in change_input() */
437 /* 10. */
438 cx25840_write(client, 0x8d3, 0x1f);
439 cx25840_write(client, 0x8e3, 0x03);
440
441 cx25840_std_setup(client);
442
443 /* trial and error says these are needed to get audio */
444 cx25840_write(client, 0x914, 0xa0);
445 cx25840_write(client, 0x918, 0xa0);
446 cx25840_write(client, 0x919, 0x01);
447
448 /* stereo preferred */
449 cx25840_write(client, 0x809, 0x04);
450 /* AC97 shift */
451 cx25840_write(client, 0x8cf, 0x0f);
452
453 /* (re)set input */
454 set_input(client, state->vid_input, state->aud_input);
455
456 /* start microcontroller */
457 cx25840_and_or(client, 0x803, ~0x10, 0x10);
458 }
459
460 static void cx23885_initialize(struct i2c_client *client)
461 {
462 DEFINE_WAIT(wait);
463 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
464 struct workqueue_struct *q;
465
466 /*
467 * Come out of digital power down
468 * The CX23888, at least, needs this, otherwise registers aside from
469 * 0x0-0x2 can't be read or written.
470 */
471 cx25840_write(client, 0x000, 0);
472
473 /* Internal Reset */
474 cx25840_and_or(client, 0x102, ~0x01, 0x01);
475 cx25840_and_or(client, 0x102, ~0x01, 0x00);
476
477 /* Stop microcontroller */
478 cx25840_and_or(client, 0x803, ~0x10, 0x00);
479
480 /* DIF in reset? */
481 cx25840_write(client, 0x398, 0);
482
483 /*
484 * Trust the default xtal, no division
485 * '885: 28.636363... MHz
486 * '887: 25.000000 MHz
487 * '888: 50.000000 MHz
488 */
489 cx25840_write(client, 0x2, 0x76);
490
491 /* Power up all the PLL's and DLL */
492 cx25840_write(client, 0x1, 0x40);
493
494 /* Sys PLL */
495 switch (state->id) {
496 case V4L2_IDENT_CX23888_AV:
497 /*
498 * 50.0 MHz * (0xb + 0xe8ba26/0x2000000)/4 = 5 * 28.636363 MHz
499 * 572.73 MHz before post divide
500 */
501 cx25840_write4(client, 0x11c, 0x00e8ba26);
502 cx25840_write4(client, 0x118, 0x0000040b);
503 break;
504 case V4L2_IDENT_CX23887_AV:
505 /*
506 * 25.0 MHz * (0x16 + 0x1d1744c/0x2000000)/4 = 5 * 28.636363 MHz
507 * 572.73 MHz before post divide
508 */
509 cx25840_write4(client, 0x11c, 0x01d1744c);
510 cx25840_write4(client, 0x118, 0x00000416);
511 break;
512 case V4L2_IDENT_CX23885_AV:
513 default:
514 /*
515 * 28.636363 MHz * (0x14 + 0x0/0x2000000)/4 = 5 * 28.636363 MHz
516 * 572.73 MHz before post divide
517 */
518 cx25840_write4(client, 0x11c, 0x00000000);
519 cx25840_write4(client, 0x118, 0x00000414);
520 break;
521 }
522
523 /* Disable DIF bypass */
524 cx25840_write4(client, 0x33c, 0x00000001);
525
526 /* DIF Src phase inc */
527 cx25840_write4(client, 0x340, 0x0df7df83);
528
529 /*
530 * Vid PLL
531 * Setup for a BT.656 pixel clock of 13.5 Mpixels/second
532 *
533 * 28.636363 MHz * (0xf + 0x02be2c9/0x2000000)/4 = 8 * 13.5 MHz
534 * 432.0 MHz before post divide
535 */
536 cx25840_write4(client, 0x10c, 0x002be2c9);
537 cx25840_write4(client, 0x108, 0x0000040f);
538
539 /* Luma */
540 cx25840_write4(client, 0x414, 0x00107d12);
541
542 /* Chroma */
543 cx25840_write4(client, 0x420, 0x3d008282);
544
545 /*
546 * Aux PLL
547 * Initial setup for audio sample clock:
548 * 48 ksps, 16 bits/sample, x160 multiplier = 122.88 MHz
549 * Initial I2S output/master clock(?):
550 * 48 ksps, 16 bits/sample, x16 multiplier = 12.288 MHz
551 */
552 switch (state->id) {
553 case V4L2_IDENT_CX23888_AV:
554 /*
555 * 50.0 MHz * (0x7 + 0x0bedfa4/0x2000000)/3 = 122.88 MHz
556 * 368.64 MHz before post divide
557 * 122.88 MHz / 0xa = 12.288 MHz
558 */
559 cx25840_write4(client, 0x114, 0x00bedfa4);
560 cx25840_write4(client, 0x110, 0x000a0307);
561 break;
562 case V4L2_IDENT_CX23887_AV:
563 /*
564 * 25.0 MHz * (0xe + 0x17dbf48/0x2000000)/3 = 122.88 MHz
565 * 368.64 MHz before post divide
566 * 122.88 MHz / 0xa = 12.288 MHz
567 */
568 cx25840_write4(client, 0x114, 0x017dbf48);
569 cx25840_write4(client, 0x110, 0x000a030e);
570 break;
571 case V4L2_IDENT_CX23885_AV:
572 default:
573 /*
574 * 28.636363 MHz * (0xc + 0x1bf0c9e/0x2000000)/3 = 122.88 MHz
575 * 368.64 MHz before post divide
576 * 122.88 MHz / 0xa = 12.288 MHz
577 */
578 cx25840_write4(client, 0x114, 0x01bf0c9e);
579 cx25840_write4(client, 0x110, 0x000a030c);
580 break;
581 };
582
583 /* ADC2 input select */
584 cx25840_write(client, 0x102, 0x10);
585
586 /* VIN1 & VIN5 */
587 cx25840_write(client, 0x103, 0x11);
588
589 /* Enable format auto detect */
590 cx25840_write(client, 0x400, 0);
591 /* Fast subchroma lock */
592 /* White crush, Chroma AGC & Chroma Killer enabled */
593 cx25840_write(client, 0x401, 0xe8);
594
595 /* Select AFE clock pad output source */
596 cx25840_write(client, 0x144, 0x05);
597
598 /* Drive GPIO2 direction and values for HVR1700
599 * where an onboard mux selects the output of demodulator
600 * vs the 417. Failure to set this results in no DTV.
601 * It's safe to set this across all Hauppauge boards
602 * currently, regardless of the board type.
603 */
604 cx25840_write(client, 0x160, 0x1d);
605 cx25840_write(client, 0x164, 0x00);
606
607 /* Do the firmware load in a work handler to prevent.
608 Otherwise the kernel is blocked waiting for the
609 bit-banging i2c interface to finish uploading the
610 firmware. */
611 INIT_WORK(&state->fw_work, cx25840_work_handler);
612 init_waitqueue_head(&state->fw_wait);
613 q = create_singlethread_workqueue("cx25840_fw");
614 prepare_to_wait(&state->fw_wait, &wait, TASK_UNINTERRUPTIBLE);
615 queue_work(q, &state->fw_work);
616 schedule();
617 finish_wait(&state->fw_wait, &wait);
618 destroy_workqueue(q);
619
620 cx25840_std_setup(client);
621
622 /* (re)set input */
623 set_input(client, state->vid_input, state->aud_input);
624
625 /* start microcontroller */
626 cx25840_and_or(client, 0x803, ~0x10, 0x10);
627
628 /* Disable and clear video interrupts - we don't use them */
629 cx25840_write4(client, CX25840_VID_INT_STAT_REG, 0xffffffff);
630
631 /* Disable and clear audio interrupts - we don't use them */
632 cx25840_write(client, CX25840_AUD_INT_CTRL_REG, 0xff);
633 cx25840_write(client, CX25840_AUD_INT_STAT_REG, 0xff);
634 }
635
636 /* ----------------------------------------------------------------------- */
637
638 static void cx231xx_initialize(struct i2c_client *client)
639 {
640 DEFINE_WAIT(wait);
641 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
642 struct workqueue_struct *q;
643
644 /* Internal Reset */
645 cx25840_and_or(client, 0x102, ~0x01, 0x01);
646 cx25840_and_or(client, 0x102, ~0x01, 0x00);
647
648 /* Stop microcontroller */
649 cx25840_and_or(client, 0x803, ~0x10, 0x00);
650
651 /* DIF in reset? */
652 cx25840_write(client, 0x398, 0);
653
654 /* Trust the default xtal, no division */
655 /* This changes for the cx23888 products */
656 cx25840_write(client, 0x2, 0x76);
657
658 /* Bring down the regulator for AUX clk */
659 cx25840_write(client, 0x1, 0x40);
660
661 /* Disable DIF bypass */
662 cx25840_write4(client, 0x33c, 0x00000001);
663
664 /* DIF Src phase inc */
665 cx25840_write4(client, 0x340, 0x0df7df83);
666
667 /* Luma */
668 cx25840_write4(client, 0x414, 0x00107d12);
669
670 /* Chroma */
671 cx25840_write4(client, 0x420, 0x3d008282);
672
673 /* ADC2 input select */
674 cx25840_write(client, 0x102, 0x10);
675
676 /* VIN1 & VIN5 */
677 cx25840_write(client, 0x103, 0x11);
678
679 /* Enable format auto detect */
680 cx25840_write(client, 0x400, 0);
681 /* Fast subchroma lock */
682 /* White crush, Chroma AGC & Chroma Killer enabled */
683 cx25840_write(client, 0x401, 0xe8);
684
685 /* Do the firmware load in a work handler to prevent.
686 Otherwise the kernel is blocked waiting for the
687 bit-banging i2c interface to finish uploading the
688 firmware. */
689 INIT_WORK(&state->fw_work, cx25840_work_handler);
690 init_waitqueue_head(&state->fw_wait);
691 q = create_singlethread_workqueue("cx25840_fw");
692 prepare_to_wait(&state->fw_wait, &wait, TASK_UNINTERRUPTIBLE);
693 queue_work(q, &state->fw_work);
694 schedule();
695 finish_wait(&state->fw_wait, &wait);
696 destroy_workqueue(q);
697
698 cx25840_std_setup(client);
699
700 /* (re)set input */
701 set_input(client, state->vid_input, state->aud_input);
702
703 /* start microcontroller */
704 cx25840_and_or(client, 0x803, ~0x10, 0x10);
705
706 /* CC raw enable */
707 cx25840_write(client, 0x404, 0x0b);
708
709 /* CC on */
710 cx25840_write(client, 0x42f, 0x66);
711 cx25840_write4(client, 0x474, 0x1e1e601a);
712 }
713
714 /* ----------------------------------------------------------------------- */
715
716 void cx25840_std_setup(struct i2c_client *client)
717 {
718 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
719 v4l2_std_id std = state->std;
720 int hblank, hactive, burst, vblank, vactive, sc;
721 int vblank656, src_decimation;
722 int luma_lpf, uv_lpf, comb;
723 u32 pll_int, pll_frac, pll_post;
724
725 /* datasheet startup, step 8d */
726 if (std & ~V4L2_STD_NTSC)
727 cx25840_write(client, 0x49f, 0x11);
728 else
729 cx25840_write(client, 0x49f, 0x14);
730
731 if (std & V4L2_STD_625_50) {
732 hblank = 132;
733 hactive = 720;
734 burst = 93;
735 vblank = 36;
736 vactive = 580;
737 vblank656 = 40;
738 src_decimation = 0x21f;
739 luma_lpf = 2;
740
741 if (std & V4L2_STD_SECAM) {
742 uv_lpf = 0;
743 comb = 0;
744 sc = 0x0a425f;
745 } else if (std == V4L2_STD_PAL_Nc) {
746 uv_lpf = 1;
747 comb = 0x20;
748 sc = 556453;
749 } else {
750 uv_lpf = 1;
751 comb = 0x20;
752 sc = 688739;
753 }
754 } else {
755 hactive = 720;
756 hblank = 122;
757 vactive = 487;
758 luma_lpf = 1;
759 uv_lpf = 1;
760
761 src_decimation = 0x21f;
762 if (std == V4L2_STD_PAL_60) {
763 vblank = 26;
764 vblank656 = 26;
765 burst = 0x5b;
766 luma_lpf = 2;
767 comb = 0x20;
768 sc = 688739;
769 } else if (std == V4L2_STD_PAL_M) {
770 vblank = 20;
771 vblank656 = 24;
772 burst = 0x61;
773 comb = 0x20;
774 sc = 555452;
775 } else {
776 vblank = 26;
777 vblank656 = 26;
778 burst = 0x5b;
779 comb = 0x66;
780 sc = 556063;
781 }
782 }
783
784 /* DEBUG: Displays configured PLL frequency */
785 if (!is_cx231xx(state)) {
786 pll_int = cx25840_read(client, 0x108);
787 pll_frac = cx25840_read4(client, 0x10c) & 0x1ffffff;
788 pll_post = cx25840_read(client, 0x109);
789 v4l_dbg(1, cx25840_debug, client,
790 "PLL regs = int: %u, frac: %u, post: %u\n",
791 pll_int, pll_frac, pll_post);
792
793 if (pll_post) {
794 int fin, fsc;
795 int pll = (28636363L * ((((u64)pll_int) << 25L) + pll_frac)) >> 25L;
796
797 pll /= pll_post;
798 v4l_dbg(1, cx25840_debug, client, "PLL = %d.%06d MHz\n",
799 pll / 1000000, pll % 1000000);
800 v4l_dbg(1, cx25840_debug, client, "PLL/8 = %d.%06d MHz\n",
801 pll / 8000000, (pll / 8) % 1000000);
802
803 fin = ((u64)src_decimation * pll) >> 12;
804 v4l_dbg(1, cx25840_debug, client,
805 "ADC Sampling freq = %d.%06d MHz\n",
806 fin / 1000000, fin % 1000000);
807
808 fsc = (((u64)sc) * pll) >> 24L;
809 v4l_dbg(1, cx25840_debug, client,
810 "Chroma sub-carrier freq = %d.%06d MHz\n",
811 fsc / 1000000, fsc % 1000000);
812
813 v4l_dbg(1, cx25840_debug, client, "hblank %i, hactive %i, "
814 "vblank %i, vactive %i, vblank656 %i, src_dec %i, "
815 "burst 0x%02x, luma_lpf %i, uv_lpf %i, comb 0x%02x, "
816 "sc 0x%06x\n",
817 hblank, hactive, vblank, vactive, vblank656,
818 src_decimation, burst, luma_lpf, uv_lpf, comb, sc);
819 }
820 }
821
822 /* Sets horizontal blanking delay and active lines */
823 cx25840_write(client, 0x470, hblank);
824 cx25840_write(client, 0x471,
825 0xff & (((hblank >> 8) & 0x3) | (hactive << 4)));
826 cx25840_write(client, 0x472, hactive >> 4);
827
828 /* Sets burst gate delay */
829 cx25840_write(client, 0x473, burst);
830
831 /* Sets vertical blanking delay and active duration */
832 cx25840_write(client, 0x474, vblank);
833 cx25840_write(client, 0x475,
834 0xff & (((vblank >> 8) & 0x3) | (vactive << 4)));
835 cx25840_write(client, 0x476, vactive >> 4);
836 cx25840_write(client, 0x477, vblank656);
837
838 /* Sets src decimation rate */
839 cx25840_write(client, 0x478, 0xff & src_decimation);
840 cx25840_write(client, 0x479, 0xff & (src_decimation >> 8));
841
842 /* Sets Luma and UV Low pass filters */
843 cx25840_write(client, 0x47a, luma_lpf << 6 | ((uv_lpf << 4) & 0x30));
844
845 /* Enables comb filters */
846 cx25840_write(client, 0x47b, comb);
847
848 /* Sets SC Step*/
849 cx25840_write(client, 0x47c, sc);
850 cx25840_write(client, 0x47d, 0xff & sc >> 8);
851 cx25840_write(client, 0x47e, 0xff & sc >> 16);
852
853 /* Sets VBI parameters */
854 if (std & V4L2_STD_625_50) {
855 cx25840_write(client, 0x47f, 0x01);
856 state->vbi_line_offset = 5;
857 } else {
858 cx25840_write(client, 0x47f, 0x00);
859 state->vbi_line_offset = 8;
860 }
861 }
862
863 /* ----------------------------------------------------------------------- */
864
865 static void input_change(struct i2c_client *client)
866 {
867 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
868 v4l2_std_id std = state->std;
869
870 /* Follow step 8c and 8d of section 3.16 in the cx25840 datasheet */
871 if (std & V4L2_STD_SECAM) {
872 cx25840_write(client, 0x402, 0);
873 }
874 else {
875 cx25840_write(client, 0x402, 0x04);
876 cx25840_write(client, 0x49f, (std & V4L2_STD_NTSC) ? 0x14 : 0x11);
877 }
878 cx25840_and_or(client, 0x401, ~0x60, 0);
879 cx25840_and_or(client, 0x401, ~0x60, 0x60);
880
881 /* Don't write into audio registers on cx2583x chips */
882 if (is_cx2583x(state))
883 return;
884
885 cx25840_and_or(client, 0x810, ~0x01, 1);
886
887 if (state->radio) {
888 cx25840_write(client, 0x808, 0xf9);
889 cx25840_write(client, 0x80b, 0x00);
890 }
891 else if (std & V4L2_STD_525_60) {
892 /* Certain Hauppauge PVR150 models have a hardware bug
893 that causes audio to drop out. For these models the
894 audio standard must be set explicitly.
895 To be precise: it affects cards with tuner models
896 85, 99 and 112 (model numbers from tveeprom). */
897 int hw_fix = state->pvr150_workaround;
898
899 if (std == V4L2_STD_NTSC_M_JP) {
900 /* Japan uses EIAJ audio standard */
901 cx25840_write(client, 0x808, hw_fix ? 0x2f : 0xf7);
902 } else if (std == V4L2_STD_NTSC_M_KR) {
903 /* South Korea uses A2 audio standard */
904 cx25840_write(client, 0x808, hw_fix ? 0x3f : 0xf8);
905 } else {
906 /* Others use the BTSC audio standard */
907 cx25840_write(client, 0x808, hw_fix ? 0x1f : 0xf6);
908 }
909 cx25840_write(client, 0x80b, 0x00);
910 } else if (std & V4L2_STD_PAL) {
911 /* Autodetect audio standard and audio system */
912 cx25840_write(client, 0x808, 0xff);
913 /* Since system PAL-L is pretty much non-existent and
914 not used by any public broadcast network, force
915 6.5 MHz carrier to be interpreted as System DK,
916 this avoids DK audio detection instability */
917 cx25840_write(client, 0x80b, 0x00);
918 } else if (std & V4L2_STD_SECAM) {
919 /* Autodetect audio standard and audio system */
920 cx25840_write(client, 0x808, 0xff);
921 /* If only one of SECAM-DK / SECAM-L is required, then force
922 6.5MHz carrier, else autodetect it */
923 if ((std & V4L2_STD_SECAM_DK) &&
924 !(std & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC))) {
925 /* 6.5 MHz carrier to be interpreted as System DK */
926 cx25840_write(client, 0x80b, 0x00);
927 } else if (!(std & V4L2_STD_SECAM_DK) &&
928 (std & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC))) {
929 /* 6.5 MHz carrier to be interpreted as System L */
930 cx25840_write(client, 0x80b, 0x08);
931 } else {
932 /* 6.5 MHz carrier to be autodetected */
933 cx25840_write(client, 0x80b, 0x10);
934 }
935 }
936
937 cx25840_and_or(client, 0x810, ~0x01, 0);
938 }
939
940 static int set_input(struct i2c_client *client, enum cx25840_video_input vid_input,
941 enum cx25840_audio_input aud_input)
942 {
943 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
944 u8 is_composite = (vid_input >= CX25840_COMPOSITE1 &&
945 vid_input <= CX25840_COMPOSITE8);
946 u8 is_component = (vid_input & CX25840_COMPONENT_ON) ==
947 CX25840_COMPONENT_ON;
948 int luma = vid_input & 0xf0;
949 int chroma = vid_input & 0xf00;
950 u8 reg;
951
952 v4l_dbg(1, cx25840_debug, client,
953 "decoder set video input %d, audio input %d\n",
954 vid_input, aud_input);
955
956 if (vid_input >= CX25840_VIN1_CH1) {
957 v4l_dbg(1, cx25840_debug, client, "vid_input 0x%x\n",
958 vid_input);
959 reg = vid_input & 0xff;
960 is_composite = !is_component &&
961 ((vid_input & CX25840_SVIDEO_ON) != CX25840_SVIDEO_ON);
962
963 v4l_dbg(1, cx25840_debug, client, "mux cfg 0x%x comp=%d\n",
964 reg, is_composite);
965 } else if (is_composite) {
966 reg = 0xf0 + (vid_input - CX25840_COMPOSITE1);
967 } else {
968 if ((vid_input & ~0xff0) ||
969 luma < CX25840_SVIDEO_LUMA1 || luma > CX25840_SVIDEO_LUMA8 ||
970 chroma < CX25840_SVIDEO_CHROMA4 || chroma > CX25840_SVIDEO_CHROMA8) {
971 v4l_err(client, "0x%04x is not a valid video input!\n",
972 vid_input);
973 return -EINVAL;
974 }
975 reg = 0xf0 + ((luma - CX25840_SVIDEO_LUMA1) >> 4);
976 if (chroma >= CX25840_SVIDEO_CHROMA7) {
977 reg &= 0x3f;
978 reg |= (chroma - CX25840_SVIDEO_CHROMA7) >> 2;
979 } else {
980 reg &= 0xcf;
981 reg |= (chroma - CX25840_SVIDEO_CHROMA4) >> 4;
982 }
983 }
984
985 /* The caller has previously prepared the correct routing
986 * configuration in reg (for the cx23885) so we have no
987 * need to attempt to flip bits for earlier av decoders.
988 */
989 if (!is_cx2388x(state) && !is_cx231xx(state)) {
990 switch (aud_input) {
991 case CX25840_AUDIO_SERIAL:
992 /* do nothing, use serial audio input */
993 break;
994 case CX25840_AUDIO4: reg &= ~0x30; break;
995 case CX25840_AUDIO5: reg &= ~0x30; reg |= 0x10; break;
996 case CX25840_AUDIO6: reg &= ~0x30; reg |= 0x20; break;
997 case CX25840_AUDIO7: reg &= ~0xc0; break;
998 case CX25840_AUDIO8: reg &= ~0xc0; reg |= 0x40; break;
999
1000 default:
1001 v4l_err(client, "0x%04x is not a valid audio input!\n",
1002 aud_input);
1003 return -EINVAL;
1004 }
1005 }
1006
1007 cx25840_write(client, 0x103, reg);
1008
1009 /* Set INPUT_MODE to Composite, S-Video or Component */
1010 if (is_component)
1011 cx25840_and_or(client, 0x401, ~0x6, 0x6);
1012 else
1013 cx25840_and_or(client, 0x401, ~0x6, is_composite ? 0 : 0x02);
1014
1015 if (!is_cx2388x(state) && !is_cx231xx(state)) {
1016 /* Set CH_SEL_ADC2 to 1 if input comes from CH3 */
1017 cx25840_and_or(client, 0x102, ~0x2, (reg & 0x80) == 0 ? 2 : 0);
1018 /* Set DUAL_MODE_ADC2 to 1 if input comes from both CH2&CH3 */
1019 if ((reg & 0xc0) != 0xc0 && (reg & 0x30) != 0x30)
1020 cx25840_and_or(client, 0x102, ~0x4, 4);
1021 else
1022 cx25840_and_or(client, 0x102, ~0x4, 0);
1023 } else {
1024 /* Set DUAL_MODE_ADC2 to 1 if component*/
1025 cx25840_and_or(client, 0x102, ~0x4, is_component ? 0x4 : 0x0);
1026 if (is_composite) {
1027 /* ADC2 input select channel 2 */
1028 cx25840_and_or(client, 0x102, ~0x2, 0);
1029 } else if (!is_component) {
1030 /* S-Video */
1031 if (chroma >= CX25840_SVIDEO_CHROMA7) {
1032 /* ADC2 input select channel 3 */
1033 cx25840_and_or(client, 0x102, ~0x2, 2);
1034 } else {
1035 /* ADC2 input select channel 2 */
1036 cx25840_and_or(client, 0x102, ~0x2, 0);
1037 }
1038 }
1039 }
1040
1041 state->vid_input = vid_input;
1042 state->aud_input = aud_input;
1043 cx25840_audio_set_path(client);
1044 input_change(client);
1045
1046 if (is_cx2388x(state)) {
1047 /* Audio channel 1 src : Parallel 1 */
1048 cx25840_write(client, 0x124, 0x03);
1049
1050 /* Select AFE clock pad output source */
1051 cx25840_write(client, 0x144, 0x05);
1052
1053 /* I2S_IN_CTL: I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1 */
1054 cx25840_write(client, 0x914, 0xa0);
1055
1056 /* I2S_OUT_CTL:
1057 * I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1
1058 * I2S_OUT_MASTER_MODE = Master
1059 */
1060 cx25840_write(client, 0x918, 0xa0);
1061 cx25840_write(client, 0x919, 0x01);
1062 } else if (is_cx231xx(state)) {
1063 /* Audio channel 1 src : Parallel 1 */
1064 cx25840_write(client, 0x124, 0x03);
1065
1066 /* I2S_IN_CTL: I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1 */
1067 cx25840_write(client, 0x914, 0xa0);
1068
1069 /* I2S_OUT_CTL:
1070 * I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1
1071 * I2S_OUT_MASTER_MODE = Master
1072 */
1073 cx25840_write(client, 0x918, 0xa0);
1074 cx25840_write(client, 0x919, 0x01);
1075 }
1076
1077 if (is_cx2388x(state) && ((aud_input == CX25840_AUDIO7) ||
1078 (aud_input == CX25840_AUDIO6))) {
1079 /* Configure audio from LR1 or LR2 input */
1080 cx25840_write4(client, 0x910, 0);
1081 cx25840_write4(client, 0x8d0, 0x63073);
1082 } else
1083 if (is_cx2388x(state) && (aud_input == CX25840_AUDIO8)) {
1084 /* Configure audio from tuner/sif input */
1085 cx25840_write4(client, 0x910, 0x12b000c9);
1086 cx25840_write4(client, 0x8d0, 0x1f063870);
1087 }
1088
1089 return 0;
1090 }
1091
1092 /* ----------------------------------------------------------------------- */
1093
1094 static int set_v4lstd(struct i2c_client *client)
1095 {
1096 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
1097 u8 fmt = 0; /* zero is autodetect */
1098 u8 pal_m = 0;
1099
1100 /* First tests should be against specific std */
1101 if (state->std == V4L2_STD_NTSC_M_JP) {
1102 fmt = 0x2;
1103 } else if (state->std == V4L2_STD_NTSC_443) {
1104 fmt = 0x3;
1105 } else if (state->std == V4L2_STD_PAL_M) {
1106 pal_m = 1;
1107 fmt = 0x5;
1108 } else if (state->std == V4L2_STD_PAL_N) {
1109 fmt = 0x6;
1110 } else if (state->std == V4L2_STD_PAL_Nc) {
1111 fmt = 0x7;
1112 } else if (state->std == V4L2_STD_PAL_60) {
1113 fmt = 0x8;
1114 } else {
1115 /* Then, test against generic ones */
1116 if (state->std & V4L2_STD_NTSC)
1117 fmt = 0x1;
1118 else if (state->std & V4L2_STD_PAL)
1119 fmt = 0x4;
1120 else if (state->std & V4L2_STD_SECAM)
1121 fmt = 0xc;
1122 }
1123
1124 v4l_dbg(1, cx25840_debug, client, "changing video std to fmt %i\n",fmt);
1125
1126 /* Follow step 9 of section 3.16 in the cx25840 datasheet.
1127 Without this PAL may display a vertical ghosting effect.
1128 This happens for example with the Yuan MPC622. */
1129 if (fmt >= 4 && fmt < 8) {
1130 /* Set format to NTSC-M */
1131 cx25840_and_or(client, 0x400, ~0xf, 1);
1132 /* Turn off LCOMB */
1133 cx25840_and_or(client, 0x47b, ~6, 0);
1134 }
1135 cx25840_and_or(client, 0x400, ~0xf, fmt);
1136 cx25840_and_or(client, 0x403, ~0x3, pal_m);
1137 cx25840_std_setup(client);
1138 if (!is_cx2583x(state))
1139 input_change(client);
1140 return 0;
1141 }
1142
1143 /* ----------------------------------------------------------------------- */
1144
1145 static int cx25840_s_ctrl(struct v4l2_ctrl *ctrl)
1146 {
1147 struct v4l2_subdev *sd = to_sd(ctrl);
1148 struct i2c_client *client = v4l2_get_subdevdata(sd);
1149
1150 switch (ctrl->id) {
1151 case V4L2_CID_BRIGHTNESS:
1152 cx25840_write(client, 0x414, ctrl->val - 128);
1153 break;
1154
1155 case V4L2_CID_CONTRAST:
1156 cx25840_write(client, 0x415, ctrl->val << 1);
1157 break;
1158
1159 case V4L2_CID_SATURATION:
1160 cx25840_write(client, 0x420, ctrl->val << 1);
1161 cx25840_write(client, 0x421, ctrl->val << 1);
1162 break;
1163
1164 case V4L2_CID_HUE:
1165 cx25840_write(client, 0x422, ctrl->val);
1166 break;
1167
1168 default:
1169 return -EINVAL;
1170 }
1171
1172 return 0;
1173 }
1174
1175 /* ----------------------------------------------------------------------- */
1176
1177 static int cx25840_s_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *fmt)
1178 {
1179 struct cx25840_state *state = to_state(sd);
1180 struct i2c_client *client = v4l2_get_subdevdata(sd);
1181 int HSC, VSC, Vsrc, Hsrc, filter, Vlines;
1182 int is_50Hz = !(state->std & V4L2_STD_525_60);
1183
1184 if (fmt->code != V4L2_MBUS_FMT_FIXED)
1185 return -EINVAL;
1186
1187 fmt->field = V4L2_FIELD_INTERLACED;
1188 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
1189
1190 Vsrc = (cx25840_read(client, 0x476) & 0x3f) << 4;
1191 Vsrc |= (cx25840_read(client, 0x475) & 0xf0) >> 4;
1192
1193 Hsrc = (cx25840_read(client, 0x472) & 0x3f) << 4;
1194 Hsrc |= (cx25840_read(client, 0x471) & 0xf0) >> 4;
1195
1196 Vlines = fmt->height + (is_50Hz ? 4 : 7);
1197
1198 if ((fmt->width * 16 < Hsrc) || (Hsrc < fmt->width) ||
1199 (Vlines * 8 < Vsrc) || (Vsrc < Vlines)) {
1200 v4l_err(client, "%dx%d is not a valid size!\n",
1201 fmt->width, fmt->height);
1202 return -ERANGE;
1203 }
1204
1205 HSC = (Hsrc * (1 << 20)) / fmt->width - (1 << 20);
1206 VSC = (1 << 16) - (Vsrc * (1 << 9) / Vlines - (1 << 9));
1207 VSC &= 0x1fff;
1208
1209 if (fmt->width >= 385)
1210 filter = 0;
1211 else if (fmt->width > 192)
1212 filter = 1;
1213 else if (fmt->width > 96)
1214 filter = 2;
1215 else
1216 filter = 3;
1217
1218 v4l_dbg(1, cx25840_debug, client, "decoder set size %dx%d -> scale %ux%u\n",
1219 fmt->width, fmt->height, HSC, VSC);
1220
1221 /* HSCALE=HSC */
1222 cx25840_write(client, 0x418, HSC & 0xff);
1223 cx25840_write(client, 0x419, (HSC >> 8) & 0xff);
1224 cx25840_write(client, 0x41a, HSC >> 16);
1225 /* VSCALE=VSC */
1226 cx25840_write(client, 0x41c, VSC & 0xff);
1227 cx25840_write(client, 0x41d, VSC >> 8);
1228 /* VS_INTRLACE=1 VFILT=filter */
1229 cx25840_write(client, 0x41e, 0x8 | filter);
1230 return 0;
1231 }
1232
1233 /* ----------------------------------------------------------------------- */
1234
1235 static void log_video_status(struct i2c_client *client)
1236 {
1237 static const char *const fmt_strs[] = {
1238 "0x0",
1239 "NTSC-M", "NTSC-J", "NTSC-4.43",
1240 "PAL-BDGHI", "PAL-M", "PAL-N", "PAL-Nc", "PAL-60",
1241 "0x9", "0xA", "0xB",
1242 "SECAM",
1243 "0xD", "0xE", "0xF"
1244 };
1245
1246 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
1247 u8 vidfmt_sel = cx25840_read(client, 0x400) & 0xf;
1248 u8 gen_stat1 = cx25840_read(client, 0x40d);
1249 u8 gen_stat2 = cx25840_read(client, 0x40e);
1250 int vid_input = state->vid_input;
1251
1252 v4l_info(client, "Video signal: %spresent\n",
1253 (gen_stat2 & 0x20) ? "" : "not ");
1254 v4l_info(client, "Detected format: %s\n",
1255 fmt_strs[gen_stat1 & 0xf]);
1256
1257 v4l_info(client, "Specified standard: %s\n",
1258 vidfmt_sel ? fmt_strs[vidfmt_sel] : "automatic detection");
1259
1260 if (vid_input >= CX25840_COMPOSITE1 &&
1261 vid_input <= CX25840_COMPOSITE8) {
1262 v4l_info(client, "Specified video input: Composite %d\n",
1263 vid_input - CX25840_COMPOSITE1 + 1);
1264 } else {
1265 v4l_info(client, "Specified video input: S-Video (Luma In%d, Chroma In%d)\n",
1266 (vid_input & 0xf0) >> 4, (vid_input & 0xf00) >> 8);
1267 }
1268
1269 v4l_info(client, "Specified audioclock freq: %d Hz\n", state->audclk_freq);
1270 }
1271
1272 /* ----------------------------------------------------------------------- */
1273
1274 static void log_audio_status(struct i2c_client *client)
1275 {
1276 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
1277 u8 download_ctl = cx25840_read(client, 0x803);
1278 u8 mod_det_stat0 = cx25840_read(client, 0x804);
1279 u8 mod_det_stat1 = cx25840_read(client, 0x805);
1280 u8 audio_config = cx25840_read(client, 0x808);
1281 u8 pref_mode = cx25840_read(client, 0x809);
1282 u8 afc0 = cx25840_read(client, 0x80b);
1283 u8 mute_ctl = cx25840_read(client, 0x8d3);
1284 int aud_input = state->aud_input;
1285 char *p;
1286
1287 switch (mod_det_stat0) {
1288 case 0x00: p = "mono"; break;
1289 case 0x01: p = "stereo"; break;
1290 case 0x02: p = "dual"; break;
1291 case 0x04: p = "tri"; break;
1292 case 0x10: p = "mono with SAP"; break;
1293 case 0x11: p = "stereo with SAP"; break;
1294 case 0x12: p = "dual with SAP"; break;
1295 case 0x14: p = "tri with SAP"; break;
1296 case 0xfe: p = "forced mode"; break;
1297 default: p = "not defined";
1298 }
1299 v4l_info(client, "Detected audio mode: %s\n", p);
1300
1301 switch (mod_det_stat1) {
1302 case 0x00: p = "not defined"; break;
1303 case 0x01: p = "EIAJ"; break;
1304 case 0x02: p = "A2-M"; break;
1305 case 0x03: p = "A2-BG"; break;
1306 case 0x04: p = "A2-DK1"; break;
1307 case 0x05: p = "A2-DK2"; break;
1308 case 0x06: p = "A2-DK3"; break;
1309 case 0x07: p = "A1 (6.0 MHz FM Mono)"; break;
1310 case 0x08: p = "AM-L"; break;
1311 case 0x09: p = "NICAM-BG"; break;
1312 case 0x0a: p = "NICAM-DK"; break;
1313 case 0x0b: p = "NICAM-I"; break;
1314 case 0x0c: p = "NICAM-L"; break;
1315 case 0x0d: p = "BTSC/EIAJ/A2-M Mono (4.5 MHz FMMono)"; break;
1316 case 0x0e: p = "IF FM Radio"; break;
1317 case 0x0f: p = "BTSC"; break;
1318 case 0x10: p = "high-deviation FM"; break;
1319 case 0x11: p = "very high-deviation FM"; break;
1320 case 0xfd: p = "unknown audio standard"; break;
1321 case 0xfe: p = "forced audio standard"; break;
1322 case 0xff: p = "no detected audio standard"; break;
1323 default: p = "not defined";
1324 }
1325 v4l_info(client, "Detected audio standard: %s\n", p);
1326 v4l_info(client, "Audio microcontroller: %s\n",
1327 (download_ctl & 0x10) ?
1328 ((mute_ctl & 0x2) ? "detecting" : "running") : "stopped");
1329
1330 switch (audio_config >> 4) {
1331 case 0x00: p = "undefined"; break;
1332 case 0x01: p = "BTSC"; break;
1333 case 0x02: p = "EIAJ"; break;
1334 case 0x03: p = "A2-M"; break;
1335 case 0x04: p = "A2-BG"; break;
1336 case 0x05: p = "A2-DK1"; break;
1337 case 0x06: p = "A2-DK2"; break;
1338 case 0x07: p = "A2-DK3"; break;
1339 case 0x08: p = "A1 (6.0 MHz FM Mono)"; break;
1340 case 0x09: p = "AM-L"; break;
1341 case 0x0a: p = "NICAM-BG"; break;
1342 case 0x0b: p = "NICAM-DK"; break;
1343 case 0x0c: p = "NICAM-I"; break;
1344 case 0x0d: p = "NICAM-L"; break;
1345 case 0x0e: p = "FM radio"; break;
1346 case 0x0f: p = "automatic detection"; break;
1347 default: p = "undefined";
1348 }
1349 v4l_info(client, "Configured audio standard: %s\n", p);
1350
1351 if ((audio_config >> 4) < 0xF) {
1352 switch (audio_config & 0xF) {
1353 case 0x00: p = "MONO1 (LANGUAGE A/Mono L+R channel for BTSC, EIAJ, A2)"; break;
1354 case 0x01: p = "MONO2 (LANGUAGE B)"; break;
1355 case 0x02: p = "MONO3 (STEREO forced MONO)"; break;
1356 case 0x03: p = "MONO4 (NICAM ANALOG-Language C/Analog Fallback)"; break;
1357 case 0x04: p = "STEREO"; break;
1358 case 0x05: p = "DUAL1 (AB)"; break;
1359 case 0x06: p = "DUAL2 (AC) (FM)"; break;
1360 case 0x07: p = "DUAL3 (BC) (FM)"; break;
1361 case 0x08: p = "DUAL4 (AC) (AM)"; break;
1362 case 0x09: p = "DUAL5 (BC) (AM)"; break;
1363 case 0x0a: p = "SAP"; break;
1364 default: p = "undefined";
1365 }
1366 v4l_info(client, "Configured audio mode: %s\n", p);
1367 } else {
1368 switch (audio_config & 0xF) {
1369 case 0x00: p = "BG"; break;
1370 case 0x01: p = "DK1"; break;
1371 case 0x02: p = "DK2"; break;
1372 case 0x03: p = "DK3"; break;
1373 case 0x04: p = "I"; break;
1374 case 0x05: p = "L"; break;
1375 case 0x06: p = "BTSC"; break;
1376 case 0x07: p = "EIAJ"; break;
1377 case 0x08: p = "A2-M"; break;
1378 case 0x09: p = "FM Radio"; break;
1379 case 0x0f: p = "automatic standard and mode detection"; break;
1380 default: p = "undefined";
1381 }
1382 v4l_info(client, "Configured audio system: %s\n", p);
1383 }
1384
1385 if (aud_input) {
1386 v4l_info(client, "Specified audio input: Tuner (In%d)\n", aud_input);
1387 } else {
1388 v4l_info(client, "Specified audio input: External\n");
1389 }
1390
1391 switch (pref_mode & 0xf) {
1392 case 0: p = "mono/language A"; break;
1393 case 1: p = "language B"; break;
1394 case 2: p = "language C"; break;
1395 case 3: p = "analog fallback"; break;
1396 case 4: p = "stereo"; break;
1397 case 5: p = "language AC"; break;
1398 case 6: p = "language BC"; break;
1399 case 7: p = "language AB"; break;
1400 default: p = "undefined";
1401 }
1402 v4l_info(client, "Preferred audio mode: %s\n", p);
1403
1404 if ((audio_config & 0xf) == 0xf) {
1405 switch ((afc0 >> 3) & 0x3) {
1406 case 0: p = "system DK"; break;
1407 case 1: p = "system L"; break;
1408 case 2: p = "autodetect"; break;
1409 default: p = "undefined";
1410 }
1411 v4l_info(client, "Selected 65 MHz format: %s\n", p);
1412
1413 switch (afc0 & 0x7) {
1414 case 0: p = "chroma"; break;
1415 case 1: p = "BTSC"; break;
1416 case 2: p = "EIAJ"; break;
1417 case 3: p = "A2-M"; break;
1418 case 4: p = "autodetect"; break;
1419 default: p = "undefined";
1420 }
1421 v4l_info(client, "Selected 45 MHz format: %s\n", p);
1422 }
1423 }
1424
1425 /* ----------------------------------------------------------------------- */
1426
1427 /* This load_fw operation must be called to load the driver's firmware.
1428 Without this the audio standard detection will fail and you will
1429 only get mono.
1430
1431 Since loading the firmware is often problematic when the driver is
1432 compiled into the kernel I recommend postponing calling this function
1433 until the first open of the video device. Another reason for
1434 postponing it is that loading this firmware takes a long time (seconds)
1435 due to the slow i2c bus speed. So it will speed up the boot process if
1436 you can avoid loading the fw as long as the video device isn't used. */
1437 static int cx25840_load_fw(struct v4l2_subdev *sd)
1438 {
1439 struct cx25840_state *state = to_state(sd);
1440 struct i2c_client *client = v4l2_get_subdevdata(sd);
1441
1442 if (!state->is_initialized) {
1443 /* initialize and load firmware */
1444 state->is_initialized = 1;
1445 if (is_cx2583x(state))
1446 cx25836_initialize(client);
1447 else if (is_cx2388x(state))
1448 cx23885_initialize(client);
1449 else if (is_cx231xx(state))
1450 cx231xx_initialize(client);
1451 else
1452 cx25840_initialize(client);
1453 }
1454 return 0;
1455 }
1456
1457 #ifdef CONFIG_VIDEO_ADV_DEBUG
1458 static int cx25840_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1459 {
1460 struct i2c_client *client = v4l2_get_subdevdata(sd);
1461
1462 if (!v4l2_chip_match_i2c_client(client, &reg->match))
1463 return -EINVAL;
1464 if (!capable(CAP_SYS_ADMIN))
1465 return -EPERM;
1466 reg->size = 1;
1467 reg->val = cx25840_read(client, reg->reg & 0x0fff);
1468 return 0;
1469 }
1470
1471 static int cx25840_s_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1472 {
1473 struct i2c_client *client = v4l2_get_subdevdata(sd);
1474
1475 if (!v4l2_chip_match_i2c_client(client, &reg->match))
1476 return -EINVAL;
1477 if (!capable(CAP_SYS_ADMIN))
1478 return -EPERM;
1479 cx25840_write(client, reg->reg & 0x0fff, reg->val & 0xff);
1480 return 0;
1481 }
1482 #endif
1483
1484 static int cx25840_s_audio_stream(struct v4l2_subdev *sd, int enable)
1485 {
1486 struct cx25840_state *state = to_state(sd);
1487 struct i2c_client *client = v4l2_get_subdevdata(sd);
1488 u8 v;
1489
1490 if (is_cx2583x(state) || is_cx2388x(state) || is_cx231xx(state))
1491 return 0;
1492
1493 v4l_dbg(1, cx25840_debug, client, "%s audio output\n",
1494 enable ? "enable" : "disable");
1495
1496 if (enable) {
1497 v = cx25840_read(client, 0x115) | 0x80;
1498 cx25840_write(client, 0x115, v);
1499 v = cx25840_read(client, 0x116) | 0x03;
1500 cx25840_write(client, 0x116, v);
1501 } else {
1502 v = cx25840_read(client, 0x115) & ~(0x80);
1503 cx25840_write(client, 0x115, v);
1504 v = cx25840_read(client, 0x116) & ~(0x03);
1505 cx25840_write(client, 0x116, v);
1506 }
1507 return 0;
1508 }
1509
1510 static int cx25840_s_stream(struct v4l2_subdev *sd, int enable)
1511 {
1512 struct cx25840_state *state = to_state(sd);
1513 struct i2c_client *client = v4l2_get_subdevdata(sd);
1514 u8 v;
1515
1516 v4l_dbg(1, cx25840_debug, client, "%s video output\n",
1517 enable ? "enable" : "disable");
1518 if (enable) {
1519 if (is_cx2388x(state) || is_cx231xx(state)) {
1520 v = cx25840_read(client, 0x421) | 0x0b;
1521 cx25840_write(client, 0x421, v);
1522 } else {
1523 v = cx25840_read(client, 0x115) | 0x0c;
1524 cx25840_write(client, 0x115, v);
1525 v = cx25840_read(client, 0x116) | 0x04;
1526 cx25840_write(client, 0x116, v);
1527 }
1528 } else {
1529 if (is_cx2388x(state) || is_cx231xx(state)) {
1530 v = cx25840_read(client, 0x421) & ~(0x0b);
1531 cx25840_write(client, 0x421, v);
1532 } else {
1533 v = cx25840_read(client, 0x115) & ~(0x0c);
1534 cx25840_write(client, 0x115, v);
1535 v = cx25840_read(client, 0x116) & ~(0x04);
1536 cx25840_write(client, 0x116, v);
1537 }
1538 }
1539 return 0;
1540 }
1541
1542 static int cx25840_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
1543 {
1544 struct cx25840_state *state = to_state(sd);
1545 struct i2c_client *client = v4l2_get_subdevdata(sd);
1546
1547 if (state->radio == 0 && state->std == std)
1548 return 0;
1549 state->radio = 0;
1550 state->std = std;
1551 return set_v4lstd(client);
1552 }
1553
1554 static int cx25840_s_radio(struct v4l2_subdev *sd)
1555 {
1556 struct cx25840_state *state = to_state(sd);
1557
1558 state->radio = 1;
1559 return 0;
1560 }
1561
1562 static int cx25840_s_video_routing(struct v4l2_subdev *sd,
1563 u32 input, u32 output, u32 config)
1564 {
1565 struct cx25840_state *state = to_state(sd);
1566 struct i2c_client *client = v4l2_get_subdevdata(sd);
1567
1568 return set_input(client, input, state->aud_input);
1569 }
1570
1571 static int cx25840_s_audio_routing(struct v4l2_subdev *sd,
1572 u32 input, u32 output, u32 config)
1573 {
1574 struct cx25840_state *state = to_state(sd);
1575 struct i2c_client *client = v4l2_get_subdevdata(sd);
1576
1577 return set_input(client, state->vid_input, input);
1578 }
1579
1580 static int cx25840_s_frequency(struct v4l2_subdev *sd, struct v4l2_frequency *freq)
1581 {
1582 struct i2c_client *client = v4l2_get_subdevdata(sd);
1583
1584 input_change(client);
1585 return 0;
1586 }
1587
1588 static int cx25840_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1589 {
1590 struct cx25840_state *state = to_state(sd);
1591 struct i2c_client *client = v4l2_get_subdevdata(sd);
1592 u8 vpres = cx25840_read(client, 0x40e) & 0x20;
1593 u8 mode;
1594 int val = 0;
1595
1596 if (state->radio)
1597 return 0;
1598
1599 vt->signal = vpres ? 0xffff : 0x0;
1600 if (is_cx2583x(state))
1601 return 0;
1602
1603 vt->capability |=
1604 V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
1605 V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
1606
1607 mode = cx25840_read(client, 0x804);
1608
1609 /* get rxsubchans and audmode */
1610 if ((mode & 0xf) == 1)
1611 val |= V4L2_TUNER_SUB_STEREO;
1612 else
1613 val |= V4L2_TUNER_SUB_MONO;
1614
1615 if (mode == 2 || mode == 4)
1616 val = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
1617
1618 if (mode & 0x10)
1619 val |= V4L2_TUNER_SUB_SAP;
1620
1621 vt->rxsubchans = val;
1622 vt->audmode = state->audmode;
1623 return 0;
1624 }
1625
1626 static int cx25840_s_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1627 {
1628 struct cx25840_state *state = to_state(sd);
1629 struct i2c_client *client = v4l2_get_subdevdata(sd);
1630
1631 if (state->radio || is_cx2583x(state))
1632 return 0;
1633
1634 switch (vt->audmode) {
1635 case V4L2_TUNER_MODE_MONO:
1636 /* mono -> mono
1637 stereo -> mono
1638 bilingual -> lang1 */
1639 cx25840_and_or(client, 0x809, ~0xf, 0x00);
1640 break;
1641 case V4L2_TUNER_MODE_STEREO:
1642 case V4L2_TUNER_MODE_LANG1:
1643 /* mono -> mono
1644 stereo -> stereo
1645 bilingual -> lang1 */
1646 cx25840_and_or(client, 0x809, ~0xf, 0x04);
1647 break;
1648 case V4L2_TUNER_MODE_LANG1_LANG2:
1649 /* mono -> mono
1650 stereo -> stereo
1651 bilingual -> lang1/lang2 */
1652 cx25840_and_or(client, 0x809, ~0xf, 0x07);
1653 break;
1654 case V4L2_TUNER_MODE_LANG2:
1655 /* mono -> mono
1656 stereo -> stereo
1657 bilingual -> lang2 */
1658 cx25840_and_or(client, 0x809, ~0xf, 0x01);
1659 break;
1660 default:
1661 return -EINVAL;
1662 }
1663 state->audmode = vt->audmode;
1664 return 0;
1665 }
1666
1667 static int cx25840_reset(struct v4l2_subdev *sd, u32 val)
1668 {
1669 struct cx25840_state *state = to_state(sd);
1670 struct i2c_client *client = v4l2_get_subdevdata(sd);
1671
1672 if (is_cx2583x(state))
1673 cx25836_initialize(client);
1674 else if (is_cx2388x(state))
1675 cx23885_initialize(client);
1676 else if (is_cx231xx(state))
1677 cx231xx_initialize(client);
1678 else
1679 cx25840_initialize(client);
1680 return 0;
1681 }
1682
1683 static int cx25840_g_chip_ident(struct v4l2_subdev *sd, struct v4l2_dbg_chip_ident *chip)
1684 {
1685 struct cx25840_state *state = to_state(sd);
1686 struct i2c_client *client = v4l2_get_subdevdata(sd);
1687
1688 return v4l2_chip_ident_i2c_client(client, chip, state->id, state->rev);
1689 }
1690
1691 static int cx25840_log_status(struct v4l2_subdev *sd)
1692 {
1693 struct cx25840_state *state = to_state(sd);
1694 struct i2c_client *client = v4l2_get_subdevdata(sd);
1695
1696 log_video_status(client);
1697 if (!is_cx2583x(state))
1698 log_audio_status(client);
1699 cx25840_ir_log_status(sd);
1700 v4l2_ctrl_handler_log_status(&state->hdl, sd->name);
1701 return 0;
1702 }
1703
1704 static int cx23885_irq_handler(struct v4l2_subdev *sd, u32 status,
1705 bool *handled)
1706 {
1707 struct cx25840_state *state = to_state(sd);
1708 struct i2c_client *c = v4l2_get_subdevdata(sd);
1709 u8 irq_stat, aud_stat, aud_en, ir_stat, ir_en;
1710 u32 vid_stat, aud_mc_stat;
1711 bool block_handled;
1712 int ret = 0;
1713
1714 irq_stat = cx25840_read(c, CX23885_PIN_CTRL_IRQ_REG);
1715 v4l_dbg(2, cx25840_debug, c, "AV Core IRQ status (entry): %s %s %s\n",
1716 irq_stat & CX23885_PIN_CTRL_IRQ_IR_STAT ? "ir" : " ",
1717 irq_stat & CX23885_PIN_CTRL_IRQ_AUD_STAT ? "aud" : " ",
1718 irq_stat & CX23885_PIN_CTRL_IRQ_VID_STAT ? "vid" : " ");
1719
1720 if ((is_cx23885(state) || is_cx23887(state))) {
1721 ir_stat = cx25840_read(c, CX25840_IR_STATS_REG);
1722 ir_en = cx25840_read(c, CX25840_IR_IRQEN_REG);
1723 v4l_dbg(2, cx25840_debug, c,
1724 "AV Core ir IRQ status: %#04x disables: %#04x\n",
1725 ir_stat, ir_en);
1726 if (irq_stat & CX23885_PIN_CTRL_IRQ_IR_STAT) {
1727 block_handled = false;
1728 ret = cx25840_ir_irq_handler(sd,
1729 status, &block_handled);
1730 if (block_handled)
1731 *handled = true;
1732 }
1733 }
1734
1735 aud_stat = cx25840_read(c, CX25840_AUD_INT_STAT_REG);
1736 aud_en = cx25840_read(c, CX25840_AUD_INT_CTRL_REG);
1737 v4l_dbg(2, cx25840_debug, c,
1738 "AV Core audio IRQ status: %#04x disables: %#04x\n",
1739 aud_stat, aud_en);
1740 aud_mc_stat = cx25840_read4(c, CX23885_AUD_MC_INT_MASK_REG);
1741 v4l_dbg(2, cx25840_debug, c,
1742 "AV Core audio MC IRQ status: %#06x enables: %#06x\n",
1743 aud_mc_stat >> CX23885_AUD_MC_INT_STAT_SHFT,
1744 aud_mc_stat & CX23885_AUD_MC_INT_CTRL_BITS);
1745 if (irq_stat & CX23885_PIN_CTRL_IRQ_AUD_STAT) {
1746 if (aud_stat) {
1747 cx25840_write(c, CX25840_AUD_INT_STAT_REG, aud_stat);
1748 *handled = true;
1749 }
1750 }
1751
1752 vid_stat = cx25840_read4(c, CX25840_VID_INT_STAT_REG);
1753 v4l_dbg(2, cx25840_debug, c,
1754 "AV Core video IRQ status: %#06x disables: %#06x\n",
1755 vid_stat & CX25840_VID_INT_STAT_BITS,
1756 vid_stat >> CX25840_VID_INT_MASK_SHFT);
1757 if (irq_stat & CX23885_PIN_CTRL_IRQ_VID_STAT) {
1758 if (vid_stat & CX25840_VID_INT_STAT_BITS) {
1759 cx25840_write4(c, CX25840_VID_INT_STAT_REG, vid_stat);
1760 *handled = true;
1761 }
1762 }
1763
1764 irq_stat = cx25840_read(c, CX23885_PIN_CTRL_IRQ_REG);
1765 v4l_dbg(2, cx25840_debug, c, "AV Core IRQ status (exit): %s %s %s\n",
1766 irq_stat & CX23885_PIN_CTRL_IRQ_IR_STAT ? "ir" : " ",
1767 irq_stat & CX23885_PIN_CTRL_IRQ_AUD_STAT ? "aud" : " ",
1768 irq_stat & CX23885_PIN_CTRL_IRQ_VID_STAT ? "vid" : " ");
1769
1770 return ret;
1771 }
1772
1773 static int cx25840_irq_handler(struct v4l2_subdev *sd, u32 status,
1774 bool *handled)
1775 {
1776 struct cx25840_state *state = to_state(sd);
1777
1778 *handled = false;
1779
1780 /* Only support the CX2388[578] AV Core for now */
1781 if (is_cx2388x(state))
1782 return cx23885_irq_handler(sd, status, handled);
1783
1784 return -ENODEV;
1785 }
1786
1787 /* ----------------------------------------------------------------------- */
1788
1789 static const struct v4l2_ctrl_ops cx25840_ctrl_ops = {
1790 .s_ctrl = cx25840_s_ctrl,
1791 };
1792
1793 static const struct v4l2_subdev_core_ops cx25840_core_ops = {
1794 .log_status = cx25840_log_status,
1795 .g_chip_ident = cx25840_g_chip_ident,
1796 .g_ctrl = v4l2_subdev_g_ctrl,
1797 .s_ctrl = v4l2_subdev_s_ctrl,
1798 .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
1799 .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
1800 .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
1801 .queryctrl = v4l2_subdev_queryctrl,
1802 .querymenu = v4l2_subdev_querymenu,
1803 .s_std = cx25840_s_std,
1804 .reset = cx25840_reset,
1805 .load_fw = cx25840_load_fw,
1806 .s_io_pin_config = common_s_io_pin_config,
1807 #ifdef CONFIG_VIDEO_ADV_DEBUG
1808 .g_register = cx25840_g_register,
1809 .s_register = cx25840_s_register,
1810 #endif
1811 .interrupt_service_routine = cx25840_irq_handler,
1812 };
1813
1814 static const struct v4l2_subdev_tuner_ops cx25840_tuner_ops = {
1815 .s_frequency = cx25840_s_frequency,
1816 .s_radio = cx25840_s_radio,
1817 .g_tuner = cx25840_g_tuner,
1818 .s_tuner = cx25840_s_tuner,
1819 };
1820
1821 static const struct v4l2_subdev_audio_ops cx25840_audio_ops = {
1822 .s_clock_freq = cx25840_s_clock_freq,
1823 .s_routing = cx25840_s_audio_routing,
1824 .s_stream = cx25840_s_audio_stream,
1825 };
1826
1827 static const struct v4l2_subdev_video_ops cx25840_video_ops = {
1828 .s_routing = cx25840_s_video_routing,
1829 .s_mbus_fmt = cx25840_s_mbus_fmt,
1830 .s_stream = cx25840_s_stream,
1831 };
1832
1833 static const struct v4l2_subdev_vbi_ops cx25840_vbi_ops = {
1834 .decode_vbi_line = cx25840_decode_vbi_line,
1835 .s_raw_fmt = cx25840_s_raw_fmt,
1836 .s_sliced_fmt = cx25840_s_sliced_fmt,
1837 .g_sliced_fmt = cx25840_g_sliced_fmt,
1838 };
1839
1840 static const struct v4l2_subdev_ops cx25840_ops = {
1841 .core = &cx25840_core_ops,
1842 .tuner = &cx25840_tuner_ops,
1843 .audio = &cx25840_audio_ops,
1844 .video = &cx25840_video_ops,
1845 .vbi = &cx25840_vbi_ops,
1846 .ir = &cx25840_ir_ops,
1847 };
1848
1849 /* ----------------------------------------------------------------------- */
1850
1851 static u32 get_cx2388x_ident(struct i2c_client *client)
1852 {
1853 u32 ret;
1854
1855 /* Come out of digital power down */
1856 cx25840_write(client, 0x000, 0);
1857
1858 /* Detecting whether the part is cx23885/7/8 is more
1859 * difficult than it needs to be. No ID register. Instead we
1860 * probe certain registers indicated in the datasheets to look
1861 * for specific defaults that differ between the silicon designs. */
1862
1863 /* It's either 885/7 if the IR Tx Clk Divider register exists */
1864 if (cx25840_read4(client, 0x204) & 0xffff) {
1865 /* CX23885 returns bogus repetitive byte values for the DIF,
1866 * which doesn't exist for it. (Ex. 8a8a8a8a or 31313131) */
1867 ret = cx25840_read4(client, 0x300);
1868 if (((ret & 0xffff0000) >> 16) == (ret & 0xffff)) {
1869 /* No DIF */
1870 ret = V4L2_IDENT_CX23885_AV;
1871 } else {
1872 /* CX23887 has a broken DIF, but the registers
1873 * appear valid (but unused), good enough to detect. */
1874 ret = V4L2_IDENT_CX23887_AV;
1875 }
1876 } else if (cx25840_read4(client, 0x300) & 0x0fffffff) {
1877 /* DIF PLL Freq Word reg exists; chip must be a CX23888 */
1878 ret = V4L2_IDENT_CX23888_AV;
1879 } else {
1880 v4l_err(client, "Unable to detect h/w, assuming cx23887\n");
1881 ret = V4L2_IDENT_CX23887_AV;
1882 }
1883
1884 /* Back into digital power down */
1885 cx25840_write(client, 0x000, 2);
1886 return ret;
1887 }
1888
1889 static int cx25840_probe(struct i2c_client *client,
1890 const struct i2c_device_id *did)
1891 {
1892 struct cx25840_state *state;
1893 struct v4l2_subdev *sd;
1894 int default_volume;
1895 u32 id = V4L2_IDENT_NONE;
1896 u16 device_id;
1897
1898 /* Check if the adapter supports the needed features */
1899 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1900 return -EIO;
1901
1902 v4l_dbg(1, cx25840_debug, client, "detecting cx25840 client on address 0x%x\n", client->addr << 1);
1903
1904 device_id = cx25840_read(client, 0x101) << 8;
1905 device_id |= cx25840_read(client, 0x100);
1906 v4l_dbg(1, cx25840_debug, client, "device_id = 0x%04x\n", device_id);
1907
1908 /* The high byte of the device ID should be
1909 * 0x83 for the cx2583x and 0x84 for the cx2584x */
1910 if ((device_id & 0xff00) == 0x8300) {
1911 id = V4L2_IDENT_CX25836 + ((device_id >> 4) & 0xf) - 6;
1912 } else if ((device_id & 0xff00) == 0x8400) {
1913 id = V4L2_IDENT_CX25840 + ((device_id >> 4) & 0xf);
1914 } else if (device_id == 0x0000) {
1915 id = get_cx2388x_ident(client);
1916 } else if ((device_id & 0xfff0) == 0x5A30) {
1917 /* The CX23100 (0x5A3C = 23100) doesn't have an A/V decoder */
1918 id = V4L2_IDENT_CX2310X_AV;
1919 } else if ((device_id & 0xff) == (device_id >> 8)) {
1920 v4l_err(client,
1921 "likely a confused/unresponsive cx2388[578] A/V decoder"
1922 " found @ 0x%x (%s)\n",
1923 client->addr << 1, client->adapter->name);
1924 v4l_err(client, "A method to reset it from the cx25840 driver"
1925 " software is not known at this time\n");
1926 return -ENODEV;
1927 } else {
1928 v4l_dbg(1, cx25840_debug, client, "cx25840 not found\n");
1929 return -ENODEV;
1930 }
1931
1932 state = kzalloc(sizeof(struct cx25840_state), GFP_KERNEL);
1933 if (state == NULL)
1934 return -ENOMEM;
1935
1936 sd = &state->sd;
1937 v4l2_i2c_subdev_init(sd, client, &cx25840_ops);
1938
1939 switch (id) {
1940 case V4L2_IDENT_CX23885_AV:
1941 v4l_info(client, "cx23885 A/V decoder found @ 0x%x (%s)\n",
1942 client->addr << 1, client->adapter->name);
1943 break;
1944 case V4L2_IDENT_CX23887_AV:
1945 v4l_info(client, "cx23887 A/V decoder found @ 0x%x (%s)\n",
1946 client->addr << 1, client->adapter->name);
1947 break;
1948 case V4L2_IDENT_CX23888_AV:
1949 v4l_info(client, "cx23888 A/V decoder found @ 0x%x (%s)\n",
1950 client->addr << 1, client->adapter->name);
1951 break;
1952 case V4L2_IDENT_CX2310X_AV:
1953 v4l_info(client, "cx%d A/V decoder found @ 0x%x (%s)\n",
1954 device_id, client->addr << 1, client->adapter->name);
1955 break;
1956 case V4L2_IDENT_CX25840:
1957 case V4L2_IDENT_CX25841:
1958 case V4L2_IDENT_CX25842:
1959 case V4L2_IDENT_CX25843:
1960 /* Note: revision '(device_id & 0x0f) == 2' was never built. The
1961 marking skips from 0x1 == 22 to 0x3 == 23. */
1962 v4l_info(client, "cx25%3x-2%x found @ 0x%x (%s)\n",
1963 (device_id & 0xfff0) >> 4,
1964 (device_id & 0x0f) < 3 ? (device_id & 0x0f) + 1
1965 : (device_id & 0x0f),
1966 client->addr << 1, client->adapter->name);
1967 break;
1968 case V4L2_IDENT_CX25836:
1969 case V4L2_IDENT_CX25837:
1970 default:
1971 v4l_info(client, "cx25%3x-%x found @ 0x%x (%s)\n",
1972 (device_id & 0xfff0) >> 4, device_id & 0x0f,
1973 client->addr << 1, client->adapter->name);
1974 break;
1975 }
1976
1977 state->c = client;
1978 state->vid_input = CX25840_COMPOSITE7;
1979 state->aud_input = CX25840_AUDIO8;
1980 state->audclk_freq = 48000;
1981 state->audmode = V4L2_TUNER_MODE_LANG1;
1982 state->vbi_line_offset = 8;
1983 state->id = id;
1984 state->rev = device_id;
1985 v4l2_ctrl_handler_init(&state->hdl, 9);
1986 v4l2_ctrl_new_std(&state->hdl, &cx25840_ctrl_ops,
1987 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1988 v4l2_ctrl_new_std(&state->hdl, &cx25840_ctrl_ops,
1989 V4L2_CID_CONTRAST, 0, 127, 1, 64);
1990 v4l2_ctrl_new_std(&state->hdl, &cx25840_ctrl_ops,
1991 V4L2_CID_SATURATION, 0, 127, 1, 64);
1992 v4l2_ctrl_new_std(&state->hdl, &cx25840_ctrl_ops,
1993 V4L2_CID_HUE, -128, 127, 1, 0);
1994 if (!is_cx2583x(state)) {
1995 default_volume = cx25840_read(client, 0x8d4);
1996 /*
1997 * Enforce the legacy PVR-350/MSP3400 to PVR-150/CX25843 volume
1998 * scale mapping limits to avoid -ERANGE errors when
1999 * initializing the volume control
2000 */
2001 if (default_volume > 228) {
2002 /* Bottom out at -96 dB, v4l2 vol range 0x2e00-0x2fff */
2003 default_volume = 228;
2004 cx25840_write(client, 0x8d4, 228);
2005 }
2006 else if (default_volume < 20) {
2007 /* Top out at + 8 dB, v4l2 vol range 0xfe00-0xffff */
2008 default_volume = 20;
2009 cx25840_write(client, 0x8d4, 20);
2010 }
2011 default_volume = (((228 - default_volume) >> 1) + 23) << 9;
2012
2013 state->volume = v4l2_ctrl_new_std(&state->hdl,
2014 &cx25840_audio_ctrl_ops, V4L2_CID_AUDIO_VOLUME,
2015 0, 65535, 65535 / 100, default_volume);
2016 state->mute = v4l2_ctrl_new_std(&state->hdl,
2017 &cx25840_audio_ctrl_ops, V4L2_CID_AUDIO_MUTE,
2018 0, 1, 1, 0);
2019 v4l2_ctrl_new_std(&state->hdl, &cx25840_audio_ctrl_ops,
2020 V4L2_CID_AUDIO_BALANCE,
2021 0, 65535, 65535 / 100, 32768);
2022 v4l2_ctrl_new_std(&state->hdl, &cx25840_audio_ctrl_ops,
2023 V4L2_CID_AUDIO_BASS,
2024 0, 65535, 65535 / 100, 32768);
2025 v4l2_ctrl_new_std(&state->hdl, &cx25840_audio_ctrl_ops,
2026 V4L2_CID_AUDIO_TREBLE,
2027 0, 65535, 65535 / 100, 32768);
2028 }
2029 sd->ctrl_handler = &state->hdl;
2030 if (state->hdl.error) {
2031 int err = state->hdl.error;
2032
2033 v4l2_ctrl_handler_free(&state->hdl);
2034 kfree(state);
2035 return err;
2036 }
2037 if (!is_cx2583x(state))
2038 v4l2_ctrl_cluster(2, &state->volume);
2039 v4l2_ctrl_handler_setup(&state->hdl);
2040
2041 if (client->dev.platform_data) {
2042 struct cx25840_platform_data *pdata = client->dev.platform_data;
2043
2044 state->pvr150_workaround = pdata->pvr150_workaround;
2045 }
2046
2047 cx25840_ir_probe(sd);
2048 return 0;
2049 }
2050
2051 static int cx25840_remove(struct i2c_client *client)
2052 {
2053 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2054 struct cx25840_state *state = to_state(sd);
2055
2056 cx25840_ir_remove(sd);
2057 v4l2_device_unregister_subdev(sd);
2058 v4l2_ctrl_handler_free(&state->hdl);
2059 kfree(state);
2060 return 0;
2061 }
2062
2063 static const struct i2c_device_id cx25840_id[] = {
2064 { "cx25840", 0 },
2065 { }
2066 };
2067 MODULE_DEVICE_TABLE(i2c, cx25840_id);
2068
2069 static struct i2c_driver cx25840_driver = {
2070 .driver = {
2071 .owner = THIS_MODULE,
2072 .name = "cx25840",
2073 },
2074 .probe = cx25840_probe,
2075 .remove = cx25840_remove,
2076 .id_table = cx25840_id,
2077 };
2078
2079 static __init int init_cx25840(void)
2080 {
2081 return i2c_add_driver(&cx25840_driver);
2082 }
2083
2084 static __exit void exit_cx25840(void)
2085 {
2086 i2c_del_driver(&cx25840_driver);
2087 }
2088
2089 module_init(init_cx25840);
2090 module_exit(exit_cx25840);