2 * Support for C64x+ Megamodule Interrupt Controller
4 * Copyright (C) 2010, 2011 Texas Instruments Incorporated
5 * Contributed by: Mark Salter <msalter@redhat.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/interrupt.h>
15 #include <linux/of_irq.h>
16 #include <linux/of_address.h>
17 #include <linux/slab.h>
19 #include <asm/megamod-pic.h>
21 #define NR_COMBINERS 4
22 #define NR_MUX_OUTPUTS 12
24 #define IRQ_UNMAPPED 0xffff
27 * Megamodule Interrupt Controller register layout
51 struct irq_host
*irqhost
;
52 struct megamod_regs __iomem
*regs
;
56 unsigned int output_to_irq
[NR_MUX_OUTPUTS
];
59 static struct megamod_pic
*mm_pic
;
61 struct megamod_cascade_data
{
62 struct megamod_pic
*pic
;
66 static struct megamod_cascade_data cascade_data
[NR_COMBINERS
];
68 static void mask_megamod(struct irq_data
*data
)
70 struct megamod_pic
*pic
= irq_data_get_irq_chip_data(data
);
71 irq_hw_number_t src
= irqd_to_hwirq(data
);
72 u32 __iomem
*evtmask
= &pic
->regs
->evtmask
[src
/ 32];
74 raw_spin_lock(&pic
->lock
);
75 soc_writel(soc_readl(evtmask
) | (1 << (src
& 31)), evtmask
);
76 raw_spin_unlock(&pic
->lock
);
79 static void unmask_megamod(struct irq_data
*data
)
81 struct megamod_pic
*pic
= irq_data_get_irq_chip_data(data
);
82 irq_hw_number_t src
= irqd_to_hwirq(data
);
83 u32 __iomem
*evtmask
= &pic
->regs
->evtmask
[src
/ 32];
85 raw_spin_lock(&pic
->lock
);
86 soc_writel(soc_readl(evtmask
) & ~(1 << (src
& 31)), evtmask
);
87 raw_spin_unlock(&pic
->lock
);
90 static struct irq_chip megamod_chip
= {
92 .irq_mask
= mask_megamod
,
93 .irq_unmask
= unmask_megamod
,
96 static void megamod_irq_cascade(unsigned int irq
, struct irq_desc
*desc
)
98 struct megamod_cascade_data
*cascade
;
99 struct megamod_pic
*pic
;
103 cascade
= irq_desc_get_handler_data(desc
);
106 idx
= cascade
->index
;
108 while ((events
= soc_readl(&pic
->regs
->mevtflag
[idx
])) != 0) {
111 irq
= irq_linear_revmap(pic
->irqhost
, idx
* 32 + n
);
113 soc_writel(1 << n
, &pic
->regs
->evtclr
[idx
]);
115 generic_handle_irq(irq
);
119 static int megamod_map(struct irq_host
*h
, unsigned int virq
,
122 struct megamod_pic
*pic
= h
->host_data
;
125 /* We shouldn't see a hwirq which is muxed to core controller */
126 for (i
= 0; i
< NR_MUX_OUTPUTS
; i
++)
127 if (pic
->output_to_irq
[i
] == hw
)
130 irq_set_chip_data(virq
, pic
);
131 irq_set_chip_and_handler(virq
, &megamod_chip
, handle_level_irq
);
133 /* Set default irq type */
134 irq_set_irq_type(virq
, IRQ_TYPE_NONE
);
139 static int megamod_xlate(struct irq_host
*h
, struct device_node
*ct
,
140 const u32
*intspec
, unsigned int intsize
,
141 irq_hw_number_t
*out_hwirq
, unsigned int *out_type
)
144 /* megamod intspecs must have 1 cell */
145 BUG_ON(intsize
!= 1);
146 *out_hwirq
= intspec
[0];
147 *out_type
= IRQ_TYPE_NONE
;
151 static struct irq_host_ops megamod_host_ops
= {
153 .xlate
= megamod_xlate
,
156 static void __init
set_megamod_mux(struct megamod_pic
*pic
, int src
, int output
)
161 if (src
< 0 || src
>= (NR_COMBINERS
* 32)) {
162 pic
->output_to_irq
[output
] = IRQ_UNMAPPED
;
166 /* four mappings per mux register */
168 offset
= (output
& 3) * 8;
170 val
= soc_readl(&pic
->regs
->intmux
[index
]);
171 val
&= ~(0xff << offset
);
172 val
|= src
<< offset
;
173 soc_writel(val
, &pic
->regs
->intmux
[index
]);
177 * Parse the MUX mapping, if one exists.
179 * The MUX map is an array of up to 12 cells; one for each usable core priority
180 * interrupt. The value of a given cell is the megamodule interrupt source
181 * which is to me MUXed to the output corresponding to the cell position
182 * withing the array. The first cell in the array corresponds to priority
183 * 4 and the last (12th) cell corresponds to priority 15. The allowed
184 * values are 4 - ((NR_COMBINERS * 32) - 1). Note that the combined interrupt
185 * sources (0 - 3) are not allowed to be mapped through this property. They
186 * are handled through the "interrupts" property. This allows us to use a
187 * value of zero as a "do not map" placeholder.
189 static void __init
parse_priority_map(struct megamod_pic
*pic
,
190 int *mapping
, int size
)
192 struct device_node
*np
= pic
->irqhost
->of_node
;
197 map
= of_get_property(np
, "ti,c64x+megamod-pic-mux", &maplen
);
203 for (i
= 0; i
< maplen
; i
++) {
204 val
= be32_to_cpup(map
);
212 static struct megamod_pic
* __init
init_megamod_pic(struct device_node
*np
)
214 struct megamod_pic
*pic
;
216 int mapping
[NR_MUX_OUTPUTS
];
218 pr_info("Initializing C64x+ Megamodule PIC\n");
220 pic
= kzalloc(sizeof(struct megamod_pic
), GFP_KERNEL
);
222 pr_err("%s: Could not alloc PIC structure.\n", np
->full_name
);
226 pic
->irqhost
= irq_alloc_host(np
, IRQ_HOST_MAP_LINEAR
,
227 NR_COMBINERS
* 32, &megamod_host_ops
,
230 pr_err("%s: Could not alloc host.\n", np
->full_name
);
234 pic
->irqhost
->host_data
= pic
;
236 raw_spin_lock_init(&pic
->lock
);
238 pic
->regs
= of_iomap(np
, 0);
240 pr_err("%s: Could not map registers.\n", np
->full_name
);
244 /* Initialize MUX map */
245 for (i
= 0; i
< ARRAY_SIZE(mapping
); i
++)
246 mapping
[i
] = IRQ_UNMAPPED
;
248 parse_priority_map(pic
, mapping
, ARRAY_SIZE(mapping
));
251 * We can have up to 12 interrupts cascading to the core controller.
252 * These cascades can be from the combined interrupt sources or for
253 * individual interrupt sources. The "interrupts" property only
254 * deals with the cascaded combined interrupts. The individual
255 * interrupts muxed to the core controller use the core controller
256 * as their interrupt parent.
258 for (i
= 0; i
< NR_COMBINERS
; i
++) {
260 irq
= irq_of_parse_and_map(np
, i
);
265 * We count on the core priority interrupts (4 - 15) being
266 * direct mapped. Check that device tree provided something
269 if (irq
< 4 || irq
>= NR_PRIORITY_IRQS
) {
270 pr_err("%s: combiner-%d virq %d out of range!\n",
271 np
->full_name
, i
, irq
);
275 /* record the mapping */
276 mapping
[irq
- 4] = i
;
278 pr_debug("%s: combiner-%d cascading to virq %d\n",
279 np
->full_name
, i
, irq
);
281 cascade_data
[i
].pic
= pic
;
282 cascade_data
[i
].index
= i
;
284 /* mask and clear all events in combiner */
285 soc_writel(~0, &pic
->regs
->evtmask
[i
]);
286 soc_writel(~0, &pic
->regs
->evtclr
[i
]);
288 irq_set_handler_data(irq
, &cascade_data
[i
]);
289 irq_set_chained_handler(irq
, megamod_irq_cascade
);
292 /* Finally, set up the MUX registers */
293 for (i
= 0; i
< NR_MUX_OUTPUTS
; i
++) {
294 if (mapping
[i
] != IRQ_UNMAPPED
) {
295 pr_debug("%s: setting mux %d to priority %d\n",
296 np
->full_name
, mapping
[i
], i
+ 4);
297 set_megamod_mux(pic
, mapping
[i
], i
);
310 * Return next active event after ACK'ing it.
311 * Return -1 if no events active.
313 static int get_exception(void)
318 for (i
= 0; i
< NR_COMBINERS
; i
++) {
319 mask
= soc_readl(&mm_pic
->regs
->mexpflag
[i
]);
322 soc_writel(1 << bit
, &mm_pic
->regs
->evtclr
[i
]);
323 return (i
* 32) + bit
;
329 static void assert_event(unsigned int val
)
331 soc_writel(val
, &mm_pic
->regs
->evtasrt
);
334 void __init
megamod_pic_init(void)
336 struct device_node
*np
;
338 np
= of_find_compatible_node(NULL
, NULL
, "ti,c64x+megamod-pic");
342 mm_pic
= init_megamod_pic(np
);
345 soc_ops
.get_exception
= get_exception
;
346 soc_ops
.assert_event
= assert_event
;