arch/mips/ath79/setup.c

   1 /*
   2  *  Atheros AR71XX/AR724X/AR913X specific setup
   3  *
   4  *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/bootmem.h>
  17 #include <linux/err.h>
  18 #include <linux/clk.h>
  19
  20 #include <asm/bootinfo.h>
  21 #include <asm/time.h>           /* for mips_hpt_frequency */
  22 #include <asm/reboot.h>         /* for _machine_{restart,halt} */
  23 #include <asm/mips_machine.h>
  24
  25 #include <asm/mach-ath79/ath79.h>
  26 #include <asm/mach-ath79/ar71xx_regs.h>
  27 #include "common.h"
  28 #include "dev-common.h"
  29 #include "machtypes.h"
  30
  31 #define ATH79_SYS_TYPE_LEN      64
  32
  33 #define AR71XX_BASE_FREQ        40000000
  34 #define AR724X_BASE_FREQ        5000000
  35 #define AR913X_BASE_FREQ        5000000
  36
  37 static char ath79_sys_type[ATH79_SYS_TYPE_LEN];
  38
  39 static void ath79_restart(char *command)
  40 {
  41         ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
  42         for (;;)
  43                 if (cpu_wait)
  44                         cpu_wait();
  45 }
  46
  47 static void ath79_halt(void)
  48 {
  49         while (1)
  50                 cpu_wait();
  51 }
  52
  53 static void __init ath79_detect_mem_size(void)
  54 {
  55         unsigned long size;
  56
  57         for (size = ATH79_MEM_SIZE_MIN; size < ATH79_MEM_SIZE_MAX;
  58              size <<= 1) {
  59                 if (!memcmp(ath79_detect_mem_size,
  60                             ath79_detect_mem_size + size, 1024))
  61                         break;
  62         }
  63
  64         add_memory_region(0, size, BOOT_MEM_RAM);
  65 }
  66
  67 static void __init ath79_detect_sys_type(void)
  68 {
  69         char *chip = "????";
  70         u32 id;
  71         u32 major;
  72         u32 minor;
  73         u32 rev = 0;
  74
  75         id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
  76         major = id & REV_ID_MAJOR_MASK;
  77
  78         switch (major) {
  79         case REV_ID_MAJOR_AR71XX:
  80                 minor = id & AR71XX_REV_ID_MINOR_MASK;
  81                 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
  82                 rev &= AR71XX_REV_ID_REVISION_MASK;
  83                 switch (minor) {
  84                 case AR71XX_REV_ID_MINOR_AR7130:
  85                         ath79_soc = ATH79_SOC_AR7130;
  86                         chip = "7130";
  87                         break;
  88
  89                 case AR71XX_REV_ID_MINOR_AR7141:
  90                         ath79_soc = ATH79_SOC_AR7141;
  91                         chip = "7141";
  92                         break;
  93
  94                 case AR71XX_REV_ID_MINOR_AR7161:
  95                         ath79_soc = ATH79_SOC_AR7161;
  96                         chip = "7161";
  97                         break;
  98                 }
  99                 break;
 100
 101         case REV_ID_MAJOR_AR7240:
 102                 ath79_soc = ATH79_SOC_AR7240;
 103                 chip = "7240";
 104                 rev = id & AR724X_REV_ID_REVISION_MASK;
 105                 break;
 106
 107         case REV_ID_MAJOR_AR7241:
 108                 ath79_soc = ATH79_SOC_AR7241;
 109                 chip = "7241";
 110                 rev = id & AR724X_REV_ID_REVISION_MASK;
 111                 break;
 112
 113         case REV_ID_MAJOR_AR7242:
 114                 ath79_soc = ATH79_SOC_AR7242;
 115                 chip = "7242";
 116                 rev = id & AR724X_REV_ID_REVISION_MASK;
 117                 break;
 118
 119         case REV_ID_MAJOR_AR9330:
 120                 ath79_soc = ATH79_SOC_AR9330;
 121                 chip = "9330";
 122                 rev = id & AR933X_REV_ID_REVISION_MASK;
 123                 break;
 124
 125         case REV_ID_MAJOR_AR9331:
 126                 ath79_soc = ATH79_SOC_AR9331;
 127                 chip = "9331";
 128                 rev = id & AR933X_REV_ID_REVISION_MASK;
 129                 break;
 130
 131         case REV_ID_MAJOR_AR913X:
 132                 minor = id & AR913X_REV_ID_MINOR_MASK;
 133                 rev = id >> AR913X_REV_ID_REVISION_SHIFT;
 134                 rev &= AR913X_REV_ID_REVISION_MASK;
 135                 switch (minor) {
 136                 case AR913X_REV_ID_MINOR_AR9130:
 137                         ath79_soc = ATH79_SOC_AR9130;
 138                         chip = "9130";
 139                         break;
 140
 141                 case AR913X_REV_ID_MINOR_AR9132:
 142                         ath79_soc = ATH79_SOC_AR9132;
 143                         chip = "9132";
 144                         break;
 145                 }
 146                 break;
 147
 148         default:
 149                 panic("ath79: unknown SoC, id:0x%08x", id);
 150         }
 151
 152         ath79_soc_rev = rev;
 153
 154         sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
 155         pr_info("SoC: %s\n", ath79_sys_type);
 156 }
 157
 158 const char *get_system_type(void)
 159 {
 160         return ath79_sys_type;
 161 }
 162
 163 unsigned int __cpuinit get_c0_compare_int(void)
 164 {
 165         return CP0_LEGACY_COMPARE_IRQ;
 166 }
 167
 168 void __init plat_mem_setup(void)
 169 {
 170         set_io_port_base(KSEG1);
 171
 172         ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
 173                                            AR71XX_RESET_SIZE);
 174         ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
 175                                          AR71XX_PLL_SIZE);
 176         ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
 177                                          AR71XX_DDR_CTRL_SIZE);
 178
 179         ath79_detect_sys_type();
 180         ath79_detect_mem_size();
 181         ath79_clocks_init();
 182
 183         _machine_restart = ath79_restart;
 184         _machine_halt = ath79_halt;
 185         pm_power_off = ath79_halt;
 186 }
 187
 188 void __init plat_time_init(void)
 189 {
 190         struct clk *clk;
 191
 192         clk = clk_get(NULL, "cpu");
 193         if (IS_ERR(clk))
 194                 panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
 195
 196         mips_hpt_frequency = clk_get_rate(clk) / 2;
 197 }
 198
 199 static int __init ath79_setup(void)
 200 {
 201         ath79_gpio_init();
 202         ath79_register_uart();
 203         ath79_register_wdt();
 204
 205         mips_machine_setup();
 206
 207         return 0;
 208 }
 209
 210 arch_initcall(ath79_setup);
 211
 212 static void __init ath79_generic_init(void)
 213 {
 214         /* Nothing to do */
 215 }
 216
 217 MIPS_MACHINE(ATH79_MACH_GENERIC,
 218              "Generic",
 219              "Generic AR71XX/AR724X/AR913X based board",
 220              ath79_generic_init);