arch/mips/include/asm/mach-pnx833x/gpio.h

   1 /*
   2  *  gpio.h: GPIO Support for PNX833X.
   3  *
   4  *  Copyright 2008 NXP Semiconductors
   5  *        Chris Steel <chris.steel@nxp.com>
   6  *    Daniel Laird <daniel.j.laird@nxp.com>
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License as published by
  10  *  the Free Software Foundation; either version 2 of the License, or
  11  *  (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful,
  14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *  GNU General Public License for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License
  19  *  along with this program; if not, write to the Free Software
  20  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22 #ifndef __ASM_MIPS_MACH_PNX833X_GPIO_H
  23 #define __ASM_MIPS_MACH_PNX833X_GPIO_H
  24
  25 /* BIG FAT WARNING: races danger!
  26    No protections exist here. Current users are only early init code,
  27    when locking is not needed because no concurrency yet exists there,
  28    and GPIO IRQ dispatcher, which does locking.
  29    However, if many uses will ever happen, proper locking will be needed
  30    - including locking between different uses
  31 */
  32
  33 #include "pnx833x.h"
  34
  35 #define SET_REG_BIT(reg, bit)           do { (reg |= (1 << (bit))); } while (0)
  36 #define CLEAR_REG_BIT(reg, bit)         do { (reg &= ~(1 << (bit))); } while (0)
  37
  38 /* Initialize GPIO to a known state */
  39 static inline void pnx833x_gpio_init(void)
  40 {
  41         PNX833X_PIO_DIR = 0;
  42         PNX833X_PIO_DIR2 = 0;
  43         PNX833X_PIO_SEL = 0;
  44         PNX833X_PIO_SEL2 = 0;
  45         PNX833X_PIO_INT_EDGE = 0;
  46         PNX833X_PIO_INT_HI = 0;
  47         PNX833X_PIO_INT_LO = 0;
  48
  49         /* clear any GPIO interrupt requests */
  50         PNX833X_PIO_INT_CLEAR = 0xffff;
  51         PNX833X_PIO_INT_CLEAR = 0;
  52         PNX833X_PIO_INT_ENABLE = 0;
  53 }
  54
  55 /* Select GPIO direction for a pin */
  56 static inline void pnx833x_gpio_select_input(unsigned int pin)
  57 {
  58         if (pin < 32)
  59                 CLEAR_REG_BIT(PNX833X_PIO_DIR, pin);
  60         else
  61                 CLEAR_REG_BIT(PNX833X_PIO_DIR2, pin & 31);
  62 }
  63 static inline void pnx833x_gpio_select_output(unsigned int pin)
  64 {
  65         if (pin < 32)
  66                 SET_REG_BIT(PNX833X_PIO_DIR, pin);
  67         else
  68                 SET_REG_BIT(PNX833X_PIO_DIR2, pin & 31);
  69 }
  70
  71 /* Select GPIO or alternate function for a pin */
  72 static inline void pnx833x_gpio_select_function_io(unsigned int pin)
  73 {
  74         if (pin < 32)
  75                 CLEAR_REG_BIT(PNX833X_PIO_SEL, pin);
  76         else
  77                 CLEAR_REG_BIT(PNX833X_PIO_SEL2, pin & 31);
  78 }
  79 static inline void pnx833x_gpio_select_function_alt(unsigned int pin)
  80 {
  81         if (pin < 32)
  82                 SET_REG_BIT(PNX833X_PIO_SEL, pin);
  83         else
  84                 SET_REG_BIT(PNX833X_PIO_SEL2, pin & 31);
  85 }
  86
  87 /* Read GPIO pin */
  88 static inline int pnx833x_gpio_read(unsigned int pin)
  89 {
  90         if (pin < 32)
  91                 return (PNX833X_PIO_IN >> pin) & 1;
  92         else
  93                 return (PNX833X_PIO_IN2 >> (pin & 31)) & 1;
  94 }
  95
  96 /* Write GPIO pin */
  97 static inline void pnx833x_gpio_write(unsigned int val, unsigned int pin)
  98 {
  99         if (pin < 32) {
 100                 if (val)
 101                         SET_REG_BIT(PNX833X_PIO_OUT, pin);
 102                 else
 103                         CLEAR_REG_BIT(PNX833X_PIO_OUT, pin);
 104         } else {
 105                 if (val)
 106                         SET_REG_BIT(PNX833X_PIO_OUT2, pin & 31);
 107                 else
 108                         CLEAR_REG_BIT(PNX833X_PIO_OUT2, pin & 31);
 109         }
 110 }
 111
 112 /* Configure GPIO interrupt */
 113 #define GPIO_INT_NONE           0
 114 #define GPIO_INT_LEVEL_LOW      1
 115 #define GPIO_INT_LEVEL_HIGH     2
 116 #define GPIO_INT_EDGE_RISING    3
 117 #define GPIO_INT_EDGE_FALLING   4
 118 #define GPIO_INT_EDGE_BOTH      5
 119 static inline void pnx833x_gpio_setup_irq(int when, unsigned int pin)
 120 {
 121         switch (when) {
 122         case GPIO_INT_LEVEL_LOW:
 123                 CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
 124                 CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
 125                 SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
 126                 break;
 127         case GPIO_INT_LEVEL_HIGH:
 128                 CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
 129                 SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
 130                 CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
 131                 break;
 132         case GPIO_INT_EDGE_RISING:
 133                 SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
 134                 SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
 135                 CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
 136                 break;
 137         case GPIO_INT_EDGE_FALLING:
 138                 SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
 139                 CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
 140                 SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
 141                 break;
 142         case GPIO_INT_EDGE_BOTH:
 143                 SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
 144                 SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
 145                 SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
 146                 break;
 147         default:
 148                 CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
 149                 CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
 150                 CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
 151                 break;
 152         }
 153 }
 154
 155 /* Enable/disable GPIO interrupt */
 156 static inline void pnx833x_gpio_enable_irq(unsigned int pin)
 157 {
 158         SET_REG_BIT(PNX833X_PIO_INT_ENABLE, pin);
 159 }
 160 static inline void pnx833x_gpio_disable_irq(unsigned int pin)
 161 {
 162         CLEAR_REG_BIT(PNX833X_PIO_INT_ENABLE, pin);
 163 }
 164
 165 /* Clear GPIO interrupt request */
 166 static inline void pnx833x_gpio_clear_irq(unsigned int pin)
 167 {
 168         SET_REG_BIT(PNX833X_PIO_INT_CLEAR, pin);
 169         CLEAR_REG_BIT(PNX833X_PIO_INT_CLEAR, pin);
 170 }
 171
 172 #endif