drivers/media/dvb/ddbridge/ddbridge-regs.h

   1 /*
   2  * ddbridge-regs.h: Digital Devices PCIe bridge driver
   3  *
   4  * Copyright (C) 2010-2011 Digital Devices GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 only, as published by the Free Software Foundation.
   9  *
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  20  * 02110-1301, USA
  21  * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
  22  */
  23
  24 /* DD-DVBBridgeV1.h 273 2010-09-17 05:03:16Z manfred */
  25
  26 /* Register Definitions */
  27
  28 #define CUR_REGISTERMAP_VERSION 0x10000
  29
  30 #define HARDWARE_VERSION       0x00
  31 #define REGISTERMAP_VERSION    0x04
  32
  33 /* ------------------------------------------------------------------------- */
  34 /* SPI Controller */
  35
  36 #define SPI_CONTROL     0x10
  37 #define SPI_DATA        0x14
  38
  39 /* ------------------------------------------------------------------------- */
  40
  41 /* Interrupt controller                                     */
  42 /* How many MSI's are available depends on HW (Min 2 max 8) */
  43 /* How many are usable also depends on Host platform        */
  44
  45 #define INTERRUPT_BASE   (0x40)
  46
  47 #define INTERRUPT_ENABLE (INTERRUPT_BASE + 0x00)
  48 #define MSI0_ENABLE      (INTERRUPT_BASE + 0x00)
  49 #define MSI1_ENABLE      (INTERRUPT_BASE + 0x04)
  50 #define MSI2_ENABLE      (INTERRUPT_BASE + 0x08)
  51 #define MSI3_ENABLE      (INTERRUPT_BASE + 0x0C)
  52 #define MSI4_ENABLE      (INTERRUPT_BASE + 0x10)
  53 #define MSI5_ENABLE      (INTERRUPT_BASE + 0x14)
  54 #define MSI6_ENABLE      (INTERRUPT_BASE + 0x18)
  55 #define MSI7_ENABLE      (INTERRUPT_BASE + 0x1C)
  56
  57 #define INTERRUPT_STATUS (INTERRUPT_BASE + 0x20)
  58 #define INTERRUPT_ACK    (INTERRUPT_BASE + 0x20)
  59
  60 #define INTMASK_I2C1        (0x00000001)
  61 #define INTMASK_I2C2        (0x00000002)
  62 #define INTMASK_I2C3        (0x00000004)
  63 #define INTMASK_I2C4        (0x00000008)
  64
  65 #define INTMASK_CIRQ1       (0x00000010)
  66 #define INTMASK_CIRQ2       (0x00000020)
  67 #define INTMASK_CIRQ3       (0x00000040)
  68 #define INTMASK_CIRQ4       (0x00000080)
  69
  70 #define INTMASK_TSINPUT1    (0x00000100)
  71 #define INTMASK_TSINPUT2    (0x00000200)
  72 #define INTMASK_TSINPUT3    (0x00000400)
  73 #define INTMASK_TSINPUT4    (0x00000800)
  74 #define INTMASK_TSINPUT5    (0x00001000)
  75 #define INTMASK_TSINPUT6    (0x00002000)
  76 #define INTMASK_TSINPUT7    (0x00004000)
  77 #define INTMASK_TSINPUT8    (0x00008000)
  78
  79 #define INTMASK_TSOUTPUT1   (0x00010000)
  80 #define INTMASK_TSOUTPUT2   (0x00020000)
  81 #define INTMASK_TSOUTPUT3   (0x00040000)
  82 #define INTMASK_TSOUTPUT4   (0x00080000)
  83
  84 /* ------------------------------------------------------------------------- */
  85 /* I2C Master Controller */
  86
  87 #define I2C_BASE        (0x80)  /* Byte offset */
  88
  89 #define I2C_COMMAND     (0x00)
  90 #define I2C_TIMING      (0x04)
  91 #define I2C_TASKLENGTH  (0x08)     /* High read, low write */
  92 #define I2C_TASKADDRESS (0x0C)     /* High read, low write */
  93
  94 #define I2C_MONITOR     (0x1C)
  95
  96 #define I2C_BASE_1      (I2C_BASE + 0x00)
  97 #define I2C_BASE_2      (I2C_BASE + 0x20)
  98 #define I2C_BASE_3      (I2C_BASE + 0x40)
  99 #define I2C_BASE_4      (I2C_BASE + 0x60)
 100
 101 #define I2C_BASE_N(i)   (I2C_BASE + (i) * 0x20)
 102
 103 #define I2C_TASKMEM_BASE    (0x1000)    /* Byte offset */
 104 #define I2C_TASKMEM_SIZE    (0x1000)
 105
 106 #define I2C_SPEED_400   (0x04030404)
 107 #define I2C_SPEED_200   (0x09080909)
 108 #define I2C_SPEED_154   (0x0C0B0C0C)
 109 #define I2C_SPEED_100   (0x13121313)
 110 #define I2C_SPEED_77    (0x19181919)
 111 #define I2C_SPEED_50    (0x27262727)
 112
 113
 114 /* ------------------------------------------------------------------------- */
 115 /* DMA  Controller */
 116
 117 #define DMA_BASE_WRITE        (0x100)
 118 #define DMA_BASE_READ         (0x140)
 119
 120 #define DMA_CONTROL     (0x00)                  /* 64 */
 121 #define DMA_ERROR       (0x04)                  /* 65 ( only read instance ) */
 122
 123 #define DMA_DIAG_CONTROL                (0x1C)  /* 71 */
 124 #define DMA_DIAG_PACKETCOUNTER_LOW      (0x20)  /* 72 */
 125 #define DMA_DIAG_PACKETCOUNTER_HIGH     (0x24)  /* 73 */
 126 #define DMA_DIAG_TIMECOUNTER_LOW        (0x28)  /* 74 */
 127 #define DMA_DIAG_TIMECOUNTER_HIGH       (0x2C)  /* 75 */
 128 #define DMA_DIAG_RECHECKCOUNTER         (0x30)  /* 76  ( Split completions on read ) */
 129 #define DMA_DIAG_WAITTIMEOUTINIT        (0x34)  /* 77 */
 130 #define DMA_DIAG_WAITOVERFLOWCOUNTER    (0x38)  /* 78 */
 131 #define DMA_DIAG_WAITCOUNTER            (0x3C)  /* 79 */
 132
 133 /* ------------------------------------------------------------------------- */
 134 /* DMA  Buffer */
 135
 136 #define TS_INPUT_BASE       (0x200)
 137 #define TS_INPUT_CONTROL(i)         (TS_INPUT_BASE + (i) * 16 + 0x00)
 138
 139 #define TS_OUTPUT_BASE       (0x280)
 140 #define TS_OUTPUT_CONTROL(i)         (TS_OUTPUT_BASE + (i) * 16 + 0x00)
 141
 142 #define DMA_BUFFER_BASE     (0x300)
 143
 144 #define DMA_BUFFER_CONTROL(i)       (DMA_BUFFER_BASE + (i) * 16 + 0x00)
 145 #define DMA_BUFFER_ACK(i)           (DMA_BUFFER_BASE + (i) * 16 + 0x04)
 146 #define DMA_BUFFER_CURRENT(i)       (DMA_BUFFER_BASE + (i) * 16 + 0x08)
 147 #define DMA_BUFFER_SIZE(i)          (DMA_BUFFER_BASE + (i) * 16 + 0x0c)
 148
 149 #define DMA_BASE_ADDRESS_TABLE  (0x2000)
 150 #define DMA_BASE_ADDRESS_TABLE_ENTRIES (512)
 151