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Avoid beyond bounds copy while caching ACL
[zen-stable.git] / drivers / media / video / ov772x.c
blob9f6ce3d8a29efc9f1652cb21e8f9768ddc2ea345
1 /*
2 * ov772x Camera Driver
3 *
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ov7670 and soc_camera_platform driver,
8 *
9 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
10 * Copyright (C) 2008 Magnus Damm
11 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/i2c.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/v4l2-mediabus.h>
24 #include <linux/videodev2.h>
25
26 #include <media/ov772x.h>
27 #include <media/soc_camera.h>
28 #include <media/v4l2-ctrls.h>
29 #include <media/v4l2-chip-ident.h>
30 #include <media/v4l2-subdev.h>
31
32 /*
33 * register offset
34 */
35 #define GAIN 0x00 /* AGC - Gain control gain setting */
36 #define BLUE 0x01 /* AWB - Blue channel gain setting */
37 #define RED 0x02 /* AWB - Red channel gain setting */
38 #define GREEN 0x03 /* AWB - Green channel gain setting */
39 #define COM1 0x04 /* Common control 1 */
40 #define BAVG 0x05 /* U/B Average Level */
41 #define GAVG 0x06 /* Y/Gb Average Level */
42 #define RAVG 0x07 /* V/R Average Level */
43 #define AECH 0x08 /* Exposure Value - AEC MSBs */
44 #define COM2 0x09 /* Common control 2 */
45 #define PID 0x0A /* Product ID Number MSB */
46 #define VER 0x0B /* Product ID Number LSB */
47 #define COM3 0x0C /* Common control 3 */
48 #define COM4 0x0D /* Common control 4 */
49 #define COM5 0x0E /* Common control 5 */
50 #define COM6 0x0F /* Common control 6 */
51 #define AEC 0x10 /* Exposure Value */
52 #define CLKRC 0x11 /* Internal clock */
53 #define COM7 0x12 /* Common control 7 */
54 #define COM8 0x13 /* Common control 8 */
55 #define COM9 0x14 /* Common control 9 */
56 #define COM10 0x15 /* Common control 10 */
57 #define REG16 0x16 /* Register 16 */
58 #define HSTART 0x17 /* Horizontal sensor size */
59 #define HSIZE 0x18 /* Horizontal frame (HREF column) end high 8-bit */
60 #define VSTART 0x19 /* Vertical frame (row) start high 8-bit */
61 #define VSIZE 0x1A /* Vertical sensor size */
62 #define PSHFT 0x1B /* Data format - pixel delay select */
63 #define MIDH 0x1C /* Manufacturer ID byte - high */
64 #define MIDL 0x1D /* Manufacturer ID byte - low */
65 #define LAEC 0x1F /* Fine AEC value */
66 #define COM11 0x20 /* Common control 11 */
67 #define BDBASE 0x22 /* Banding filter Minimum AEC value */
68 #define DBSTEP 0x23 /* Banding filter Maximum Setp */
69 #define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */
70 #define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */
71 #define VPT 0x26 /* AGC/AEC Fast mode operating region */
72 #define REG28 0x28 /* Register 28 */
73 #define HOUTSIZE 0x29 /* Horizontal data output size MSBs */
74 #define EXHCH 0x2A /* Dummy pixel insert MSB */
75 #define EXHCL 0x2B /* Dummy pixel insert LSB */
76 #define VOUTSIZE 0x2C /* Vertical data output size MSBs */
77 #define ADVFL 0x2D /* LSB of insert dummy lines in Vertical direction */
78 #define ADVFH 0x2E /* MSG of insert dummy lines in Vertical direction */
79 #define YAVE 0x2F /* Y/G Channel Average value */
80 #define LUMHTH 0x30 /* Histogram AEC/AGC Luminance high level threshold */
81 #define LUMLTH 0x31 /* Histogram AEC/AGC Luminance low level threshold */
82 #define HREF 0x32 /* Image start and size control */
83 #define DM_LNL 0x33 /* Dummy line low 8 bits */
84 #define DM_LNH 0x34 /* Dummy line high 8 bits */
85 #define ADOFF_B 0x35 /* AD offset compensation value for B channel */
86 #define ADOFF_R 0x36 /* AD offset compensation value for R channel */
87 #define ADOFF_GB 0x37 /* AD offset compensation value for Gb channel */
88 #define ADOFF_GR 0x38 /* AD offset compensation value for Gr channel */
89 #define OFF_B 0x39 /* Analog process B channel offset value */
90 #define OFF_R 0x3A /* Analog process R channel offset value */
91 #define OFF_GB 0x3B /* Analog process Gb channel offset value */
92 #define OFF_GR 0x3C /* Analog process Gr channel offset value */
93 #define COM12 0x3D /* Common control 12 */
94 #define COM13 0x3E /* Common control 13 */
95 #define COM14 0x3F /* Common control 14 */
96 #define COM15 0x40 /* Common control 15*/
97 #define COM16 0x41 /* Common control 16 */
98 #define TGT_B 0x42 /* BLC blue channel target value */
99 #define TGT_R 0x43 /* BLC red channel target value */
100 #define TGT_GB 0x44 /* BLC Gb channel target value */
101 #define TGT_GR 0x45 /* BLC Gr channel target value */
102 /* for ov7720 */
103 #define LCC0 0x46 /* Lens correction control 0 */
104 #define LCC1 0x47 /* Lens correction option 1 - X coordinate */
105 #define LCC2 0x48 /* Lens correction option 2 - Y coordinate */
106 #define LCC3 0x49 /* Lens correction option 3 */
107 #define LCC4 0x4A /* Lens correction option 4 - radius of the circular */
108 #define LCC5 0x4B /* Lens correction option 5 */
109 #define LCC6 0x4C /* Lens correction option 6 */
110 /* for ov7725 */
111 #define LC_CTR 0x46 /* Lens correction control */
112 #define LC_XC 0x47 /* X coordinate of lens correction center relative */
113 #define LC_YC 0x48 /* Y coordinate of lens correction center relative */
114 #define LC_COEF 0x49 /* Lens correction coefficient */
115 #define LC_RADI 0x4A /* Lens correction radius */
116 #define LC_COEFB 0x4B /* Lens B channel compensation coefficient */
117 #define LC_COEFR 0x4C /* Lens R channel compensation coefficient */
118
119 #define FIXGAIN 0x4D /* Analog fix gain amplifer */
120 #define AREF0 0x4E /* Sensor reference control */
121 #define AREF1 0x4F /* Sensor reference current control */
122 #define AREF2 0x50 /* Analog reference control */
123 #define AREF3 0x51 /* ADC reference control */
124 #define AREF4 0x52 /* ADC reference control */
125 #define AREF5 0x53 /* ADC reference control */
126 #define AREF6 0x54 /* Analog reference control */
127 #define AREF7 0x55 /* Analog reference control */
128 #define UFIX 0x60 /* U channel fixed value output */
129 #define VFIX 0x61 /* V channel fixed value output */
130 #define AWBB_BLK 0x62 /* AWB option for advanced AWB */
131 #define AWB_CTRL0 0x63 /* AWB control byte 0 */
132 #define DSP_CTRL1 0x64 /* DSP control byte 1 */
133 #define DSP_CTRL2 0x65 /* DSP control byte 2 */
134 #define DSP_CTRL3 0x66 /* DSP control byte 3 */
135 #define DSP_CTRL4 0x67 /* DSP control byte 4 */
136 #define AWB_BIAS 0x68 /* AWB BLC level clip */
137 #define AWB_CTRL1 0x69 /* AWB control 1 */
138 #define AWB_CTRL2 0x6A /* AWB control 2 */
139 #define AWB_CTRL3 0x6B /* AWB control 3 */
140 #define AWB_CTRL4 0x6C /* AWB control 4 */
141 #define AWB_CTRL5 0x6D /* AWB control 5 */
142 #define AWB_CTRL6 0x6E /* AWB control 6 */
143 #define AWB_CTRL7 0x6F /* AWB control 7 */
144 #define AWB_CTRL8 0x70 /* AWB control 8 */
145 #define AWB_CTRL9 0x71 /* AWB control 9 */
146 #define AWB_CTRL10 0x72 /* AWB control 10 */
147 #define AWB_CTRL11 0x73 /* AWB control 11 */
148 #define AWB_CTRL12 0x74 /* AWB control 12 */
149 #define AWB_CTRL13 0x75 /* AWB control 13 */
150 #define AWB_CTRL14 0x76 /* AWB control 14 */
151 #define AWB_CTRL15 0x77 /* AWB control 15 */
152 #define AWB_CTRL16 0x78 /* AWB control 16 */
153 #define AWB_CTRL17 0x79 /* AWB control 17 */
154 #define AWB_CTRL18 0x7A /* AWB control 18 */
155 #define AWB_CTRL19 0x7B /* AWB control 19 */
156 #define AWB_CTRL20 0x7C /* AWB control 20 */
157 #define AWB_CTRL21 0x7D /* AWB control 21 */
158 #define GAM1 0x7E /* Gamma Curve 1st segment input end point */
159 #define GAM2 0x7F /* Gamma Curve 2nd segment input end point */
160 #define GAM3 0x80 /* Gamma Curve 3rd segment input end point */
161 #define GAM4 0x81 /* Gamma Curve 4th segment input end point */
162 #define GAM5 0x82 /* Gamma Curve 5th segment input end point */
163 #define GAM6 0x83 /* Gamma Curve 6th segment input end point */
164 #define GAM7 0x84 /* Gamma Curve 7th segment input end point */
165 #define GAM8 0x85 /* Gamma Curve 8th segment input end point */
166 #define GAM9 0x86 /* Gamma Curve 9th segment input end point */
167 #define GAM10 0x87 /* Gamma Curve 10th segment input end point */
168 #define GAM11 0x88 /* Gamma Curve 11th segment input end point */
169 #define GAM12 0x89 /* Gamma Curve 12th segment input end point */
170 #define GAM13 0x8A /* Gamma Curve 13th segment input end point */
171 #define GAM14 0x8B /* Gamma Curve 14th segment input end point */
172 #define GAM15 0x8C /* Gamma Curve 15th segment input end point */
173 #define SLOP 0x8D /* Gamma curve highest segment slope */
174 #define DNSTH 0x8E /* De-noise threshold */
175 #define EDGE_STRNGT 0x8F /* Edge strength control when manual mode */
176 #define EDGE_TRSHLD 0x90 /* Edge threshold control when manual mode */
177 #define DNSOFF 0x91 /* Auto De-noise threshold control */
178 #define EDGE_UPPER 0x92 /* Edge strength upper limit when Auto mode */
179 #define EDGE_LOWER 0x93 /* Edge strength lower limit when Auto mode */
180 #define MTX1 0x94 /* Matrix coefficient 1 */
181 #define MTX2 0x95 /* Matrix coefficient 2 */
182 #define MTX3 0x96 /* Matrix coefficient 3 */
183 #define MTX4 0x97 /* Matrix coefficient 4 */
184 #define MTX5 0x98 /* Matrix coefficient 5 */
185 #define MTX6 0x99 /* Matrix coefficient 6 */
186 #define MTX_CTRL 0x9A /* Matrix control */
187 #define BRIGHT 0x9B /* Brightness control */
188 #define CNTRST 0x9C /* Contrast contrast */
189 #define CNTRST_CTRL 0x9D /* Contrast contrast center */
190 #define UVAD_J0 0x9E /* Auto UV adjust contrast 0 */
191 #define UVAD_J1 0x9F /* Auto UV adjust contrast 1 */
192 #define SCAL0 0xA0 /* Scaling control 0 */
193 #define SCAL1 0xA1 /* Scaling control 1 */
194 #define SCAL2 0xA2 /* Scaling control 2 */
195 #define FIFODLYM 0xA3 /* FIFO manual mode delay control */
196 #define FIFODLYA 0xA4 /* FIFO auto mode delay control */
197 #define SDE 0xA6 /* Special digital effect control */
198 #define USAT 0xA7 /* U component saturation control */
199 #define VSAT 0xA8 /* V component saturation control */
200 /* for ov7720 */
201 #define HUE0 0xA9 /* Hue control 0 */
202 #define HUE1 0xAA /* Hue control 1 */
203 /* for ov7725 */
204 #define HUECOS 0xA9 /* Cosine value */
205 #define HUESIN 0xAA /* Sine value */
206
207 #define SIGN 0xAB /* Sign bit for Hue and contrast */
208 #define DSPAUTO 0xAC /* DSP auto function ON/OFF control */
209
210 /*
211 * register detail
212 */
213
214 /* COM2 */
215 #define SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */
216 /* Output drive capability */
217 #define OCAP_1x 0x00 /* 1x */
218 #define OCAP_2x 0x01 /* 2x */
219 #define OCAP_3x 0x02 /* 3x */
220 #define OCAP_4x 0x03 /* 4x */
221
222 /* COM3 */
223 #define SWAP_MASK (SWAP_RGB | SWAP_YUV | SWAP_ML)
224 #define IMG_MASK (VFLIP_IMG | HFLIP_IMG)
225
226 #define VFLIP_IMG 0x80 /* Vertical flip image ON/OFF selection */
227 #define HFLIP_IMG 0x40 /* Horizontal mirror image ON/OFF selection */
228 #define SWAP_RGB 0x20 /* Swap B/R output sequence in RGB mode */
229 #define SWAP_YUV 0x10 /* Swap Y/UV output sequence in YUV mode */
230 #define SWAP_ML 0x08 /* Swap output MSB/LSB */
231 /* Tri-state option for output clock */
232 #define NOTRI_CLOCK 0x04 /* 0: Tri-state at this period */
233 /* 1: No tri-state at this period */
234 /* Tri-state option for output data */
235 #define NOTRI_DATA 0x02 /* 0: Tri-state at this period */
236 /* 1: No tri-state at this period */
237 #define SCOLOR_TEST 0x01 /* Sensor color bar test pattern */
238
239 /* COM4 */
240 /* PLL frequency control */
241 #define PLL_BYPASS 0x00 /* 00: Bypass PLL */
242 #define PLL_4x 0x40 /* 01: PLL 4x */
243 #define PLL_6x 0x80 /* 10: PLL 6x */
244 #define PLL_8x 0xc0 /* 11: PLL 8x */
245 /* AEC evaluate window */
246 #define AEC_FULL 0x00 /* 00: Full window */
247 #define AEC_1p2 0x10 /* 01: 1/2 window */
248 #define AEC_1p4 0x20 /* 10: 1/4 window */
249 #define AEC_2p3 0x30 /* 11: Low 2/3 window */
250
251 /* COM5 */
252 #define AFR_ON_OFF 0x80 /* Auto frame rate control ON/OFF selection */
253 #define AFR_SPPED 0x40 /* Auto frame rate control speed selection */
254 /* Auto frame rate max rate control */
255 #define AFR_NO_RATE 0x00 /* No reduction of frame rate */
256 #define AFR_1p2 0x10 /* Max reduction to 1/2 frame rate */
257 #define AFR_1p4 0x20 /* Max reduction to 1/4 frame rate */
258 #define AFR_1p8 0x30 /* Max reduction to 1/8 frame rate */
259 /* Auto frame rate active point control */
260 #define AF_2x 0x00 /* Add frame when AGC reaches 2x gain */
261 #define AF_4x 0x04 /* Add frame when AGC reaches 4x gain */
262 #define AF_8x 0x08 /* Add frame when AGC reaches 8x gain */
263 #define AF_16x 0x0c /* Add frame when AGC reaches 16x gain */
264 /* AEC max step control */
265 #define AEC_NO_LIMIT 0x01 /* 0 : AEC incease step has limit */
266 /* 1 : No limit to AEC increase step */
267
268 /* COM7 */
269 /* SCCB Register Reset */
270 #define SCCB_RESET 0x80 /* 0 : No change */
271 /* 1 : Resets all registers to default */
272 /* Resolution selection */
273 #define SLCT_MASK 0x40 /* Mask of VGA or QVGA */
274 #define SLCT_VGA 0x00 /* 0 : VGA */
275 #define SLCT_QVGA 0x40 /* 1 : QVGA */
276 #define ITU656_ON_OFF 0x20 /* ITU656 protocol ON/OFF selection */
277 /* RGB output format control */
278 #define FMT_MASK 0x0c /* Mask of color format */
279 #define FMT_GBR422 0x00 /* 00 : GBR 4:2:2 */
280 #define FMT_RGB565 0x04 /* 01 : RGB 565 */
281 #define FMT_RGB555 0x08 /* 10 : RGB 555 */
282 #define FMT_RGB444 0x0c /* 11 : RGB 444 */
283 /* Output format control */
284 #define OFMT_MASK 0x03 /* Mask of output format */
285 #define OFMT_YUV 0x00 /* 00 : YUV */
286 #define OFMT_P_BRAW 0x01 /* 01 : Processed Bayer RAW */
287 #define OFMT_RGB 0x02 /* 10 : RGB */
288 #define OFMT_BRAW 0x03 /* 11 : Bayer RAW */
289
290 /* COM8 */
291 #define FAST_ALGO 0x80 /* Enable fast AGC/AEC algorithm */
292 /* AEC Setp size limit */
293 #define UNLMT_STEP 0x40 /* 0 : Step size is limited */
294 /* 1 : Unlimited step size */
295 #define BNDF_ON_OFF 0x20 /* Banding filter ON/OFF */
296 #define AEC_BND 0x10 /* Enable AEC below banding value */
297 #define AEC_ON_OFF 0x08 /* Fine AEC ON/OFF control */
298 #define AGC_ON 0x04 /* AGC Enable */
299 #define AWB_ON 0x02 /* AWB Enable */
300 #define AEC_ON 0x01 /* AEC Enable */
301
302 /* COM9 */
303 #define BASE_AECAGC 0x80 /* Histogram or average based AEC/AGC */
304 /* Automatic gain ceiling - maximum AGC value */
305 #define GAIN_2x 0x00 /* 000 : 2x */
306 #define GAIN_4x 0x10 /* 001 : 4x */
307 #define GAIN_8x 0x20 /* 010 : 8x */
308 #define GAIN_16x 0x30 /* 011 : 16x */
309 #define GAIN_32x 0x40 /* 100 : 32x */
310 #define GAIN_64x 0x50 /* 101 : 64x */
311 #define GAIN_128x 0x60 /* 110 : 128x */
312 #define DROP_VSYNC 0x04 /* Drop VSYNC output of corrupt frame */
313 #define DROP_HREF 0x02 /* Drop HREF output of corrupt frame */
314
315 /* COM11 */
316 #define SGLF_ON_OFF 0x02 /* Single frame ON/OFF selection */
317 #define SGLF_TRIG 0x01 /* Single frame transfer trigger */
318
319 /* EXHCH */
320 #define VSIZE_LSB 0x04 /* Vertical data output size LSB */
321
322 /* DSP_CTRL1 */
323 #define FIFO_ON 0x80 /* FIFO enable/disable selection */
324 #define UV_ON_OFF 0x40 /* UV adjust function ON/OFF selection */
325 #define YUV444_2_422 0x20 /* YUV444 to 422 UV channel option selection */
326 #define CLR_MTRX_ON_OFF 0x10 /* Color matrix ON/OFF selection */
327 #define INTPLT_ON_OFF 0x08 /* Interpolation ON/OFF selection */
328 #define GMM_ON_OFF 0x04 /* Gamma function ON/OFF selection */
329 #define AUTO_BLK_ON_OFF 0x02 /* Black defect auto correction ON/OFF */
330 #define AUTO_WHT_ON_OFF 0x01 /* White define auto correction ON/OFF */
331
332 /* DSP_CTRL3 */
333 #define UV_MASK 0x80 /* UV output sequence option */
334 #define UV_ON 0x80 /* ON */
335 #define UV_OFF 0x00 /* OFF */
336 #define CBAR_MASK 0x20 /* DSP Color bar mask */
337 #define CBAR_ON 0x20 /* ON */
338 #define CBAR_OFF 0x00 /* OFF */
339
340 /* HSTART */
341 #define HST_VGA 0x23
342 #define HST_QVGA 0x3F
343
344 /* HSIZE */
345 #define HSZ_VGA 0xA0
346 #define HSZ_QVGA 0x50
347
348 /* VSTART */
349 #define VST_VGA 0x07
350 #define VST_QVGA 0x03
351
352 /* VSIZE */
353 #define VSZ_VGA 0xF0
354 #define VSZ_QVGA 0x78
355
356 /* HOUTSIZE */
357 #define HOSZ_VGA 0xA0
358 #define HOSZ_QVGA 0x50
359
360 /* VOUTSIZE */
361 #define VOSZ_VGA 0xF0
362 #define VOSZ_QVGA 0x78
363
364 /* DSPAUTO (DSP Auto Function ON/OFF Control) */
365 #define AWB_ACTRL 0x80 /* AWB auto threshold control */
366 #define DENOISE_ACTRL 0x40 /* De-noise auto threshold control */
367 #define EDGE_ACTRL 0x20 /* Edge enhancement auto strength control */
368 #define UV_ACTRL 0x10 /* UV adjust auto slope control */
369 #define SCAL0_ACTRL 0x08 /* Auto scaling factor control */
370 #define SCAL1_2_ACTRL 0x04 /* Auto scaling factor control */
371
372 /*
373 * ID
374 */
375 #define OV7720 0x7720
376 #define OV7725 0x7721
377 #define VERSION(pid, ver) ((pid<<8)|(ver&0xFF))
378
379 /*
380 * struct
381 */
382 struct regval_list {
383 unsigned char reg_num;
384 unsigned char value;
385 };
386
387 struct ov772x_color_format {
388 enum v4l2_mbus_pixelcode code;
389 enum v4l2_colorspace colorspace;
390 u8 dsp3;
391 u8 com3;
392 u8 com7;
393 };
394
395 struct ov772x_win_size {
396 char *name;
397 __u32 width;
398 __u32 height;
399 unsigned char com7_bit;
400 const struct regval_list *regs;
401 };
402
403 struct ov772x_priv {
404 struct v4l2_subdev subdev;
405 struct v4l2_ctrl_handler hdl;
406 struct ov772x_camera_info *info;
407 const struct ov772x_color_format *cfmt;
408 const struct ov772x_win_size *win;
409 int model;
410 unsigned short flag_vflip:1;
411 unsigned short flag_hflip:1;
412 /* band_filter = COM8[5] ? 256 - BDBASE : 0 */
413 unsigned short band_filter;
414 };
415
416 #define ENDMARKER { 0xff, 0xff }
417
418 /*
419 * register setting for window size
420 */
421 static const struct regval_list ov772x_qvga_regs[] = {
422 { HSTART, HST_QVGA },
423 { HSIZE, HSZ_QVGA },
424 { VSTART, VST_QVGA },
425 { VSIZE, VSZ_QVGA },
426 { HOUTSIZE, HOSZ_QVGA },
427 { VOUTSIZE, VOSZ_QVGA },
428 ENDMARKER,
429 };
430
431 static const struct regval_list ov772x_vga_regs[] = {
432 { HSTART, HST_VGA },
433 { HSIZE, HSZ_VGA },
434 { VSTART, VST_VGA },
435 { VSIZE, VSZ_VGA },
436 { HOUTSIZE, HOSZ_VGA },
437 { VOUTSIZE, VOSZ_VGA },
438 ENDMARKER,
439 };
440
441 /*
442 * supported color format list
443 */
444 static const struct ov772x_color_format ov772x_cfmts[] = {
445 {
446 .code = V4L2_MBUS_FMT_YUYV8_2X8,
447 .colorspace = V4L2_COLORSPACE_JPEG,
448 .dsp3 = 0x0,
449 .com3 = SWAP_YUV,
450 .com7 = OFMT_YUV,
451 },
452 {
453 .code = V4L2_MBUS_FMT_YVYU8_2X8,
454 .colorspace = V4L2_COLORSPACE_JPEG,
455 .dsp3 = UV_ON,
456 .com3 = SWAP_YUV,
457 .com7 = OFMT_YUV,
458 },
459 {
460 .code = V4L2_MBUS_FMT_UYVY8_2X8,
461 .colorspace = V4L2_COLORSPACE_JPEG,
462 .dsp3 = 0x0,
463 .com3 = 0x0,
464 .com7 = OFMT_YUV,
465 },
466 {
467 .code = V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE,
468 .colorspace = V4L2_COLORSPACE_SRGB,
469 .dsp3 = 0x0,
470 .com3 = SWAP_RGB,
471 .com7 = FMT_RGB555 | OFMT_RGB,
472 },
473 {
474 .code = V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE,
475 .colorspace = V4L2_COLORSPACE_SRGB,
476 .dsp3 = 0x0,
477 .com3 = 0x0,
478 .com7 = FMT_RGB555 | OFMT_RGB,
479 },
480 {
481 .code = V4L2_MBUS_FMT_RGB565_2X8_LE,
482 .colorspace = V4L2_COLORSPACE_SRGB,
483 .dsp3 = 0x0,
484 .com3 = SWAP_RGB,
485 .com7 = FMT_RGB565 | OFMT_RGB,
486 },
487 {
488 .code = V4L2_MBUS_FMT_RGB565_2X8_BE,
489 .colorspace = V4L2_COLORSPACE_SRGB,
490 .dsp3 = 0x0,
491 .com3 = 0x0,
492 .com7 = FMT_RGB565 | OFMT_RGB,
493 },
494 };
495
496
497 /*
498 * window size list
499 */
500 #define VGA_WIDTH 640
501 #define VGA_HEIGHT 480
502 #define QVGA_WIDTH 320
503 #define QVGA_HEIGHT 240
504 #define MAX_WIDTH VGA_WIDTH
505 #define MAX_HEIGHT VGA_HEIGHT
506
507 static const struct ov772x_win_size ov772x_win_vga = {
508 .name = "VGA",
509 .width = VGA_WIDTH,
510 .height = VGA_HEIGHT,
511 .com7_bit = SLCT_VGA,
512 .regs = ov772x_vga_regs,
513 };
514
515 static const struct ov772x_win_size ov772x_win_qvga = {
516 .name = "QVGA",
517 .width = QVGA_WIDTH,
518 .height = QVGA_HEIGHT,
519 .com7_bit = SLCT_QVGA,
520 .regs = ov772x_qvga_regs,
521 };
522
523 /*
524 * general function
525 */
526
527 static struct ov772x_priv *to_ov772x(const struct i2c_client *client)
528 {
529 return container_of(i2c_get_clientdata(client), struct ov772x_priv,
530 subdev);
531 }
532
533 static int ov772x_write_array(struct i2c_client *client,
534 const struct regval_list *vals)
535 {
536 while (vals->reg_num != 0xff) {
537 int ret = i2c_smbus_write_byte_data(client,
538 vals->reg_num,
539 vals->value);
540 if (ret < 0)
541 return ret;
542 vals++;
543 }
544 return 0;
545 }
546
547 static int ov772x_mask_set(struct i2c_client *client,
548 u8 command,
549 u8 mask,
550 u8 set)
551 {
552 s32 val = i2c_smbus_read_byte_data(client, command);
553 if (val < 0)
554 return val;
555
556 val &= ~mask;
557 val |= set & mask;
558
559 return i2c_smbus_write_byte_data(client, command, val);
560 }
561
562 static int ov772x_reset(struct i2c_client *client)
563 {
564 int ret = i2c_smbus_write_byte_data(client, COM7, SCCB_RESET);
565 msleep(1);
566 return ret;
567 }
568
569 /*
570 * soc_camera_ops function
571 */
572
573 static int ov772x_s_stream(struct v4l2_subdev *sd, int enable)
574 {
575 struct i2c_client *client = v4l2_get_subdevdata(sd);
576 struct ov772x_priv *priv = container_of(sd, struct ov772x_priv, subdev);
577
578 if (!enable) {
579 ov772x_mask_set(client, COM2, SOFT_SLEEP_MODE, SOFT_SLEEP_MODE);
580 return 0;
581 }
582
583 if (!priv->win || !priv->cfmt) {
584 dev_err(&client->dev, "norm or win select error\n");
585 return -EPERM;
586 }
587
588 ov772x_mask_set(client, COM2, SOFT_SLEEP_MODE, 0);
589
590 dev_dbg(&client->dev, "format %d, win %s\n",
591 priv->cfmt->code, priv->win->name);
592
593 return 0;
594 }
595
596 static int ov772x_s_ctrl(struct v4l2_ctrl *ctrl)
597 {
598 struct ov772x_priv *priv = container_of(ctrl->handler,
599 struct ov772x_priv, hdl);
600 struct v4l2_subdev *sd = &priv->subdev;
601 struct i2c_client *client = v4l2_get_subdevdata(sd);
602 int ret = 0;
603 u8 val;
604
605 switch (ctrl->id) {
606 case V4L2_CID_VFLIP:
607 val = ctrl->val ? VFLIP_IMG : 0x00;
608 priv->flag_vflip = ctrl->val;
609 if (priv->info->flags & OV772X_FLAG_VFLIP)
610 val ^= VFLIP_IMG;
611 return ov772x_mask_set(client, COM3, VFLIP_IMG, val);
612 case V4L2_CID_HFLIP:
613 val = ctrl->val ? HFLIP_IMG : 0x00;
614 priv->flag_hflip = ctrl->val;
615 if (priv->info->flags & OV772X_FLAG_HFLIP)
616 val ^= HFLIP_IMG;
617 return ov772x_mask_set(client, COM3, HFLIP_IMG, val);
618 case V4L2_CID_BAND_STOP_FILTER:
619 if (!ctrl->val) {
620 /* Switch the filter off, it is on now */
621 ret = ov772x_mask_set(client, BDBASE, 0xff, 0xff);
622 if (!ret)
623 ret = ov772x_mask_set(client, COM8,
624 BNDF_ON_OFF, 0);
625 } else {
626 /* Switch the filter on, set AEC low limit */
627 val = 256 - ctrl->val;
628 ret = ov772x_mask_set(client, COM8,
629 BNDF_ON_OFF, BNDF_ON_OFF);
630 if (!ret)
631 ret = ov772x_mask_set(client, BDBASE,
632 0xff, val);
633 }
634 if (!ret)
635 priv->band_filter = ctrl->val;
636 return ret;
637 }
638
639 return -EINVAL;
640 }
641
642 static int ov772x_g_chip_ident(struct v4l2_subdev *sd,
643 struct v4l2_dbg_chip_ident *id)
644 {
645 struct ov772x_priv *priv = container_of(sd, struct ov772x_priv, subdev);
646
647 id->ident = priv->model;
648 id->revision = 0;
649
650 return 0;
651 }
652
653 #ifdef CONFIG_VIDEO_ADV_DEBUG
654 static int ov772x_g_register(struct v4l2_subdev *sd,
655 struct v4l2_dbg_register *reg)
656 {
657 struct i2c_client *client = v4l2_get_subdevdata(sd);
658 int ret;
659
660 reg->size = 1;
661 if (reg->reg > 0xff)
662 return -EINVAL;
663
664 ret = i2c_smbus_read_byte_data(client, reg->reg);
665 if (ret < 0)
666 return ret;
667
668 reg->val = (__u64)ret;
669
670 return 0;
671 }
672
673 static int ov772x_s_register(struct v4l2_subdev *sd,
674 struct v4l2_dbg_register *reg)
675 {
676 struct i2c_client *client = v4l2_get_subdevdata(sd);
677
678 if (reg->reg > 0xff ||
679 reg->val > 0xff)
680 return -EINVAL;
681
682 return i2c_smbus_write_byte_data(client, reg->reg, reg->val);
683 }
684 #endif
685
686 static const struct ov772x_win_size *ov772x_select_win(u32 width, u32 height)
687 {
688 __u32 diff;
689 const struct ov772x_win_size *win;
690
691 /* default is QVGA */
692 diff = abs(width - ov772x_win_qvga.width) +
693 abs(height - ov772x_win_qvga.height);
694 win = &ov772x_win_qvga;
695
696 /* VGA */
697 if (diff >
698 abs(width - ov772x_win_vga.width) +
699 abs(height - ov772x_win_vga.height))
700 win = &ov772x_win_vga;
701
702 return win;
703 }
704
705 static int ov772x_set_params(struct i2c_client *client, u32 *width, u32 *height,
706 enum v4l2_mbus_pixelcode code)
707 {
708 struct ov772x_priv *priv = to_ov772x(client);
709 int ret = -EINVAL;
710 u8 val;
711 int i;
712
713 /*
714 * select format
715 */
716 priv->cfmt = NULL;
717 for (i = 0; i < ARRAY_SIZE(ov772x_cfmts); i++) {
718 if (code == ov772x_cfmts[i].code) {
719 priv->cfmt = ov772x_cfmts + i;
720 break;
721 }
722 }
723 if (!priv->cfmt)
724 goto ov772x_set_fmt_error;
725
726 /*
727 * select win
728 */
729 priv->win = ov772x_select_win(*width, *height);
730
731 /*
732 * reset hardware
733 */
734 ov772x_reset(client);
735
736 /*
737 * Edge Ctrl
738 */
739 if (priv->info->edgectrl.strength & OV772X_MANUAL_EDGE_CTRL) {
740
741 /*
742 * Manual Edge Control Mode
743 *
744 * Edge auto strength bit is set by default.
745 * Remove it when manual mode.
746 */
747
748 ret = ov772x_mask_set(client, DSPAUTO, EDGE_ACTRL, 0x00);
749 if (ret < 0)
750 goto ov772x_set_fmt_error;
751
752 ret = ov772x_mask_set(client,
753 EDGE_TRSHLD, OV772X_EDGE_THRESHOLD_MASK,
754 priv->info->edgectrl.threshold);
755 if (ret < 0)
756 goto ov772x_set_fmt_error;
757
758 ret = ov772x_mask_set(client,
759 EDGE_STRNGT, OV772X_EDGE_STRENGTH_MASK,
760 priv->info->edgectrl.strength);
761 if (ret < 0)
762 goto ov772x_set_fmt_error;
763
764 } else if (priv->info->edgectrl.upper > priv->info->edgectrl.lower) {
765 /*
766 * Auto Edge Control Mode
767 *
768 * set upper and lower limit
769 */
770 ret = ov772x_mask_set(client,
771 EDGE_UPPER, OV772X_EDGE_UPPER_MASK,
772 priv->info->edgectrl.upper);
773 if (ret < 0)
774 goto ov772x_set_fmt_error;
775
776 ret = ov772x_mask_set(client,
777 EDGE_LOWER, OV772X_EDGE_LOWER_MASK,
778 priv->info->edgectrl.lower);
779 if (ret < 0)
780 goto ov772x_set_fmt_error;
781 }
782
783 /*
784 * set size format
785 */
786 ret = ov772x_write_array(client, priv->win->regs);
787 if (ret < 0)
788 goto ov772x_set_fmt_error;
789
790 /*
791 * set DSP_CTRL3
792 */
793 val = priv->cfmt->dsp3;
794 if (val) {
795 ret = ov772x_mask_set(client,
796 DSP_CTRL3, UV_MASK, val);
797 if (ret < 0)
798 goto ov772x_set_fmt_error;
799 }
800
801 /*
802 * set COM3
803 */
804 val = priv->cfmt->com3;
805 if (priv->info->flags & OV772X_FLAG_VFLIP)
806 val |= VFLIP_IMG;
807 if (priv->info->flags & OV772X_FLAG_HFLIP)
808 val |= HFLIP_IMG;
809 if (priv->flag_vflip)
810 val ^= VFLIP_IMG;
811 if (priv->flag_hflip)
812 val ^= HFLIP_IMG;
813
814 ret = ov772x_mask_set(client,
815 COM3, SWAP_MASK | IMG_MASK, val);
816 if (ret < 0)
817 goto ov772x_set_fmt_error;
818
819 /*
820 * set COM7
821 */
822 val = priv->win->com7_bit | priv->cfmt->com7;
823 ret = ov772x_mask_set(client,
824 COM7, SLCT_MASK | FMT_MASK | OFMT_MASK,
825 val);
826 if (ret < 0)
827 goto ov772x_set_fmt_error;
828
829 /*
830 * set COM8
831 */
832 if (priv->band_filter) {
833 ret = ov772x_mask_set(client, COM8, BNDF_ON_OFF, 1);
834 if (!ret)
835 ret = ov772x_mask_set(client, BDBASE,
836 0xff, 256 - priv->band_filter);
837 if (ret < 0)
838 goto ov772x_set_fmt_error;
839 }
840
841 *width = priv->win->width;
842 *height = priv->win->height;
843
844 return ret;
845
846 ov772x_set_fmt_error:
847
848 ov772x_reset(client);
849 priv->win = NULL;
850 priv->cfmt = NULL;
851
852 return ret;
853 }
854
855 static int ov772x_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
856 {
857 a->c.left = 0;
858 a->c.top = 0;
859 a->c.width = VGA_WIDTH;
860 a->c.height = VGA_HEIGHT;
861 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
862
863 return 0;
864 }
865
866 static int ov772x_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
867 {
868 a->bounds.left = 0;
869 a->bounds.top = 0;
870 a->bounds.width = VGA_WIDTH;
871 a->bounds.height = VGA_HEIGHT;
872 a->defrect = a->bounds;
873 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
874 a->pixelaspect.numerator = 1;
875 a->pixelaspect.denominator = 1;
876
877 return 0;
878 }
879
880 static int ov772x_g_fmt(struct v4l2_subdev *sd,
881 struct v4l2_mbus_framefmt *mf)
882 {
883 struct i2c_client *client = v4l2_get_subdevdata(sd);
884 struct ov772x_priv *priv = container_of(sd, struct ov772x_priv, subdev);
885
886 if (!priv->win || !priv->cfmt) {
887 u32 width = VGA_WIDTH, height = VGA_HEIGHT;
888 int ret = ov772x_set_params(client, &width, &height,
889 V4L2_MBUS_FMT_YUYV8_2X8);
890 if (ret < 0)
891 return ret;
892 }
893
894 mf->width = priv->win->width;
895 mf->height = priv->win->height;
896 mf->code = priv->cfmt->code;
897 mf->colorspace = priv->cfmt->colorspace;
898 mf->field = V4L2_FIELD_NONE;
899
900 return 0;
901 }
902
903 static int ov772x_s_fmt(struct v4l2_subdev *sd,
904 struct v4l2_mbus_framefmt *mf)
905 {
906 struct i2c_client *client = v4l2_get_subdevdata(sd);
907 struct ov772x_priv *priv = container_of(sd, struct ov772x_priv, subdev);
908 int ret = ov772x_set_params(client, &mf->width, &mf->height,
909 mf->code);
910
911 if (!ret)
912 mf->colorspace = priv->cfmt->colorspace;
913
914 return ret;
915 }
916
917 static int ov772x_try_fmt(struct v4l2_subdev *sd,
918 struct v4l2_mbus_framefmt *mf)
919 {
920 struct ov772x_priv *priv = container_of(sd, struct ov772x_priv, subdev);
921 const struct ov772x_win_size *win;
922 int i;
923
924 /*
925 * select suitable win
926 */
927 win = ov772x_select_win(mf->width, mf->height);
928
929 mf->width = win->width;
930 mf->height = win->height;
931 mf->field = V4L2_FIELD_NONE;
932
933 for (i = 0; i < ARRAY_SIZE(ov772x_cfmts); i++)
934 if (mf->code == ov772x_cfmts[i].code)
935 break;
936
937 if (i == ARRAY_SIZE(ov772x_cfmts)) {
938 /* Unsupported format requested. Propose either */
939 if (priv->cfmt) {
940 /* the current one or */
941 mf->colorspace = priv->cfmt->colorspace;
942 mf->code = priv->cfmt->code;
943 } else {
944 /* the default one */
945 mf->colorspace = ov772x_cfmts[0].colorspace;
946 mf->code = ov772x_cfmts[0].code;
947 }
948 } else {
949 /* Also return the colorspace */
950 mf->colorspace = ov772x_cfmts[i].colorspace;
951 }
952
953 return 0;
954 }
955
956 static int ov772x_video_probe(struct i2c_client *client)
957 {
958 struct ov772x_priv *priv = to_ov772x(client);
959 u8 pid, ver;
960 const char *devname;
961
962 /*
963 * check and show product ID and manufacturer ID
964 */
965 pid = i2c_smbus_read_byte_data(client, PID);
966 ver = i2c_smbus_read_byte_data(client, VER);
967
968 switch (VERSION(pid, ver)) {
969 case OV7720:
970 devname = "ov7720";
971 priv->model = V4L2_IDENT_OV7720;
972 break;
973 case OV7725:
974 devname = "ov7725";
975 priv->model = V4L2_IDENT_OV7725;
976 break;
977 default:
978 dev_err(&client->dev,
979 "Product ID error %x:%x\n", pid, ver);
980 return -ENODEV;
981 }
982
983 dev_info(&client->dev,
984 "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
985 devname,
986 pid,
987 ver,
988 i2c_smbus_read_byte_data(client, MIDH),
989 i2c_smbus_read_byte_data(client, MIDL));
990 return v4l2_ctrl_handler_setup(&priv->hdl);
991 }
992
993 static const struct v4l2_ctrl_ops ov772x_ctrl_ops = {
994 .s_ctrl = ov772x_s_ctrl,
995 };
996
997 static struct v4l2_subdev_core_ops ov772x_subdev_core_ops = {
998 .g_chip_ident = ov772x_g_chip_ident,
999 #ifdef CONFIG_VIDEO_ADV_DEBUG
1000 .g_register = ov772x_g_register,
1001 .s_register = ov772x_s_register,
1002 #endif
1003 };
1004
1005 static int ov772x_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
1006 enum v4l2_mbus_pixelcode *code)
1007 {
1008 if (index >= ARRAY_SIZE(ov772x_cfmts))
1009 return -EINVAL;
1010
1011 *code = ov772x_cfmts[index].code;
1012 return 0;
1013 }
1014
1015 static int ov772x_g_mbus_config(struct v4l2_subdev *sd,
1016 struct v4l2_mbus_config *cfg)
1017 {
1018 struct i2c_client *client = v4l2_get_subdevdata(sd);
1019 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
1020
1021 cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
1022 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
1023 V4L2_MBUS_DATA_ACTIVE_HIGH;
1024 cfg->type = V4L2_MBUS_PARALLEL;
1025 cfg->flags = soc_camera_apply_board_flags(icl, cfg);
1026
1027 return 0;
1028 }
1029
1030 static struct v4l2_subdev_video_ops ov772x_subdev_video_ops = {
1031 .s_stream = ov772x_s_stream,
1032 .g_mbus_fmt = ov772x_g_fmt,
1033 .s_mbus_fmt = ov772x_s_fmt,
1034 .try_mbus_fmt = ov772x_try_fmt,
1035 .cropcap = ov772x_cropcap,
1036 .g_crop = ov772x_g_crop,
1037 .enum_mbus_fmt = ov772x_enum_fmt,
1038 .g_mbus_config = ov772x_g_mbus_config,
1039 };
1040
1041 static struct v4l2_subdev_ops ov772x_subdev_ops = {
1042 .core = &ov772x_subdev_core_ops,
1043 .video = &ov772x_subdev_video_ops,
1044 };
1045
1046 /*
1047 * i2c_driver function
1048 */
1049
1050 static int ov772x_probe(struct i2c_client *client,
1051 const struct i2c_device_id *did)
1052 {
1053 struct ov772x_priv *priv;
1054 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
1055 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
1056 int ret;
1057
1058 if (!icl || !icl->priv) {
1059 dev_err(&client->dev, "OV772X: missing platform data!\n");
1060 return -EINVAL;
1061 }
1062
1063 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
1064 dev_err(&adapter->dev,
1065 "I2C-Adapter doesn't support "
1066 "I2C_FUNC_SMBUS_BYTE_DATA\n");
1067 return -EIO;
1068 }
1069
1070 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1071 if (!priv)
1072 return -ENOMEM;
1073
1074 priv->info = icl->priv;
1075
1076 v4l2_i2c_subdev_init(&priv->subdev, client, &ov772x_subdev_ops);
1077 v4l2_ctrl_handler_init(&priv->hdl, 3);
1078 v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops,
1079 V4L2_CID_VFLIP, 0, 1, 1, 0);
1080 v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops,
1081 V4L2_CID_HFLIP, 0, 1, 1, 0);
1082 v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops,
1083 V4L2_CID_BAND_STOP_FILTER, 0, 256, 1, 0);
1084 priv->subdev.ctrl_handler = &priv->hdl;
1085 if (priv->hdl.error) {
1086 int err = priv->hdl.error;
1087
1088 kfree(priv);
1089 return err;
1090 }
1091
1092 ret = ov772x_video_probe(client);
1093 if (ret) {
1094 v4l2_ctrl_handler_free(&priv->hdl);
1095 kfree(priv);
1096 }
1097
1098 return ret;
1099 }
1100
1101 static int ov772x_remove(struct i2c_client *client)
1102 {
1103 struct ov772x_priv *priv = to_ov772x(client);
1104
1105 v4l2_device_unregister_subdev(&priv->subdev);
1106 v4l2_ctrl_handler_free(&priv->hdl);
1107 kfree(priv);
1108 return 0;
1109 }
1110
1111 static const struct i2c_device_id ov772x_id[] = {
1112 { "ov772x", 0 },
1113 { }
1114 };
1115 MODULE_DEVICE_TABLE(i2c, ov772x_id);
1116
1117 static struct i2c_driver ov772x_i2c_driver = {
1118 .driver = {
1119 .name = "ov772x",
1120 },
1121 .probe = ov772x_probe,
1122 .remove = ov772x_remove,
1123 .id_table = ov772x_id,
1124 };
1125
1126 /*
1127 * module function
1128 */
1129
1130 static int __init ov772x_module_init(void)
1131 {
1132 return i2c_add_driver(&ov772x_i2c_driver);
1133 }
1134
1135 static void __exit ov772x_module_exit(void)
1136 {
1137 i2c_del_driver(&ov772x_i2c_driver);
1138 }
1139
1140 module_init(ov772x_module_init);
1141 module_exit(ov772x_module_exit);
1142
1143 MODULE_DESCRIPTION("SoC Camera driver for ov772x");
1144 MODULE_AUTHOR("Kuninori Morimoto");
1145 MODULE_LICENSE("GPL v2");