drivers/ssb/driver_pcicore.c

   1 /*
   2  * Sonics Silicon Backplane
   3  * Broadcom PCI-core driver
   4  *
   5  * Copyright 2005, Broadcom Corporation
   6  * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
   7  *
   8  * Licensed under the GNU/GPL. See COPYING for details.
   9  */
  10
  11 #include <linux/ssb/ssb.h>
  12 #include <linux/pci.h>
  13 #include <linux/export.h>
  14 #include <linux/delay.h>
  15 #include <linux/ssb/ssb_embedded.h>
  16
  17 #include "ssb_private.h"
  18
  19 static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
  20 static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
  21 static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
  22 static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
  23                                 u8 address, u16 data);
  24
  25 static inline
  26 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
  27 {
  28         return ssb_read32(pc->dev, offset);
  29 }
  30
  31 static inline
  32 void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)
  33 {
  34         ssb_write32(pc->dev, offset, value);
  35 }
  36
  37 static inline
  38 u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset)
  39 {
  40         return ssb_read16(pc->dev, offset);
  41 }
  42
  43 static inline
  44 void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value)
  45 {
  46         ssb_write16(pc->dev, offset, value);
  47 }
  48
  49 /**************************************************
  50  * Code for hostmode operation.
  51  **************************************************/
  52
  53 #ifdef CONFIG_SSB_PCICORE_HOSTMODE
  54
  55 #include <asm/paccess.h>
  56 /* Probe a 32bit value on the bus and catch bus exceptions.
  57  * Returns nonzero on a bus exception.
  58  * This is MIPS specific */
  59 #define mips_busprobe32(val, addr)      get_dbe((val), ((u32 *)(addr)))
  60
  61 /* Assume one-hot slot wiring */
  62 #define SSB_PCI_SLOT_MAX        16
  63
  64 /* Global lock is OK, as we won't have more than one extpci anyway. */
  65 static DEFINE_SPINLOCK(cfgspace_lock);
  66 /* Core to access the external PCI config space. Can only have one. */
  67 static struct ssb_pcicore *extpci_core;
  68
  69
  70 static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
  71                              unsigned int bus, unsigned int dev,
  72                              unsigned int func, unsigned int off)
  73 {
  74         u32 addr = 0;
  75         u32 tmp;
  76
  77         /* We do only have one cardbus device behind the bridge. */
  78         if (pc->cardbusmode && (dev > 1))
  79                 goto out;
  80
  81         if (bus == 0) {
  82                 /* Type 0 transaction */
  83                 if (unlikely(dev >= SSB_PCI_SLOT_MAX))
  84                         goto out;
  85                 /* Slide the window */
  86                 tmp = SSB_PCICORE_SBTOPCI_CFG0;
  87                 tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK);
  88                 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp);
  89                 /* Calculate the address */
  90                 addr = SSB_PCI_CFG;
  91                 addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK);
  92                 addr |= (func << 8);
  93                 addr |= (off & ~3);
  94         } else {
  95                 /* Type 1 transaction */
  96                 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
  97                                 SSB_PCICORE_SBTOPCI_CFG1);
  98                 /* Calculate the address */
  99                 addr = SSB_PCI_CFG;
 100                 addr |= (bus << 16);
 101                 addr |= (dev << 11);
 102                 addr |= (func << 8);
 103                 addr |= (off & ~3);
 104         }
 105 out:
 106         return addr;
 107 }
 108
 109 static int ssb_extpci_read_config(struct ssb_pcicore *pc,
 110                                   unsigned int bus, unsigned int dev,
 111                                   unsigned int func, unsigned int off,
 112                                   void *buf, int len)
 113 {
 114         int err = -EINVAL;
 115         u32 addr, val;
 116         void __iomem *mmio;
 117
 118         SSB_WARN_ON(!pc->hostmode);
 119         if (unlikely(len != 1 && len != 2 && len != 4))
 120                 goto out;
 121         addr = get_cfgspace_addr(pc, bus, dev, func, off);
 122         if (unlikely(!addr))
 123                 goto out;
 124         err = -ENOMEM;
 125         mmio = ioremap_nocache(addr, len);
 126         if (!mmio)
 127                 goto out;
 128
 129         if (mips_busprobe32(val, mmio)) {
 130                 val = 0xffffffff;
 131                 goto unmap;
 132         }
 133
 134         val = readl(mmio);
 135         val >>= (8 * (off & 3));
 136
 137         switch (len) {
 138         case 1:
 139                 *((u8 *)buf) = (u8)val;
 140                 break;
 141         case 2:
 142                 *((u16 *)buf) = (u16)val;
 143                 break;
 144         case 4:
 145                 *((u32 *)buf) = (u32)val;
 146                 break;
 147         }
 148         err = 0;
 149 unmap:
 150         iounmap(mmio);
 151 out:
 152         return err;
 153 }
 154
 155 static int ssb_extpci_write_config(struct ssb_pcicore *pc,
 156                                    unsigned int bus, unsigned int dev,
 157                                    unsigned int func, unsigned int off,
 158                                    const void *buf, int len)
 159 {
 160         int err = -EINVAL;
 161         u32 addr, val = 0;
 162         void __iomem *mmio;
 163
 164         SSB_WARN_ON(!pc->hostmode);
 165         if (unlikely(len != 1 && len != 2 && len != 4))
 166                 goto out;
 167         addr = get_cfgspace_addr(pc, bus, dev, func, off);
 168         if (unlikely(!addr))
 169                 goto out;
 170         err = -ENOMEM;
 171         mmio = ioremap_nocache(addr, len);
 172         if (!mmio)
 173                 goto out;
 174
 175         if (mips_busprobe32(val, mmio)) {
 176                 val = 0xffffffff;
 177                 goto unmap;
 178         }
 179
 180         switch (len) {
 181         case 1:
 182                 val = readl(mmio);
 183                 val &= ~(0xFF << (8 * (off & 3)));
 184                 val |= *((const u8 *)buf) << (8 * (off & 3));
 185                 break;
 186         case 2:
 187                 val = readl(mmio);
 188                 val &= ~(0xFFFF << (8 * (off & 3)));
 189                 val |= *((const u16 *)buf) << (8 * (off & 3));
 190                 break;
 191         case 4:
 192                 val = *((const u32 *)buf);
 193                 break;
 194         }
 195         writel(val, mmio);
 196
 197         err = 0;
 198 unmap:
 199         iounmap(mmio);
 200 out:
 201         return err;
 202 }
 203
 204 static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn,
 205                                    int reg, int size, u32 *val)
 206 {
 207         unsigned long flags;
 208         int err;
 209
 210         spin_lock_irqsave(&cfgspace_lock, flags);
 211         err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn),
 212                                      PCI_FUNC(devfn), reg, val, size);
 213         spin_unlock_irqrestore(&cfgspace_lock, flags);
 214
 215         return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
 216 }
 217
 218 static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn,
 219                                     int reg, int size, u32 val)
 220 {
 221         unsigned long flags;
 222         int err;
 223
 224         spin_lock_irqsave(&cfgspace_lock, flags);
 225         err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn),
 226                                       PCI_FUNC(devfn), reg, &val, size);
 227         spin_unlock_irqrestore(&cfgspace_lock, flags);
 228
 229         return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
 230 }
 231
 232 static struct pci_ops ssb_pcicore_pciops = {
 233         .read   = ssb_pcicore_read_config,
 234         .write  = ssb_pcicore_write_config,
 235 };
 236
 237 static struct resource ssb_pcicore_mem_resource = {
 238         .name   = "SSB PCIcore external memory",
 239         .start  = SSB_PCI_DMA,
 240         .end    = SSB_PCI_DMA + SSB_PCI_DMA_SZ - 1,
 241         .flags  = IORESOURCE_MEM | IORESOURCE_PCI_FIXED,
 242 };
 243
 244 static struct resource ssb_pcicore_io_resource = {
 245         .name   = "SSB PCIcore external I/O",
 246         .start  = 0x100,
 247         .end    = 0x7FF,
 248         .flags  = IORESOURCE_IO | IORESOURCE_PCI_FIXED,
 249 };
 250
 251 static struct pci_controller ssb_pcicore_controller = {
 252         .pci_ops        = &ssb_pcicore_pciops,
 253         .io_resource    = &ssb_pcicore_io_resource,
 254         .mem_resource   = &ssb_pcicore_mem_resource,
 255 };
 256
 257 /* This function is called when doing a pci_enable_device().
 258  * We must first check if the device is a device on the PCI-core bridge. */
 259 int ssb_pcicore_plat_dev_init(struct pci_dev *d)
 260 {
 261         if (d->bus->ops != &ssb_pcicore_pciops) {
 262                 /* This is not a device on the PCI-core bridge. */
 263                 return -ENODEV;
 264         }
 265
 266         ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
 267                    pci_name(d));
 268
 269         /* Fix up interrupt lines */
 270         d->irq = ssb_mips_irq(extpci_core->dev) + 2;
 271         pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
 272
 273         return 0;
 274 }
 275
 276 /* Early PCI fixup for a device on the PCI-core bridge. */
 277 static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev)
 278 {
 279         u8 lat;
 280
 281         if (dev->bus->ops != &ssb_pcicore_pciops) {
 282                 /* This is not a device on the PCI-core bridge. */
 283                 return;
 284         }
 285         if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
 286                 return;
 287
 288         ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
 289
 290         /* Enable PCI bridge bus mastering and memory space */
 291         pci_set_master(dev);
 292         if (pcibios_enable_device(dev, ~0) < 0) {
 293                 ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
 294                 return;
 295         }
 296
 297         /* Enable PCI bridge BAR1 prefetch and burst */
 298         pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
 299
 300         /* Make sure our latency is high enough to handle the devices behind us */
 301         lat = 168;
 302         ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
 303                    pci_name(dev), lat);
 304         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 305 }
 306 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
 307
 308 /* PCI device IRQ mapping. */
 309 int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 310 {
 311         if (dev->bus->ops != &ssb_pcicore_pciops) {
 312                 /* This is not a device on the PCI-core bridge. */
 313                 return -ENODEV;
 314         }
 315         return ssb_mips_irq(extpci_core->dev) + 2;
 316 }
 317
 318 static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
 319 {
 320         u32 val;
 321
 322         if (WARN_ON(extpci_core))
 323                 return;
 324         extpci_core = pc;
 325
 326         ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
 327         /* Reset devices on the external PCI bus */
 328         val = SSB_PCICORE_CTL_RST_OE;
 329         val |= SSB_PCICORE_CTL_CLK_OE;
 330         pcicore_write32(pc, SSB_PCICORE_CTL, val);
 331         val |= SSB_PCICORE_CTL_CLK; /* Clock on */
 332         pcicore_write32(pc, SSB_PCICORE_CTL, val);
 333         udelay(150); /* Assertion time demanded by the PCI standard */
 334         val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
 335         pcicore_write32(pc, SSB_PCICORE_CTL, val);
 336         val = SSB_PCICORE_ARBCTL_INTERN;
 337         pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
 338         udelay(1); /* Assertion time demanded by the PCI standard */
 339
 340         if (pc->dev->bus->has_cardbus_slot) {
 341                 ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n");
 342                 pc->cardbusmode = 1;
 343                 /* GPIO 1 resets the bridge */
 344                 ssb_gpio_out(pc->dev->bus, 1, 1);
 345                 ssb_gpio_outen(pc->dev->bus, 1, 1);
 346                 pcicore_write16(pc, SSB_PCICORE_SPROM(0),
 347                                 pcicore_read16(pc, SSB_PCICORE_SPROM(0))
 348                                 | 0x0400);
 349         }
 350
 351         /* 64MB I/O window */
 352         pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
 353                         SSB_PCICORE_SBTOPCI_IO);
 354         /* 64MB config space */
 355         pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
 356                         SSB_PCICORE_SBTOPCI_CFG0);
 357         /* 1GB memory window */
 358         pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
 359                         SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
 360
 361         /* Enable PCI bridge BAR0 prefetch and burst */
 362         val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 363         ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2);
 364         /* Clear error conditions */
 365         val = 0;
 366         ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2);
 367
 368         /* Enable PCI interrupts */
 369         pcicore_write32(pc, SSB_PCICORE_IMASK,
 370                         SSB_PCICORE_IMASK_INTA);
 371
 372         /* Ok, ready to run, register it to the system.
 373          * The following needs change, if we want to port hostmode
 374          * to non-MIPS platform. */
 375         ssb_pcicore_controller.io_map_base = (unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000);
 376         set_io_port_base(ssb_pcicore_controller.io_map_base);
 377         /* Give some time to the PCI controller to configure itself with the new
 378          * values. Not waiting at this point causes crashes of the machine. */
 379         mdelay(10);
 380         register_pci_controller(&ssb_pcicore_controller);
 381 }
 382
 383 static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc)
 384 {
 385         struct ssb_bus *bus = pc->dev->bus;
 386         u16 chipid_top;
 387         u32 tmp;
 388
 389         chipid_top = (bus->chip_id & 0xFF00);
 390         if (chipid_top != 0x4700 &&
 391             chipid_top != 0x5300)
 392                 return 0;
 393
 394         if (bus->sprom.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
 395                 return 0;
 396
 397         /* The 200-pin BCM4712 package does not bond out PCI. Even when
 398          * PCI is bonded out, some boards may leave the pins floating. */
 399         if (bus->chip_id == 0x4712) {
 400                 if (bus->chip_package == SSB_CHIPPACK_BCM4712S)
 401                         return 0;
 402                 if (bus->chip_package == SSB_CHIPPACK_BCM4712M)
 403                         return 0;
 404         }
 405         if (bus->chip_id == 0x5350)
 406                 return 0;
 407
 408         return !mips_busprobe32(tmp, (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE)));
 409 }
 410 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
 411
 412 /**************************************************
 413  * Workarounds.
 414  **************************************************/
 415
 416 static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
 417 {
 418         u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
 419         if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
 420                 tmp &= ~0xF000;
 421                 tmp |= (pc->dev->core_index << 12);
 422                 pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
 423         }
 424 }
 425
 426 static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
 427 {
 428         return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
 429 }
 430
 431 static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
 432 {
 433         const u8 serdes_pll_device = 0x1D;
 434         const u8 serdes_rx_device = 0x1F;
 435         u16 tmp;
 436
 437         ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
 438                             ssb_pcicore_polarity_workaround(pc));
 439         tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
 440         if (tmp & 0x4000)
 441                 ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
 442 }
 443
 444 static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
 445 {
 446         struct ssb_device *pdev = pc->dev;
 447         struct ssb_bus *bus = pdev->bus;
 448         u32 tmp;
 449
 450         tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
 451         tmp |= SSB_PCICORE_SBTOPCI_PREF;
 452         tmp |= SSB_PCICORE_SBTOPCI_BURST;
 453         pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
 454
 455         if (pdev->id.revision < 5) {
 456                 tmp = ssb_read32(pdev, SSB_IMCFGLO);
 457                 tmp &= ~SSB_IMCFGLO_SERTO;
 458                 tmp |= 2;
 459                 tmp &= ~SSB_IMCFGLO_REQTO;
 460                 tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
 461                 ssb_write32(pdev, SSB_IMCFGLO, tmp);
 462                 ssb_commit_settings(bus);
 463         } else if (pdev->id.revision >= 11) {
 464                 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
 465                 tmp |= SSB_PCICORE_SBTOPCI_MRM;
 466                 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
 467         }
 468 }
 469
 470 static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
 471 {
 472         u32 tmp;
 473         u8 rev = pc->dev->id.revision;
 474
 475         if (rev == 0 || rev == 1) {
 476                 /* TLP Workaround register. */
 477                 tmp = ssb_pcie_read(pc, 0x4);
 478                 tmp |= 0x8;
 479                 ssb_pcie_write(pc, 0x4, tmp);
 480         }
 481         if (rev == 1) {
 482                 /* DLLP Link Control register. */
 483                 tmp = ssb_pcie_read(pc, 0x100);
 484                 tmp |= 0x40;
 485                 ssb_pcie_write(pc, 0x100, tmp);
 486         }
 487
 488         if (rev == 0) {
 489                 const u8 serdes_rx_device = 0x1F;
 490
 491                 ssb_pcie_mdio_write(pc, serdes_rx_device,
 492                                         2 /* Timer */, 0x8128);
 493                 ssb_pcie_mdio_write(pc, serdes_rx_device,
 494                                         6 /* CDR */, 0x0100);
 495                 ssb_pcie_mdio_write(pc, serdes_rx_device,
 496                                         7 /* CDR BW */, 0x1466);
 497         } else if (rev == 3 || rev == 4 || rev == 5) {
 498                 /* TODO: DLLP Power Management Threshold */
 499                 ssb_pcicore_serdes_workaround(pc);
 500                 /* TODO: ASPM */
 501         } else if (rev == 7) {
 502                 /* TODO: No PLL down */
 503         }
 504
 505         if (rev >= 6) {
 506                 /* Miscellaneous Configuration Fixup */
 507                 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
 508                 if (!(tmp & 0x8000))
 509                         pcicore_write16(pc, SSB_PCICORE_SPROM(5),
 510                                         tmp | 0x8000);
 511         }
 512 }
 513
 514 /**************************************************
 515  * Generic and Clientmode operation code.
 516  **************************************************/
 517
 518 static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
 519 {
 520         struct ssb_device *pdev = pc->dev;
 521         struct ssb_bus *bus = pdev->bus;
 522
 523         if (bus->bustype == SSB_BUSTYPE_PCI)
 524                 ssb_pcicore_fix_sprom_core_index(pc);
 525
 526         /* Disable PCI interrupts. */
 527         ssb_write32(pdev, SSB_INTVEC, 0);
 528
 529         /* Additional PCIe always once-executed workarounds */
 530         if (pc->dev->id.coreid == SSB_DEV_PCIE) {
 531                 ssb_pcicore_serdes_workaround(pc);
 532                 /* TODO: ASPM */
 533                 /* TODO: Clock Request Update */
 534         }
 535 }
 536
 537 void __devinit ssb_pcicore_init(struct ssb_pcicore *pc)
 538 {
 539         struct ssb_device *dev = pc->dev;
 540
 541         if (!dev)
 542                 return;
 543         if (!ssb_device_is_enabled(dev))
 544                 ssb_device_enable(dev, 0);
 545
 546 #ifdef CONFIG_SSB_PCICORE_HOSTMODE
 547         pc->hostmode = pcicore_is_in_hostmode(pc);
 548         if (pc->hostmode)
 549                 ssb_pcicore_init_hostmode(pc);
 550 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
 551         if (!pc->hostmode)
 552                 ssb_pcicore_init_clientmode(pc);
 553 }
 554
 555 static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)
 556 {
 557         pcicore_write32(pc, 0x130, address);
 558         return pcicore_read32(pc, 0x134);
 559 }
 560
 561 static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data)
 562 {
 563         pcicore_write32(pc, 0x130, address);
 564         pcicore_write32(pc, 0x134, data);
 565 }
 566
 567 static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
 568 {
 569         const u16 mdio_control = 0x128;
 570         const u16 mdio_data = 0x12C;
 571         u32 v;
 572         int i;
 573
 574         v = (1 << 30); /* Start of Transaction */
 575         v |= (1 << 28); /* Write Transaction */
 576         v |= (1 << 17); /* Turnaround */
 577         v |= (0x1F << 18);
 578         v |= (phy << 4);
 579         pcicore_write32(pc, mdio_data, v);
 580
 581         udelay(10);
 582         for (i = 0; i < 200; i++) {
 583                 v = pcicore_read32(pc, mdio_control);
 584                 if (v & 0x100 /* Trans complete */)
 585                         break;
 586                 msleep(1);
 587         }
 588 }
 589
 590 static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
 591 {
 592         const u16 mdio_control = 0x128;
 593         const u16 mdio_data = 0x12C;
 594         int max_retries = 10;
 595         u16 ret = 0;
 596         u32 v;
 597         int i;
 598
 599         v = 0x80; /* Enable Preamble Sequence */
 600         v |= 0x2; /* MDIO Clock Divisor */
 601         pcicore_write32(pc, mdio_control, v);
 602
 603         if (pc->dev->id.revision >= 10) {
 604                 max_retries = 200;
 605                 ssb_pcie_mdio_set_phy(pc, device);
 606         }
 607
 608         v = (1 << 30); /* Start of Transaction */
 609         v |= (1 << 29); /* Read Transaction */
 610         v |= (1 << 17); /* Turnaround */
 611         if (pc->dev->id.revision < 10)
 612                 v |= (u32)device << 22;
 613         v |= (u32)address << 18;
 614         pcicore_write32(pc, mdio_data, v);
 615         /* Wait for the device to complete the transaction */
 616         udelay(10);
 617         for (i = 0; i < max_retries; i++) {
 618                 v = pcicore_read32(pc, mdio_control);
 619                 if (v & 0x100 /* Trans complete */) {
 620                         udelay(10);
 621                         ret = pcicore_read32(pc, mdio_data);
 622                         break;
 623                 }
 624                 msleep(1);
 625         }
 626         pcicore_write32(pc, mdio_control, 0);
 627         return ret;
 628 }
 629
 630 static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
 631                                 u8 address, u16 data)
 632 {
 633         const u16 mdio_control = 0x128;
 634         const u16 mdio_data = 0x12C;
 635         int max_retries = 10;
 636         u32 v;
 637         int i;
 638
 639         v = 0x80; /* Enable Preamble Sequence */
 640         v |= 0x2; /* MDIO Clock Divisor */
 641         pcicore_write32(pc, mdio_control, v);
 642
 643         if (pc->dev->id.revision >= 10) {
 644                 max_retries = 200;
 645                 ssb_pcie_mdio_set_phy(pc, device);
 646         }
 647
 648         v = (1 << 30); /* Start of Transaction */
 649         v |= (1 << 28); /* Write Transaction */
 650         v |= (1 << 17); /* Turnaround */
 651         if (pc->dev->id.revision < 10)
 652                 v |= (u32)device << 22;
 653         v |= (u32)address << 18;
 654         v |= data;
 655         pcicore_write32(pc, mdio_data, v);
 656         /* Wait for the device to complete the transaction */
 657         udelay(10);
 658         for (i = 0; i < max_retries; i++) {
 659                 v = pcicore_read32(pc, mdio_control);
 660                 if (v & 0x100 /* Trans complete */)
 661                         break;
 662                 msleep(1);
 663         }
 664         pcicore_write32(pc, mdio_control, 0);
 665 }
 666
 667 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
 668                                    struct ssb_device *dev)
 669 {
 670         struct ssb_device *pdev = pc->dev;
 671         struct ssb_bus *bus;
 672         int err = 0;
 673         u32 tmp;
 674
 675         if (dev->bus->bustype != SSB_BUSTYPE_PCI) {
 676                 /* This SSB device is not on a PCI host-bus. So the IRQs are
 677                  * not routed through the PCI core.
 678                  * So we must not enable routing through the PCI core. */
 679                 goto out;
 680         }
 681
 682         if (!pdev)
 683                 goto out;
 684         bus = pdev->bus;
 685
 686         might_sleep_if(pdev->id.coreid != SSB_DEV_PCI);
 687
 688         /* Enable interrupts for this device. */
 689         if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) {
 690                 u32 coremask;
 691
 692                 /* Calculate the "coremask" for the device. */
 693                 coremask = (1 << dev->core_index);
 694
 695                 SSB_WARN_ON(bus->bustype != SSB_BUSTYPE_PCI);
 696                 err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
 697                 if (err)
 698                         goto out;
 699                 tmp |= coremask << 8;
 700                 err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp);
 701                 if (err)
 702                         goto out;
 703         } else {
 704                 u32 intvec;
 705
 706                 intvec = ssb_read32(pdev, SSB_INTVEC);
 707                 tmp = ssb_read32(dev, SSB_TPSFLAG);
 708                 tmp &= SSB_TPSFLAG_BPFLAG;
 709                 intvec |= (1 << tmp);
 710                 ssb_write32(pdev, SSB_INTVEC, intvec);
 711         }
 712
 713         /* Setup PCIcore operation. */
 714         if (pc->setup_done)
 715                 goto out;
 716         if (pdev->id.coreid == SSB_DEV_PCI) {
 717                 ssb_pcicore_pci_setup_workarounds(pc);
 718         } else {
 719                 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
 720                 ssb_pcicore_pcie_setup_workarounds(pc);
 721         }
 722         pc->setup_done = 1;
 723 out:
 724         return err;
 725 }
 726 EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable);