1 /* Driver for Realtek RTS51xx USB card reader
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * wwang (wei_wang@realsil.com.cn)
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
22 * Edwin Rong (edwin_rong@realsil.com.cn)
23 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
26 #include <linux/blkdev.h>
27 #include <linux/kthread.h>
28 #include <linux/sched.h>
29 #include <linux/workqueue.h>
31 #include <scsi/scsi.h>
32 #include <scsi/scsi_eh.h>
33 #include <scsi/scsi_device.h>
37 #include "rts51x_chip.h"
38 #include "rts51x_card.h"
39 #include "rts51x_transport.h"
40 #include "rts51x_sys.h"
45 void do_remaining_work(struct rts51x_chip
*chip
)
47 struct sd_info
*sd_card
= &(chip
->sd_card
);
48 struct xd_info
*xd_card
= &(chip
->xd_card
);
49 struct ms_info
*ms_card
= &(chip
->ms_card
);
51 if (chip
->card_ready
& SD_CARD
) {
52 if (sd_card
->seq_mode
) {
53 RTS51X_SET_STAT(chip
, STAT_RUN
);
60 if (chip
->card_ready
& XD_CARD
) {
61 if (xd_card
->delay_write
.delay_write_flag
) {
62 RTS51X_SET_STAT(chip
, STAT_RUN
);
69 if (chip
->card_ready
& MS_CARD
) {
70 if (CHK_MSPRO(ms_card
)) {
71 if (ms_card
->seq_mode
) {
72 RTS51X_SET_STAT(chip
, STAT_RUN
);
78 if (ms_card
->delay_write
.delay_write_flag
) {
79 RTS51X_SET_STAT(chip
, STAT_RUN
);
87 if (sd_card
->counter
> POLLING_WAIT_CNT
)
88 sd_cleanup_work(chip
);
90 if (xd_card
->counter
> POLLING_WAIT_CNT
)
91 xd_cleanup_work(chip
);
93 if (ms_card
->counter
> POLLING_WAIT_CNT
)
94 ms_cleanup_work(chip
);
97 void do_reset_xd_card(struct rts51x_chip
*chip
)
101 if (chip
->card2lun
[XD_CARD
] >= MAX_ALLOWED_LUN_CNT
)
104 retval
= reset_xd_card(chip
);
105 if (retval
== STATUS_SUCCESS
) {
106 chip
->card_ready
|= XD_CARD
;
107 chip
->card_fail
&= ~XD_CARD
;
108 chip
->rw_card
[chip
->card2lun
[XD_CARD
]] = xd_rw
;
110 chip
->card_ready
&= ~XD_CARD
;
111 chip
->card_fail
|= XD_CARD
;
112 chip
->capacity
[chip
->card2lun
[XD_CARD
]] = 0;
113 chip
->rw_card
[chip
->card2lun
[XD_CARD
]] = NULL
;
115 rts51x_init_cmd(chip
);
116 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_OE
, XD_OUTPUT_EN
, 0);
117 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PWR_CTL
, POWER_MASK
,
119 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_CLK_EN
, XD_CLK_EN
, 0);
120 rts51x_send_cmd(chip
, MODE_C
, 100);
124 void do_reset_sd_card(struct rts51x_chip
*chip
)
128 if (chip
->card2lun
[SD_CARD
] >= MAX_ALLOWED_LUN_CNT
)
131 retval
= reset_sd_card(chip
);
132 if (retval
== STATUS_SUCCESS
) {
133 chip
->card_ready
|= SD_CARD
;
134 chip
->card_fail
&= ~SD_CARD
;
135 chip
->rw_card
[chip
->card2lun
[SD_CARD
]] = sd_rw
;
137 chip
->card_ready
&= ~SD_CARD
;
138 chip
->card_fail
|= SD_CARD
;
139 chip
->capacity
[chip
->card2lun
[SD_CARD
]] = 0;
140 chip
->rw_card
[chip
->card2lun
[SD_CARD
]] = NULL
;
142 rts51x_init_cmd(chip
);
143 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_OE
, SD_OUTPUT_EN
, 0);
144 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PWR_CTL
, POWER_MASK
,
146 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_CLK_EN
, SD_CLK_EN
, 0);
147 rts51x_send_cmd(chip
, MODE_C
, 100);
151 void do_reset_ms_card(struct rts51x_chip
*chip
)
155 if (chip
->card2lun
[MS_CARD
] >= MAX_ALLOWED_LUN_CNT
)
158 retval
= reset_ms_card(chip
);
159 if (retval
== STATUS_SUCCESS
) {
160 chip
->card_ready
|= MS_CARD
;
161 chip
->card_fail
&= ~MS_CARD
;
162 chip
->rw_card
[chip
->card2lun
[MS_CARD
]] = ms_rw
;
164 chip
->card_ready
&= ~MS_CARD
;
165 chip
->card_fail
|= MS_CARD
;
166 chip
->capacity
[chip
->card2lun
[MS_CARD
]] = 0;
167 chip
->rw_card
[chip
->card2lun
[MS_CARD
]] = NULL
;
169 rts51x_init_cmd(chip
);
170 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_OE
, MS_OUTPUT_EN
, 0);
171 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PWR_CTL
, POWER_MASK
,
173 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_CLK_EN
, MS_CLK_EN
, 0);
174 rts51x_send_cmd(chip
, MODE_C
, 100);
178 void card_cd_debounce(struct rts51x_chip
*chip
, u8
*need_reset
,
182 u8 release_map
= 0, reset_map
= 0;
185 retval
= rts51x_get_card_status(chip
, &(chip
->card_status
));
187 chip
->ocp_stat
= (chip
->card_status
>> 4) & 0x03;
190 if (retval
!= STATUS_SUCCESS
)
193 if (chip
->card_exist
) {
194 rts51x_clear_start_time(chip
);
195 retval
= rts51x_read_register(chip
, CARD_INT_PEND
, &value
);
196 if (retval
!= STATUS_SUCCESS
) {
197 rts51x_ep0_write_register(chip
, MC_FIFO_CTL
, FIFO_FLUSH
,
199 rts51x_ep0_write_register(chip
, SFSM_ED
, 0xf8, 0xf8);
203 if (chip
->card_exist
& XD_CARD
) {
204 if (!(chip
->card_status
& XD_CD
))
205 release_map
|= XD_CARD
;
206 } else if (chip
->card_exist
& SD_CARD
) {
207 /* if (!(chip->card_status & SD_CD)) { */
208 if (!(chip
->card_status
& SD_CD
) || (value
& SD_INT
))
209 release_map
|= SD_CARD
;
210 } else if (chip
->card_exist
& MS_CARD
) {
211 /* if (!(chip->card_status & MS_CD)) { */
212 if (!(chip
->card_status
& MS_CD
) || (value
& MS_INT
))
213 release_map
|= MS_CARD
;
216 if (chip
->card_status
& XD_CD
) {
217 rts51x_clear_start_time(chip
);
218 reset_map
|= XD_CARD
;
219 } else if (chip
->card_status
& SD_CD
) {
220 rts51x_clear_start_time(chip
);
221 reset_map
|= SD_CARD
;
222 } else if (chip
->card_status
& MS_CD
) {
223 rts51x_clear_start_time(chip
);
224 reset_map
|= MS_CARD
;
226 if (rts51x_check_start_time(chip
))
227 rts51x_set_start_time(chip
);
231 if (CHECK_PKG(chip
, QFN24
) && reset_map
) {
232 if (chip
->card_exist
& XD_CARD
) {
239 int xd_cnt
= 0, sd_cnt
= 0, ms_cnt
= 0;
242 for (i
= 0; i
< (chip
->option
.debounce_num
); i
++) {
244 rts51x_get_card_status(chip
, &(chip
->card_status
));
245 if (retval
!= STATUS_SUCCESS
) {
246 reset_map
= release_map
= 0;
249 if (chip
->card_status
& XD_CD
)
253 if (chip
->card_status
& SD_CD
)
257 if (chip
->card_status
& MS_CD
)
265 if (!(chip
->card_exist
& XD_CARD
)
266 && (xd_cnt
> (chip
->option
.debounce_num
- 1))) {
267 reset_map
|= XD_CARD
;
269 if (!(chip
->card_exist
& SD_CARD
)
270 && (sd_cnt
> (chip
->option
.debounce_num
- 1))) {
271 reset_map
|= SD_CARD
;
273 if (!(chip
->card_exist
& MS_CARD
)
274 && (ms_cnt
> (chip
->option
.debounce_num
- 1))) {
275 reset_map
|= MS_CARD
;
278 rts51x_write_register(chip
, CARD_INT_PEND
, XD_INT
| MS_INT
| SD_INT
,
279 XD_INT
| MS_INT
| SD_INT
);
283 *need_reset
= reset_map
;
285 *need_release
= release_map
;
288 void rts51x_init_cards(struct rts51x_chip
*chip
)
290 u8 need_reset
= 0, need_release
= 0;
292 card_cd_debounce(chip
, &need_reset
, &need_release
);
295 RTS51X_DEBUGP("need_release = 0x%x\n", need_release
);
297 rts51x_prepare_run(chip
);
298 RTS51X_SET_STAT(chip
, STAT_RUN
);
301 if (chip
->ocp_stat
& (MS_OCP_NOW
| MS_OCP_EVER
)) {
302 rts51x_write_register(chip
, OCPCTL
, MS_OCP_CLEAR
,
305 RTS51X_DEBUGP("Clear OCP status.\n");
309 if (need_release
& XD_CARD
) {
310 chip
->card_exist
&= ~XD_CARD
;
311 chip
->card_ejected
= 0;
312 if (chip
->card_ready
& XD_CARD
) {
313 release_xd_card(chip
);
314 chip
->rw_card
[chip
->card2lun
[XD_CARD
]] = NULL
;
315 clear_bit(chip
->card2lun
[XD_CARD
],
320 if (need_release
& SD_CARD
) {
321 chip
->card_exist
&= ~SD_CARD
;
322 chip
->card_ejected
= 0;
323 if (chip
->card_ready
& SD_CARD
) {
324 release_sd_card(chip
);
325 chip
->rw_card
[chip
->card2lun
[SD_CARD
]] = NULL
;
326 clear_bit(chip
->card2lun
[SD_CARD
],
331 if (need_release
& MS_CARD
) {
332 chip
->card_exist
&= ~MS_CARD
;
333 chip
->card_ejected
= 0;
334 if (chip
->card_ready
& MS_CARD
) {
335 release_ms_card(chip
);
336 chip
->rw_card
[chip
->card2lun
[MS_CARD
]] = NULL
;
337 clear_bit(chip
->card2lun
[MS_CARD
],
343 if (need_reset
&& !chip
->card_ready
) {
344 RTS51X_DEBUGP("need_reset = 0x%x\n", need_reset
);
346 rts51x_prepare_run(chip
);
347 RTS51X_SET_STAT(chip
, STAT_RUN
);
349 if (need_reset
& XD_CARD
) {
350 chip
->card_exist
|= XD_CARD
;
351 do_reset_xd_card(chip
);
352 } else if (need_reset
& SD_CARD
) {
353 chip
->card_exist
|= SD_CARD
;
354 do_reset_sd_card(chip
);
355 } else if (need_reset
& MS_CARD
) {
356 chip
->card_exist
|= MS_CARD
;
357 do_reset_ms_card(chip
);
362 void rts51x_release_cards(struct rts51x_chip
*chip
)
364 if (chip
->card_ready
& SD_CARD
) {
365 sd_cleanup_work(chip
);
366 release_sd_card(chip
);
367 chip
->card_ready
&= ~SD_CARD
;
370 if (chip
->card_ready
& XD_CARD
) {
371 xd_cleanup_work(chip
);
372 release_xd_card(chip
);
373 chip
->card_ready
&= ~XD_CARD
;
376 if (chip
->card_ready
& MS_CARD
) {
377 ms_cleanup_work(chip
);
378 release_ms_card(chip
);
379 chip
->card_ready
&= ~MS_CARD
;
383 static inline u8
double_depth(u8 depth
)
385 return ((depth
> 1) ? (depth
- 1) : depth
);
388 int switch_ssc_clock(struct rts51x_chip
*chip
, int clk
)
390 struct sd_info
*sd_card
= &(chip
->sd_card
);
391 struct ms_info
*ms_card
= &(chip
->ms_card
);
393 u8 N
= (u8
) (clk
- 2), min_N
, max_N
;
394 u8 mcu_cnt
, div
, max_div
, ssc_depth
;
395 int sd_vpclk_phase_reset
= 0;
397 if (chip
->cur_clk
== clk
)
398 return STATUS_SUCCESS
;
404 RTS51X_DEBUGP("Switch SSC clock to %dMHz\n", clk
);
406 if ((clk
<= 2) || (N
> max_N
))
407 TRACE_RET(chip
, STATUS_FAIL
);
409 mcu_cnt
= (u8
) (60 / clk
+ 3);
412 /* To make sure that the SSC clock div_n is
413 * equal or greater than min_N */
415 while ((N
< min_N
) && (div
< max_div
)) {
419 RTS51X_DEBUGP("N = %d, div = %d\n", N
, div
);
421 if (chip
->option
.ssc_en
) {
422 if (chip
->cur_card
== SD_CARD
) {
423 if (CHK_SD_SDR104(sd_card
)) {
424 ssc_depth
= chip
->option
.ssc_depth_sd_sdr104
;
425 } else if (CHK_SD_SDR50(sd_card
)) {
426 ssc_depth
= chip
->option
.ssc_depth_sd_sdr50
;
427 } else if (CHK_SD_DDR50(sd_card
)) {
429 double_depth(chip
->option
.
431 } else if (CHK_SD_HS(sd_card
)) {
433 double_depth(chip
->option
.ssc_depth_sd_hs
);
434 } else if (CHK_MMC_52M(sd_card
)
435 || CHK_MMC_DDR52(sd_card
)) {
437 double_depth(chip
->option
.
441 double_depth(chip
->option
.
442 ssc_depth_low_speed
);
444 } else if (chip
->cur_card
== MS_CARD
) {
445 if (CHK_MSPRO(ms_card
)) {
446 if (CHK_HG8BIT(ms_card
)) {
448 double_depth(chip
->option
.
452 double_depth(chip
->option
.
456 if (CHK_MS4BIT(ms_card
)) {
458 double_depth(chip
->option
.
462 double_depth(chip
->option
.
463 ssc_depth_low_speed
);
468 double_depth(chip
->option
.ssc_depth_low_speed
);
472 if (div
== CLK_DIV_2
) {
473 /* If clock divided by 2, ssc depth must
474 * be multiplied by 2 */
478 ssc_depth
= SSC_DEPTH_2M
;
479 } else if (div
== CLK_DIV_4
) {
480 /* If clock divided by 4, ssc depth must
481 * be multiplied by 4 */
485 ssc_depth
= SSC_DEPTH_2M
;
493 RTS51X_DEBUGP("ssc_depth = %d\n", ssc_depth
);
495 rts51x_init_cmd(chip
);
496 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CLK_DIV
, CLK_CHANGE
, CLK_CHANGE
);
497 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CLK_DIV
, 0x3F,
498 (div
<< 4) | mcu_cnt
);
499 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SSC_CTL1
, SSC_RSTB
, 0);
500 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SSC_CTL2
, SSC_DEPTH_MASK
,
502 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SSC_DIV_N_0
, 0xFF, N
);
503 if (sd_vpclk_phase_reset
) {
504 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_VPCLK0_CTL
,
506 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_VPCLK0_CTL
,
507 PHASE_NOT_RESET
, PHASE_NOT_RESET
);
510 retval
= rts51x_send_cmd(chip
, MODE_C
, 2000);
511 if (retval
!= STATUS_SUCCESS
)
512 TRACE_RET(chip
, retval
);
513 if (chip
->option
.ssc_en
&& ssc_depth
)
514 rts51x_write_register(chip
, SSC_CTL1
, 0xff, 0xD0);
516 rts51x_write_register(chip
, SSC_CTL1
, 0xff, 0x50);
518 RTS51X_WRITE_REG(chip
, CLK_DIV
, CLK_CHANGE
, 0);
522 return STATUS_SUCCESS
;
525 int switch_normal_clock(struct rts51x_chip
*chip
, int clk
)
528 u8 sel
, div
, mcu_cnt
;
529 int sd_vpclk_phase_reset
= 0;
531 if (chip
->cur_clk
== clk
)
532 return STATUS_SUCCESS
;
534 if (chip
->cur_card
== SD_CARD
) {
535 struct sd_info
*sd_card
= &(chip
->sd_card
);
536 if (CHK_SD30_SPEED(sd_card
) || CHK_MMC_DDR52(sd_card
))
537 sd_vpclk_phase_reset
= 1;
542 RTS51X_DEBUGP("Switch clock to 20MHz\n");
549 RTS51X_DEBUGP("Switch clock to 30MHz\n");
556 RTS51X_DEBUGP("Switch clock to 40MHz\n");
563 RTS51X_DEBUGP("Switch clock to 50MHz\n");
570 RTS51X_DEBUGP("Switch clock to 60MHz\n");
577 RTS51X_DEBUGP("Switch clock to 80MHz\n");
584 RTS51X_DEBUGP("Switch clock to 100MHz\n");
591 RTS51X_DEBUGP("Switch clock to 120MHz\n");
598 RTS51X_DEBUGP("Switch clock to 150MHz\n");
605 RTS51X_DEBUGP("Try to switch to an illegal clock (%d)\n",
607 TRACE_RET(chip
, STATUS_FAIL
);
610 if (!sd_vpclk_phase_reset
) {
611 rts51x_init_cmd(chip
);
613 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CLK_DIV
, CLK_CHANGE
,
615 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CLK_DIV
, 0x3F,
616 (div
<< 4) | mcu_cnt
);
617 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SSC_CLK_FPGA_SEL
, 0xFF,
619 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CLK_DIV
, CLK_CHANGE
, 0);
621 retval
= rts51x_send_cmd(chip
, MODE_C
, 100);
622 if (retval
!= STATUS_SUCCESS
)
623 TRACE_RET(chip
, retval
);
625 rts51x_init_cmd(chip
);
627 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CLK_DIV
, CLK_CHANGE
,
629 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_VPCLK0_CTL
,
631 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_VPCLK1_CTL
,
633 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CLK_DIV
, 0x3F,
634 (div
<< 4) | mcu_cnt
);
635 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SSC_CLK_FPGA_SEL
, 0xFF,
638 retval
= rts51x_send_cmd(chip
, MODE_C
, 100);
639 if (retval
!= STATUS_SUCCESS
)
640 TRACE_RET(chip
, retval
);
644 rts51x_init_cmd(chip
);
646 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_VPCLK0_CTL
,
647 PHASE_NOT_RESET
, PHASE_NOT_RESET
);
648 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_VPCLK1_CTL
,
649 PHASE_NOT_RESET
, PHASE_NOT_RESET
);
651 retval
= rts51x_send_cmd(chip
, MODE_C
, 100);
652 if (retval
!= STATUS_SUCCESS
)
653 TRACE_RET(chip
, retval
);
657 RTS51X_WRITE_REG(chip
, CLK_DIV
, CLK_CHANGE
, 0);
662 return STATUS_SUCCESS
;
665 int card_rw(struct scsi_cmnd
*srb
, struct rts51x_chip
*chip
, u32 sec_addr
,
669 unsigned int lun
= SCSI_LUN(srb
);
672 if (chip
->rw_card
[lun
] == NULL
)
675 RTS51X_DEBUGP("%s card, sector addr: 0x%x, sector cnt: %d\n",
676 (srb
->sc_data_direction
==
677 DMA_TO_DEVICE
) ? "Write" : "Read", sec_addr
, sec_cnt
);
679 chip
->rw_need_retry
= 0;
680 for (i
= 0; i
< 3; i
++) {
681 retval
= chip
->rw_card
[lun
] (srb
, chip
, sec_addr
, sec_cnt
);
682 if (retval
!= STATUS_SUCCESS
) {
684 if (chip
->option
.reset_or_rw_fail_set_pad_drive
) {
685 rts51x_write_register(chip
, CARD_DRIVE_SEL
,
691 if (!chip
->rw_need_retry
)
694 RTS51X_DEBUGP("Retry RW, (i = %d\n)", i
);
700 u8
get_lun_card(struct rts51x_chip
*chip
, unsigned int lun
)
702 if ((chip
->card_ready
& chip
->lun2card
[lun
]) == XD_CARD
)
704 else if ((chip
->card_ready
& chip
->lun2card
[lun
]) == SD_CARD
)
706 else if ((chip
->card_ready
& chip
->lun2card
[lun
]) == MS_CARD
)
712 int card_share_mode(struct rts51x_chip
*chip
, int card
)
717 value
= CARD_SHARE_SD
;
718 else if (card
== MS_CARD
)
719 value
= CARD_SHARE_MS
;
720 else if (card
== XD_CARD
)
721 value
= CARD_SHARE_XD
;
723 TRACE_RET(chip
, STATUS_FAIL
);
725 RTS51X_WRITE_REG(chip
, CARD_SHARE_MODE
, CARD_SHARE_MASK
, value
);
727 return STATUS_SUCCESS
;
730 int rts51x_select_card(struct rts51x_chip
*chip
, int card
)
734 if (chip
->cur_card
!= card
) {
739 else if (card
== MS_CARD
)
741 else if (card
== XD_CARD
)
744 TRACE_RET(chip
, STATUS_FAIL
);
745 RTS51X_WRITE_REG(chip
, CARD_SELECT
, 0x07, mod
);
746 chip
->cur_card
= card
;
748 retval
= card_share_mode(chip
, card
);
749 if (retval
!= STATUS_SUCCESS
)
750 TRACE_RET(chip
, retval
);
753 return STATUS_SUCCESS
;
756 void eject_card(struct rts51x_chip
*chip
, unsigned int lun
)
758 RTS51X_DEBUGP("eject card\n");
759 RTS51X_SET_STAT(chip
, STAT_RUN
);
760 do_remaining_work(chip
);
762 if ((chip
->card_ready
& chip
->lun2card
[lun
]) == SD_CARD
) {
763 release_sd_card(chip
);
764 chip
->card_ejected
|= SD_CARD
;
765 chip
->card_ready
&= ~SD_CARD
;
766 chip
->capacity
[lun
] = 0;
767 } else if ((chip
->card_ready
& chip
->lun2card
[lun
]) == XD_CARD
) {
768 release_xd_card(chip
);
769 chip
->card_ejected
|= XD_CARD
;
770 chip
->card_ready
&= ~XD_CARD
;
771 chip
->capacity
[lun
] = 0;
772 } else if ((chip
->card_ready
& chip
->lun2card
[lun
]) == MS_CARD
) {
773 release_ms_card(chip
);
774 chip
->card_ejected
|= MS_CARD
;
775 chip
->card_ready
&= ~MS_CARD
;
776 chip
->capacity
[lun
] = 0;
778 rts51x_write_register(chip
, CARD_INT_PEND
, XD_INT
| MS_INT
| SD_INT
,
779 XD_INT
| MS_INT
| SD_INT
);
782 void trans_dma_enable(enum dma_data_direction dir
, struct rts51x_chip
*chip
,
783 u32 byte_cnt
, u8 pack_size
)
785 if (pack_size
> DMA_1024
)
788 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01,
791 rts51x_add_cmd(chip
, WRITE_REG_CMD
, MC_DMA_TC3
, 0xFF,
792 (u8
) (byte_cnt
>> 24));
793 rts51x_add_cmd(chip
, WRITE_REG_CMD
, MC_DMA_TC2
, 0xFF,
794 (u8
) (byte_cnt
>> 16));
795 rts51x_add_cmd(chip
, WRITE_REG_CMD
, MC_DMA_TC1
, 0xFF,
796 (u8
) (byte_cnt
>> 8));
797 rts51x_add_cmd(chip
, WRITE_REG_CMD
, MC_DMA_TC0
, 0xFF, (u8
) byte_cnt
);
799 if (dir
== DMA_FROM_DEVICE
) {
800 rts51x_add_cmd(chip
, WRITE_REG_CMD
, MC_DMA_CTL
,
801 0x03 | DMA_PACK_SIZE_MASK
,
802 DMA_DIR_FROM_CARD
| DMA_EN
| pack_size
);
804 rts51x_add_cmd(chip
, WRITE_REG_CMD
, MC_DMA_CTL
,
805 0x03 | DMA_PACK_SIZE_MASK
,
806 DMA_DIR_TO_CARD
| DMA_EN
| pack_size
);
810 int enable_card_clock(struct rts51x_chip
*chip
, u8 card
)
821 RTS51X_WRITE_REG(chip
, CARD_CLK_EN
, clk_en
, clk_en
);
823 return STATUS_SUCCESS
;
826 int disable_card_clock(struct rts51x_chip
*chip
, u8 card
)
837 RTS51X_WRITE_REG(chip
, CARD_CLK_EN
, clk_en
, 0);
839 return STATUS_SUCCESS
;
842 int card_power_on(struct rts51x_chip
*chip
, u8 card
)
847 val1
= PARTIAL_POWER_ON
;
850 #ifdef SD_XD_IO_FOLLOW_PWR
851 if ((card
== SD_CARD
) || (card
== XD_CARD
)) {
852 RTS51X_WRITE_REG(chip
, CARD_PWR_CTL
, mask
| LDO3318_PWR_MASK
,
854 /* RTS51X_WRITE_REG(chip, CARD_PWR_CTL,
855 LDO3318_PWR_MASK, LDO_SUSPEND); */
857 /* else if(card==XD_CARD)
859 RTS51X_WRITE_REG(chip, CARD_PWR_CTL,
860 mask|LDO3318_PWR_MASK, val1|LDO_SUSPEND);
861 //RTS51X_WRITE_REG(chip, CARD_PWR_CTL,
862 // LDO3318_PWR_MASK, LDO_SUSPEND);
866 RTS51X_WRITE_REG(chip
, CARD_PWR_CTL
, mask
, val1
);
867 #ifdef SD_XD_IO_FOLLOW_PWR
870 udelay(chip
->option
.pwr_delay
);
871 RTS51X_WRITE_REG(chip
, CARD_PWR_CTL
, mask
, val2
);
872 #ifdef SD_XD_IO_FOLLOW_PWR
873 if (card
== SD_CARD
) {
874 rts51x_write_register(chip
, CARD_PWR_CTL
, LDO3318_PWR_MASK
,
879 return STATUS_SUCCESS
;
882 int card_power_off(struct rts51x_chip
*chip
, u8 card
)
888 RTS51X_WRITE_REG(chip
, CARD_PWR_CTL
, mask
, val
);
890 return STATUS_SUCCESS
;
893 int monitor_card_cd(struct rts51x_chip
*chip
, u8 card
)
896 u8 card_cd
[32] = { 0 };
898 card_cd
[SD_CARD
] = SD_CD
;
899 card_cd
[XD_CARD
] = XD_CD
;
900 card_cd
[MS_CARD
] = MS_CD
;
902 retval
= rts51x_get_card_status(chip
, &(chip
->card_status
));
903 if (retval
!= STATUS_SUCCESS
)
906 if (chip
->card_status
& card_cd
[card
])
912 int toggle_gpio(struct rts51x_chip
*chip
, u8 gpio
)
916 u8 gpio_output
[4] = {
923 retval
= rts51x_ep0_read_register(chip
, CARD_GPIO
, &temp_reg
);
924 if (retval
!= STATUS_SUCCESS
)
925 TRACE_RET(chip
, STATUS_FAIL
);
926 temp_reg
^= gpio_oe
[gpio
];
927 temp_reg
&= 0xfe; /* bit 0 always set 0 */
929 rts51x_ep0_write_register(chip
, CARD_GPIO
, 0x03, temp_reg
);
930 if (retval
!= STATUS_SUCCESS
)
931 TRACE_RET(chip
, STATUS_FAIL
);
933 retval
= rts51x_ep0_read_register(chip
, CARD_GPIO
, &temp_reg
);
934 if (retval
!= STATUS_SUCCESS
)
935 TRACE_RET(chip
, STATUS_FAIL
);
936 temp_reg
^= gpio_output
[gpio
];
938 rts51x_ep0_write_register(chip
, CARD_GPIO
, 0xFF,
939 temp_reg
| gpio_oe
[gpio
]);
940 if (retval
!= STATUS_SUCCESS
)
941 TRACE_RET(chip
, STATUS_FAIL
);
944 return STATUS_SUCCESS
;
947 int turn_on_led(struct rts51x_chip
*chip
, u8 gpio
)
958 rts51x_ep0_write_register(chip
, CARD_GPIO
, gpio_mask
[gpio
],
960 if (retval
!= STATUS_SUCCESS
)
961 TRACE_RET(chip
, STATUS_FAIL
);
963 return STATUS_SUCCESS
;
966 int turn_off_led(struct rts51x_chip
*chip
, u8 gpio
)
969 u8 gpio_output
[4] = {
980 rts51x_ep0_write_register(chip
, CARD_GPIO
, gpio_mask
[gpio
],
981 gpio_oe
[gpio
] | gpio_output
[gpio
]);
982 if (retval
!= STATUS_SUCCESS
)
983 TRACE_RET(chip
, STATUS_FAIL
);
985 return STATUS_SUCCESS
;