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Avoid beyond bounds copy while caching ACL
[zen-stable.git] / drivers / usb / gadget / pch_udc.c
blob9c0d2d53dda9c8b03bc65c80eba1c8b9d3b5299b
1 /*
2 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 */
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/delay.h>
13 #include <linux/errno.h>
14 #include <linux/list.h>
15 #include <linux/interrupt.h>
16 #include <linux/usb/ch9.h>
17 #include <linux/usb/gadget.h>
18
19 /* Address offset of Registers */
20 #define UDC_EP_REG_SHIFT 0x20 /* Offset to next EP */
21
22 #define UDC_EPCTL_ADDR 0x00 /* Endpoint control */
23 #define UDC_EPSTS_ADDR 0x04 /* Endpoint status */
24 #define UDC_BUFIN_FRAMENUM_ADDR 0x08 /* buffer size in / frame number out */
25 #define UDC_BUFOUT_MAXPKT_ADDR 0x0C /* buffer size out / maxpkt in */
26 #define UDC_SUBPTR_ADDR 0x10 /* setup buffer pointer */
27 #define UDC_DESPTR_ADDR 0x14 /* Data descriptor pointer */
28 #define UDC_CONFIRM_ADDR 0x18 /* Write/Read confirmation */
29
30 #define UDC_DEVCFG_ADDR 0x400 /* Device configuration */
31 #define UDC_DEVCTL_ADDR 0x404 /* Device control */
32 #define UDC_DEVSTS_ADDR 0x408 /* Device status */
33 #define UDC_DEVIRQSTS_ADDR 0x40C /* Device irq status */
34 #define UDC_DEVIRQMSK_ADDR 0x410 /* Device irq mask */
35 #define UDC_EPIRQSTS_ADDR 0x414 /* Endpoint irq status */
36 #define UDC_EPIRQMSK_ADDR 0x418 /* Endpoint irq mask */
37 #define UDC_DEVLPM_ADDR 0x41C /* LPM control / status */
38 #define UDC_CSR_BUSY_ADDR 0x4f0 /* UDC_CSR_BUSY Status register */
39 #define UDC_SRST_ADDR 0x4fc /* SOFT RESET register */
40 #define UDC_CSR_ADDR 0x500 /* USB_DEVICE endpoint register */
41
42 /* Endpoint control register */
43 /* Bit position */
44 #define UDC_EPCTL_MRXFLUSH (1 << 12)
45 #define UDC_EPCTL_RRDY (1 << 9)
46 #define UDC_EPCTL_CNAK (1 << 8)
47 #define UDC_EPCTL_SNAK (1 << 7)
48 #define UDC_EPCTL_NAK (1 << 6)
49 #define UDC_EPCTL_P (1 << 3)
50 #define UDC_EPCTL_F (1 << 1)
51 #define UDC_EPCTL_S (1 << 0)
52 #define UDC_EPCTL_ET_SHIFT 4
53 /* Mask patern */
54 #define UDC_EPCTL_ET_MASK 0x00000030
55 /* Value for ET field */
56 #define UDC_EPCTL_ET_CONTROL 0
57 #define UDC_EPCTL_ET_ISO 1
58 #define UDC_EPCTL_ET_BULK 2
59 #define UDC_EPCTL_ET_INTERRUPT 3
60
61 /* Endpoint status register */
62 /* Bit position */
63 #define UDC_EPSTS_XFERDONE (1 << 27)
64 #define UDC_EPSTS_RSS (1 << 26)
65 #define UDC_EPSTS_RCS (1 << 25)
66 #define UDC_EPSTS_TXEMPTY (1 << 24)
67 #define UDC_EPSTS_TDC (1 << 10)
68 #define UDC_EPSTS_HE (1 << 9)
69 #define UDC_EPSTS_MRXFIFO_EMP (1 << 8)
70 #define UDC_EPSTS_BNA (1 << 7)
71 #define UDC_EPSTS_IN (1 << 6)
72 #define UDC_EPSTS_OUT_SHIFT 4
73 /* Mask patern */
74 #define UDC_EPSTS_OUT_MASK 0x00000030
75 #define UDC_EPSTS_ALL_CLR_MASK 0x1F0006F0
76 /* Value for OUT field */
77 #define UDC_EPSTS_OUT_SETUP 2
78 #define UDC_EPSTS_OUT_DATA 1
79
80 /* Device configuration register */
81 /* Bit position */
82 #define UDC_DEVCFG_CSR_PRG (1 << 17)
83 #define UDC_DEVCFG_SP (1 << 3)
84 /* SPD Valee */
85 #define UDC_DEVCFG_SPD_HS 0x0
86 #define UDC_DEVCFG_SPD_FS 0x1
87 #define UDC_DEVCFG_SPD_LS 0x2
88
89 /* Device control register */
90 /* Bit position */
91 #define UDC_DEVCTL_THLEN_SHIFT 24
92 #define UDC_DEVCTL_BRLEN_SHIFT 16
93 #define UDC_DEVCTL_CSR_DONE (1 << 13)
94 #define UDC_DEVCTL_SD (1 << 10)
95 #define UDC_DEVCTL_MODE (1 << 9)
96 #define UDC_DEVCTL_BREN (1 << 8)
97 #define UDC_DEVCTL_THE (1 << 7)
98 #define UDC_DEVCTL_DU (1 << 4)
99 #define UDC_DEVCTL_TDE (1 << 3)
100 #define UDC_DEVCTL_RDE (1 << 2)
101 #define UDC_DEVCTL_RES (1 << 0)
102
103 /* Device status register */
104 /* Bit position */
105 #define UDC_DEVSTS_TS_SHIFT 18
106 #define UDC_DEVSTS_ENUM_SPEED_SHIFT 13
107 #define UDC_DEVSTS_ALT_SHIFT 8
108 #define UDC_DEVSTS_INTF_SHIFT 4
109 #define UDC_DEVSTS_CFG_SHIFT 0
110 /* Mask patern */
111 #define UDC_DEVSTS_TS_MASK 0xfffc0000
112 #define UDC_DEVSTS_ENUM_SPEED_MASK 0x00006000
113 #define UDC_DEVSTS_ALT_MASK 0x00000f00
114 #define UDC_DEVSTS_INTF_MASK 0x000000f0
115 #define UDC_DEVSTS_CFG_MASK 0x0000000f
116 /* value for maximum speed for SPEED field */
117 #define UDC_DEVSTS_ENUM_SPEED_FULL 1
118 #define UDC_DEVSTS_ENUM_SPEED_HIGH 0
119 #define UDC_DEVSTS_ENUM_SPEED_LOW 2
120 #define UDC_DEVSTS_ENUM_SPEED_FULLX 3
121
122 /* Device irq register */
123 /* Bit position */
124 #define UDC_DEVINT_RWKP (1 << 7)
125 #define UDC_DEVINT_ENUM (1 << 6)
126 #define UDC_DEVINT_SOF (1 << 5)
127 #define UDC_DEVINT_US (1 << 4)
128 #define UDC_DEVINT_UR (1 << 3)
129 #define UDC_DEVINT_ES (1 << 2)
130 #define UDC_DEVINT_SI (1 << 1)
131 #define UDC_DEVINT_SC (1 << 0)
132 /* Mask patern */
133 #define UDC_DEVINT_MSK 0x7f
134
135 /* Endpoint irq register */
136 /* Bit position */
137 #define UDC_EPINT_IN_SHIFT 0
138 #define UDC_EPINT_OUT_SHIFT 16
139 #define UDC_EPINT_IN_EP0 (1 << 0)
140 #define UDC_EPINT_OUT_EP0 (1 << 16)
141 /* Mask patern */
142 #define UDC_EPINT_MSK_DISABLE_ALL 0xffffffff
143
144 /* UDC_CSR_BUSY Status register */
145 /* Bit position */
146 #define UDC_CSR_BUSY (1 << 0)
147
148 /* SOFT RESET register */
149 /* Bit position */
150 #define UDC_PSRST (1 << 1)
151 #define UDC_SRST (1 << 0)
152
153 /* USB_DEVICE endpoint register */
154 /* Bit position */
155 #define UDC_CSR_NE_NUM_SHIFT 0
156 #define UDC_CSR_NE_DIR_SHIFT 4
157 #define UDC_CSR_NE_TYPE_SHIFT 5
158 #define UDC_CSR_NE_CFG_SHIFT 7
159 #define UDC_CSR_NE_INTF_SHIFT 11
160 #define UDC_CSR_NE_ALT_SHIFT 15
161 #define UDC_CSR_NE_MAX_PKT_SHIFT 19
162 /* Mask patern */
163 #define UDC_CSR_NE_NUM_MASK 0x0000000f
164 #define UDC_CSR_NE_DIR_MASK 0x00000010
165 #define UDC_CSR_NE_TYPE_MASK 0x00000060
166 #define UDC_CSR_NE_CFG_MASK 0x00000780
167 #define UDC_CSR_NE_INTF_MASK 0x00007800
168 #define UDC_CSR_NE_ALT_MASK 0x00078000
169 #define UDC_CSR_NE_MAX_PKT_MASK 0x3ff80000
170
171 #define PCH_UDC_CSR(ep) (UDC_CSR_ADDR + ep*4)
172 #define PCH_UDC_EPINT(in, num)\
173 (1 << (num + (in ? UDC_EPINT_IN_SHIFT : UDC_EPINT_OUT_SHIFT)))
174
175 /* Index of endpoint */
176 #define UDC_EP0IN_IDX 0
177 #define UDC_EP0OUT_IDX 1
178 #define UDC_EPIN_IDX(ep) (ep * 2)
179 #define UDC_EPOUT_IDX(ep) (ep * 2 + 1)
180 #define PCH_UDC_EP0 0
181 #define PCH_UDC_EP1 1
182 #define PCH_UDC_EP2 2
183 #define PCH_UDC_EP3 3
184
185 /* Number of endpoint */
186 #define PCH_UDC_EP_NUM 32 /* Total number of EPs (16 IN,16 OUT) */
187 #define PCH_UDC_USED_EP_NUM 4 /* EP number of EP's really used */
188 /* Length Value */
189 #define PCH_UDC_BRLEN 0x0F /* Burst length */
190 #define PCH_UDC_THLEN 0x1F /* Threshold length */
191 /* Value of EP Buffer Size */
192 #define UDC_EP0IN_BUFF_SIZE 16
193 #define UDC_EPIN_BUFF_SIZE 256
194 #define UDC_EP0OUT_BUFF_SIZE 16
195 #define UDC_EPOUT_BUFF_SIZE 256
196 /* Value of EP maximum packet size */
197 #define UDC_EP0IN_MAX_PKT_SIZE 64
198 #define UDC_EP0OUT_MAX_PKT_SIZE 64
199 #define UDC_BULK_MAX_PKT_SIZE 512
200
201 /* DMA */
202 #define DMA_DIR_RX 1 /* DMA for data receive */
203 #define DMA_DIR_TX 2 /* DMA for data transmit */
204 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
205 #define UDC_DMA_MAXPACKET 65536 /* maximum packet size for DMA */
206
207 /**
208 * struct pch_udc_data_dma_desc - Structure to hold DMA descriptor information
209 * for data
210 * @status: Status quadlet
211 * @reserved: Reserved
212 * @dataptr: Buffer descriptor
213 * @next: Next descriptor
214 */
215 struct pch_udc_data_dma_desc {
216 u32 status;
217 u32 reserved;
218 u32 dataptr;
219 u32 next;
220 };
221
222 /**
223 * struct pch_udc_stp_dma_desc - Structure to hold DMA descriptor information
224 * for control data
225 * @status: Status
226 * @reserved: Reserved
227 * @data12: First setup word
228 * @data34: Second setup word
229 */
230 struct pch_udc_stp_dma_desc {
231 u32 status;
232 u32 reserved;
233 struct usb_ctrlrequest request;
234 } __attribute((packed));
235
236 /* DMA status definitions */
237 /* Buffer status */
238 #define PCH_UDC_BUFF_STS 0xC0000000
239 #define PCH_UDC_BS_HST_RDY 0x00000000
240 #define PCH_UDC_BS_DMA_BSY 0x40000000
241 #define PCH_UDC_BS_DMA_DONE 0x80000000
242 #define PCH_UDC_BS_HST_BSY 0xC0000000
243 /* Rx/Tx Status */
244 #define PCH_UDC_RXTX_STS 0x30000000
245 #define PCH_UDC_RTS_SUCC 0x00000000
246 #define PCH_UDC_RTS_DESERR 0x10000000
247 #define PCH_UDC_RTS_BUFERR 0x30000000
248 /* Last Descriptor Indication */
249 #define PCH_UDC_DMA_LAST 0x08000000
250 /* Number of Rx/Tx Bytes Mask */
251 #define PCH_UDC_RXTX_BYTES 0x0000ffff
252
253 /**
254 * struct pch_udc_cfg_data - Structure to hold current configuration
255 * and interface information
256 * @cur_cfg: current configuration in use
257 * @cur_intf: current interface in use
258 * @cur_alt: current alt interface in use
259 */
260 struct pch_udc_cfg_data {
261 u16 cur_cfg;
262 u16 cur_intf;
263 u16 cur_alt;
264 };
265
266 /**
267 * struct pch_udc_ep - Structure holding a PCH USB device Endpoint information
268 * @ep: embedded ep request
269 * @td_stp_phys: for setup request
270 * @td_data_phys: for data request
271 * @td_stp: for setup request
272 * @td_data: for data request
273 * @dev: reference to device struct
274 * @offset_addr: offset address of ep register
275 * @desc: for this ep
276 * @queue: queue for requests
277 * @num: endpoint number
278 * @in: endpoint is IN
279 * @halted: endpoint halted?
280 * @epsts: Endpoint status
281 */
282 struct pch_udc_ep {
283 struct usb_ep ep;
284 dma_addr_t td_stp_phys;
285 dma_addr_t td_data_phys;
286 struct pch_udc_stp_dma_desc *td_stp;
287 struct pch_udc_data_dma_desc *td_data;
288 struct pch_udc_dev *dev;
289 unsigned long offset_addr;
290 const struct usb_endpoint_descriptor *desc;
291 struct list_head queue;
292 unsigned num:5,
293 in:1,
294 halted:1;
295 unsigned long epsts;
296 };
297
298 /**
299 * struct pch_udc_dev - Structure holding complete information
300 * of the PCH USB device
301 * @gadget: gadget driver data
302 * @driver: reference to gadget driver bound
303 * @pdev: reference to the PCI device
304 * @ep: array of endpoints
305 * @lock: protects all state
306 * @active: enabled the PCI device
307 * @stall: stall requested
308 * @prot_stall: protcol stall requested
309 * @irq_registered: irq registered with system
310 * @mem_region: device memory mapped
311 * @registered: driver regsitered with system
312 * @suspended: driver in suspended state
313 * @connected: gadget driver associated
314 * @vbus_session: required vbus_session state
315 * @set_cfg_not_acked: pending acknowledgement 4 setup
316 * @waiting_zlp_ack: pending acknowledgement 4 ZLP
317 * @data_requests: DMA pool for data requests
318 * @stp_requests: DMA pool for setup requests
319 * @dma_addr: DMA pool for received
320 * @ep0out_buf: Buffer for DMA
321 * @setup_data: Received setup data
322 * @phys_addr: of device memory
323 * @base_addr: for mapped device memory
324 * @irq: IRQ line for the device
325 * @cfg_data: current cfg, intf, and alt in use
326 */
327 struct pch_udc_dev {
328 struct usb_gadget gadget;
329 struct usb_gadget_driver *driver;
330 struct pci_dev *pdev;
331 struct pch_udc_ep ep[PCH_UDC_EP_NUM];
332 spinlock_t lock; /* protects all state */
333 unsigned active:1,
334 stall:1,
335 prot_stall:1,
336 irq_registered:1,
337 mem_region:1,
338 registered:1,
339 suspended:1,
340 connected:1,
341 vbus_session:1,
342 set_cfg_not_acked:1,
343 waiting_zlp_ack:1;
344 struct pci_pool *data_requests;
345 struct pci_pool *stp_requests;
346 dma_addr_t dma_addr;
347 void *ep0out_buf;
348 struct usb_ctrlrequest setup_data;
349 unsigned long phys_addr;
350 void __iomem *base_addr;
351 unsigned irq;
352 struct pch_udc_cfg_data cfg_data;
353 };
354
355 #define PCH_UDC_PCI_BAR 1
356 #define PCI_DEVICE_ID_INTEL_EG20T_UDC 0x8808
357 #define PCI_VENDOR_ID_ROHM 0x10DB
358 #define PCI_DEVICE_ID_ML7213_IOH_UDC 0x801D
359 #define PCI_DEVICE_ID_ML7831_IOH_UDC 0x8808
360
361 static const char ep0_string[] = "ep0in";
362 static DEFINE_SPINLOCK(udc_stall_spinlock); /* stall spin lock */
363 struct pch_udc_dev *pch_udc; /* pointer to device object */
364 static bool speed_fs;
365 module_param_named(speed_fs, speed_fs, bool, S_IRUGO);
366 MODULE_PARM_DESC(speed_fs, "true for Full speed operation");
367
368 /**
369 * struct pch_udc_request - Structure holding a PCH USB device request packet
370 * @req: embedded ep request
371 * @td_data_phys: phys. address
372 * @td_data: first dma desc. of chain
373 * @td_data_last: last dma desc. of chain
374 * @queue: associated queue
375 * @dma_going: DMA in progress for request
376 * @dma_mapped: DMA memory mapped for request
377 * @dma_done: DMA completed for request
378 * @chain_len: chain length
379 * @buf: Buffer memory for align adjustment
380 * @dma: DMA memory for align adjustment
381 */
382 struct pch_udc_request {
383 struct usb_request req;
384 dma_addr_t td_data_phys;
385 struct pch_udc_data_dma_desc *td_data;
386 struct pch_udc_data_dma_desc *td_data_last;
387 struct list_head queue;
388 unsigned dma_going:1,
389 dma_mapped:1,
390 dma_done:1;
391 unsigned chain_len;
392 void *buf;
393 dma_addr_t dma;
394 };
395
396 static inline u32 pch_udc_readl(struct pch_udc_dev *dev, unsigned long reg)
397 {
398 return ioread32(dev->base_addr + reg);
399 }
400
401 static inline void pch_udc_writel(struct pch_udc_dev *dev,
402 unsigned long val, unsigned long reg)
403 {
404 iowrite32(val, dev->base_addr + reg);
405 }
406
407 static inline void pch_udc_bit_set(struct pch_udc_dev *dev,
408 unsigned long reg,
409 unsigned long bitmask)
410 {
411 pch_udc_writel(dev, pch_udc_readl(dev, reg) | bitmask, reg);
412 }
413
414 static inline void pch_udc_bit_clr(struct pch_udc_dev *dev,
415 unsigned long reg,
416 unsigned long bitmask)
417 {
418 pch_udc_writel(dev, pch_udc_readl(dev, reg) & ~(bitmask), reg);
419 }
420
421 static inline u32 pch_udc_ep_readl(struct pch_udc_ep *ep, unsigned long reg)
422 {
423 return ioread32(ep->dev->base_addr + ep->offset_addr + reg);
424 }
425
426 static inline void pch_udc_ep_writel(struct pch_udc_ep *ep,
427 unsigned long val, unsigned long reg)
428 {
429 iowrite32(val, ep->dev->base_addr + ep->offset_addr + reg);
430 }
431
432 static inline void pch_udc_ep_bit_set(struct pch_udc_ep *ep,
433 unsigned long reg,
434 unsigned long bitmask)
435 {
436 pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) | bitmask, reg);
437 }
438
439 static inline void pch_udc_ep_bit_clr(struct pch_udc_ep *ep,
440 unsigned long reg,
441 unsigned long bitmask)
442 {
443 pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) & ~(bitmask), reg);
444 }
445
446 /**
447 * pch_udc_csr_busy() - Wait till idle.
448 * @dev: Reference to pch_udc_dev structure
449 */
450 static void pch_udc_csr_busy(struct pch_udc_dev *dev)
451 {
452 unsigned int count = 200;
453
454 /* Wait till idle */
455 while ((pch_udc_readl(dev, UDC_CSR_BUSY_ADDR) & UDC_CSR_BUSY)
456 && --count)
457 cpu_relax();
458 if (!count)
459 dev_err(&dev->pdev->dev, "%s: wait error\n", __func__);
460 }
461
462 /**
463 * pch_udc_write_csr() - Write the command and status registers.
464 * @dev: Reference to pch_udc_dev structure
465 * @val: value to be written to CSR register
466 * @addr: address of CSR register
467 */
468 static void pch_udc_write_csr(struct pch_udc_dev *dev, unsigned long val,
469 unsigned int ep)
470 {
471 unsigned long reg = PCH_UDC_CSR(ep);
472
473 pch_udc_csr_busy(dev); /* Wait till idle */
474 pch_udc_writel(dev, val, reg);
475 pch_udc_csr_busy(dev); /* Wait till idle */
476 }
477
478 /**
479 * pch_udc_read_csr() - Read the command and status registers.
480 * @dev: Reference to pch_udc_dev structure
481 * @addr: address of CSR register
482 *
483 * Return codes: content of CSR register
484 */
485 static u32 pch_udc_read_csr(struct pch_udc_dev *dev, unsigned int ep)
486 {
487 unsigned long reg = PCH_UDC_CSR(ep);
488
489 pch_udc_csr_busy(dev); /* Wait till idle */
490 pch_udc_readl(dev, reg); /* Dummy read */
491 pch_udc_csr_busy(dev); /* Wait till idle */
492 return pch_udc_readl(dev, reg);
493 }
494
495 /**
496 * pch_udc_rmt_wakeup() - Initiate for remote wakeup
497 * @dev: Reference to pch_udc_dev structure
498 */
499 static inline void pch_udc_rmt_wakeup(struct pch_udc_dev *dev)
500 {
501 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
502 mdelay(1);
503 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
504 }
505
506 /**
507 * pch_udc_get_frame() - Get the current frame from device status register
508 * @dev: Reference to pch_udc_dev structure
509 * Retern current frame
510 */
511 static inline int pch_udc_get_frame(struct pch_udc_dev *dev)
512 {
513 u32 frame = pch_udc_readl(dev, UDC_DEVSTS_ADDR);
514 return (frame & UDC_DEVSTS_TS_MASK) >> UDC_DEVSTS_TS_SHIFT;
515 }
516
517 /**
518 * pch_udc_clear_selfpowered() - Clear the self power control
519 * @dev: Reference to pch_udc_regs structure
520 */
521 static inline void pch_udc_clear_selfpowered(struct pch_udc_dev *dev)
522 {
523 pch_udc_bit_clr(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
524 }
525
526 /**
527 * pch_udc_set_selfpowered() - Set the self power control
528 * @dev: Reference to pch_udc_regs structure
529 */
530 static inline void pch_udc_set_selfpowered(struct pch_udc_dev *dev)
531 {
532 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
533 }
534
535 /**
536 * pch_udc_set_disconnect() - Set the disconnect status.
537 * @dev: Reference to pch_udc_regs structure
538 */
539 static inline void pch_udc_set_disconnect(struct pch_udc_dev *dev)
540 {
541 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
542 }
543
544 /**
545 * pch_udc_clear_disconnect() - Clear the disconnect status.
546 * @dev: Reference to pch_udc_regs structure
547 */
548 static void pch_udc_clear_disconnect(struct pch_udc_dev *dev)
549 {
550 /* Clear the disconnect */
551 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
552 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
553 mdelay(1);
554 /* Resume USB signalling */
555 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
556 }
557
558 /**
559 * pch_udc_reconnect() - This API initializes usb device controller,
560 * and clear the disconnect status.
561 * @dev: Reference to pch_udc_regs structure
562 */
563 static void pch_udc_init(struct pch_udc_dev *dev);
564 static void pch_udc_reconnect(struct pch_udc_dev *dev)
565 {
566 pch_udc_init(dev);
567
568 /* enable device interrupts */
569 /* pch_udc_enable_interrupts() */
570 pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR,
571 UDC_DEVINT_UR | UDC_DEVINT_ENUM);
572
573 /* Clear the disconnect */
574 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
575 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
576 mdelay(1);
577 /* Resume USB signalling */
578 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
579 }
580
581 /**
582 * pch_udc_vbus_session() - set or clearr the disconnect status.
583 * @dev: Reference to pch_udc_regs structure
584 * @is_active: Parameter specifying the action
585 * 0: indicating VBUS power is ending
586 * !0: indicating VBUS power is starting
587 */
588 static inline void pch_udc_vbus_session(struct pch_udc_dev *dev,
589 int is_active)
590 {
591 if (is_active) {
592 pch_udc_reconnect(dev);
593 dev->vbus_session = 1;
594 } else {
595 if (dev->driver && dev->driver->disconnect) {
596 spin_unlock(&dev->lock);
597 dev->driver->disconnect(&dev->gadget);
598 spin_lock(&dev->lock);
599 }
600 pch_udc_set_disconnect(dev);
601 dev->vbus_session = 0;
602 }
603 }
604
605 /**
606 * pch_udc_ep_set_stall() - Set the stall of endpoint
607 * @ep: Reference to structure of type pch_udc_ep_regs
608 */
609 static void pch_udc_ep_set_stall(struct pch_udc_ep *ep)
610 {
611 if (ep->in) {
612 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
613 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
614 } else {
615 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
616 }
617 }
618
619 /**
620 * pch_udc_ep_clear_stall() - Clear the stall of endpoint
621 * @ep: Reference to structure of type pch_udc_ep_regs
622 */
623 static inline void pch_udc_ep_clear_stall(struct pch_udc_ep *ep)
624 {
625 /* Clear the stall */
626 pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
627 /* Clear NAK by writing CNAK */
628 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
629 }
630
631 /**
632 * pch_udc_ep_set_trfr_type() - Set the transfer type of endpoint
633 * @ep: Reference to structure of type pch_udc_ep_regs
634 * @type: Type of endpoint
635 */
636 static inline void pch_udc_ep_set_trfr_type(struct pch_udc_ep *ep,
637 u8 type)
638 {
639 pch_udc_ep_writel(ep, ((type << UDC_EPCTL_ET_SHIFT) &
640 UDC_EPCTL_ET_MASK), UDC_EPCTL_ADDR);
641 }
642
643 /**
644 * pch_udc_ep_set_bufsz() - Set the maximum packet size for the endpoint
645 * @ep: Reference to structure of type pch_udc_ep_regs
646 * @buf_size: The buffer word size
647 */
648 static void pch_udc_ep_set_bufsz(struct pch_udc_ep *ep,
649 u32 buf_size, u32 ep_in)
650 {
651 u32 data;
652 if (ep_in) {
653 data = pch_udc_ep_readl(ep, UDC_BUFIN_FRAMENUM_ADDR);
654 data = (data & 0xffff0000) | (buf_size & 0xffff);
655 pch_udc_ep_writel(ep, data, UDC_BUFIN_FRAMENUM_ADDR);
656 } else {
657 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
658 data = (buf_size << 16) | (data & 0xffff);
659 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
660 }
661 }
662
663 /**
664 * pch_udc_ep_set_maxpkt() - Set the Max packet size for the endpoint
665 * @ep: Reference to structure of type pch_udc_ep_regs
666 * @pkt_size: The packet byte size
667 */
668 static void pch_udc_ep_set_maxpkt(struct pch_udc_ep *ep, u32 pkt_size)
669 {
670 u32 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
671 data = (data & 0xffff0000) | (pkt_size & 0xffff);
672 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
673 }
674
675 /**
676 * pch_udc_ep_set_subptr() - Set the Setup buffer pointer for the endpoint
677 * @ep: Reference to structure of type pch_udc_ep_regs
678 * @addr: Address of the register
679 */
680 static inline void pch_udc_ep_set_subptr(struct pch_udc_ep *ep, u32 addr)
681 {
682 pch_udc_ep_writel(ep, addr, UDC_SUBPTR_ADDR);
683 }
684
685 /**
686 * pch_udc_ep_set_ddptr() - Set the Data descriptor pointer for the endpoint
687 * @ep: Reference to structure of type pch_udc_ep_regs
688 * @addr: Address of the register
689 */
690 static inline void pch_udc_ep_set_ddptr(struct pch_udc_ep *ep, u32 addr)
691 {
692 pch_udc_ep_writel(ep, addr, UDC_DESPTR_ADDR);
693 }
694
695 /**
696 * pch_udc_ep_set_pd() - Set the poll demand bit for the endpoint
697 * @ep: Reference to structure of type pch_udc_ep_regs
698 */
699 static inline void pch_udc_ep_set_pd(struct pch_udc_ep *ep)
700 {
701 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_P);
702 }
703
704 /**
705 * pch_udc_ep_set_rrdy() - Set the receive ready bit for the endpoint
706 * @ep: Reference to structure of type pch_udc_ep_regs
707 */
708 static inline void pch_udc_ep_set_rrdy(struct pch_udc_ep *ep)
709 {
710 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
711 }
712
713 /**
714 * pch_udc_ep_clear_rrdy() - Clear the receive ready bit for the endpoint
715 * @ep: Reference to structure of type pch_udc_ep_regs
716 */
717 static inline void pch_udc_ep_clear_rrdy(struct pch_udc_ep *ep)
718 {
719 pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
720 }
721
722 /**
723 * pch_udc_set_dma() - Set the 'TDE' or RDE bit of device control
724 * register depending on the direction specified
725 * @dev: Reference to structure of type pch_udc_regs
726 * @dir: whether Tx or Rx
727 * DMA_DIR_RX: Receive
728 * DMA_DIR_TX: Transmit
729 */
730 static inline void pch_udc_set_dma(struct pch_udc_dev *dev, int dir)
731 {
732 if (dir == DMA_DIR_RX)
733 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
734 else if (dir == DMA_DIR_TX)
735 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
736 }
737
738 /**
739 * pch_udc_clear_dma() - Clear the 'TDE' or RDE bit of device control
740 * register depending on the direction specified
741 * @dev: Reference to structure of type pch_udc_regs
742 * @dir: Whether Tx or Rx
743 * DMA_DIR_RX: Receive
744 * DMA_DIR_TX: Transmit
745 */
746 static inline void pch_udc_clear_dma(struct pch_udc_dev *dev, int dir)
747 {
748 if (dir == DMA_DIR_RX)
749 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
750 else if (dir == DMA_DIR_TX)
751 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
752 }
753
754 /**
755 * pch_udc_set_csr_done() - Set the device control register
756 * CSR done field (bit 13)
757 * @dev: reference to structure of type pch_udc_regs
758 */
759 static inline void pch_udc_set_csr_done(struct pch_udc_dev *dev)
760 {
761 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_CSR_DONE);
762 }
763
764 /**
765 * pch_udc_disable_interrupts() - Disables the specified interrupts
766 * @dev: Reference to structure of type pch_udc_regs
767 * @mask: Mask to disable interrupts
768 */
769 static inline void pch_udc_disable_interrupts(struct pch_udc_dev *dev,
770 u32 mask)
771 {
772 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, mask);
773 }
774
775 /**
776 * pch_udc_enable_interrupts() - Enable the specified interrupts
777 * @dev: Reference to structure of type pch_udc_regs
778 * @mask: Mask to enable interrupts
779 */
780 static inline void pch_udc_enable_interrupts(struct pch_udc_dev *dev,
781 u32 mask)
782 {
783 pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR, mask);
784 }
785
786 /**
787 * pch_udc_disable_ep_interrupts() - Disable endpoint interrupts
788 * @dev: Reference to structure of type pch_udc_regs
789 * @mask: Mask to disable interrupts
790 */
791 static inline void pch_udc_disable_ep_interrupts(struct pch_udc_dev *dev,
792 u32 mask)
793 {
794 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, mask);
795 }
796
797 /**
798 * pch_udc_enable_ep_interrupts() - Enable endpoint interrupts
799 * @dev: Reference to structure of type pch_udc_regs
800 * @mask: Mask to enable interrupts
801 */
802 static inline void pch_udc_enable_ep_interrupts(struct pch_udc_dev *dev,
803 u32 mask)
804 {
805 pch_udc_bit_clr(dev, UDC_EPIRQMSK_ADDR, mask);
806 }
807
808 /**
809 * pch_udc_read_device_interrupts() - Read the device interrupts
810 * @dev: Reference to structure of type pch_udc_regs
811 * Retern The device interrupts
812 */
813 static inline u32 pch_udc_read_device_interrupts(struct pch_udc_dev *dev)
814 {
815 return pch_udc_readl(dev, UDC_DEVIRQSTS_ADDR);
816 }
817
818 /**
819 * pch_udc_write_device_interrupts() - Write device interrupts
820 * @dev: Reference to structure of type pch_udc_regs
821 * @val: The value to be written to interrupt register
822 */
823 static inline void pch_udc_write_device_interrupts(struct pch_udc_dev *dev,
824 u32 val)
825 {
826 pch_udc_writel(dev, val, UDC_DEVIRQSTS_ADDR);
827 }
828
829 /**
830 * pch_udc_read_ep_interrupts() - Read the endpoint interrupts
831 * @dev: Reference to structure of type pch_udc_regs
832 * Retern The endpoint interrupt
833 */
834 static inline u32 pch_udc_read_ep_interrupts(struct pch_udc_dev *dev)
835 {
836 return pch_udc_readl(dev, UDC_EPIRQSTS_ADDR);
837 }
838
839 /**
840 * pch_udc_write_ep_interrupts() - Clear endpoint interupts
841 * @dev: Reference to structure of type pch_udc_regs
842 * @val: The value to be written to interrupt register
843 */
844 static inline void pch_udc_write_ep_interrupts(struct pch_udc_dev *dev,
845 u32 val)
846 {
847 pch_udc_writel(dev, val, UDC_EPIRQSTS_ADDR);
848 }
849
850 /**
851 * pch_udc_read_device_status() - Read the device status
852 * @dev: Reference to structure of type pch_udc_regs
853 * Retern The device status
854 */
855 static inline u32 pch_udc_read_device_status(struct pch_udc_dev *dev)
856 {
857 return pch_udc_readl(dev, UDC_DEVSTS_ADDR);
858 }
859
860 /**
861 * pch_udc_read_ep_control() - Read the endpoint control
862 * @ep: Reference to structure of type pch_udc_ep_regs
863 * Retern The endpoint control register value
864 */
865 static inline u32 pch_udc_read_ep_control(struct pch_udc_ep *ep)
866 {
867 return pch_udc_ep_readl(ep, UDC_EPCTL_ADDR);
868 }
869
870 /**
871 * pch_udc_clear_ep_control() - Clear the endpoint control register
872 * @ep: Reference to structure of type pch_udc_ep_regs
873 * Retern The endpoint control register value
874 */
875 static inline void pch_udc_clear_ep_control(struct pch_udc_ep *ep)
876 {
877 return pch_udc_ep_writel(ep, 0, UDC_EPCTL_ADDR);
878 }
879
880 /**
881 * pch_udc_read_ep_status() - Read the endpoint status
882 * @ep: Reference to structure of type pch_udc_ep_regs
883 * Retern The endpoint status
884 */
885 static inline u32 pch_udc_read_ep_status(struct pch_udc_ep *ep)
886 {
887 return pch_udc_ep_readl(ep, UDC_EPSTS_ADDR);
888 }
889
890 /**
891 * pch_udc_clear_ep_status() - Clear the endpoint status
892 * @ep: Reference to structure of type pch_udc_ep_regs
893 * @stat: Endpoint status
894 */
895 static inline void pch_udc_clear_ep_status(struct pch_udc_ep *ep,
896 u32 stat)
897 {
898 return pch_udc_ep_writel(ep, stat, UDC_EPSTS_ADDR);
899 }
900
901 /**
902 * pch_udc_ep_set_nak() - Set the bit 7 (SNAK field)
903 * of the endpoint control register
904 * @ep: Reference to structure of type pch_udc_ep_regs
905 */
906 static inline void pch_udc_ep_set_nak(struct pch_udc_ep *ep)
907 {
908 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_SNAK);
909 }
910
911 /**
912 * pch_udc_ep_clear_nak() - Set the bit 8 (CNAK field)
913 * of the endpoint control register
914 * @ep: reference to structure of type pch_udc_ep_regs
915 */
916 static void pch_udc_ep_clear_nak(struct pch_udc_ep *ep)
917 {
918 unsigned int loopcnt = 0;
919 struct pch_udc_dev *dev = ep->dev;
920
921 if (!(pch_udc_ep_readl(ep, UDC_EPCTL_ADDR) & UDC_EPCTL_NAK))
922 return;
923 if (!ep->in) {
924 loopcnt = 10000;
925 while (!(pch_udc_read_ep_status(ep) & UDC_EPSTS_MRXFIFO_EMP) &&
926 --loopcnt)
927 udelay(5);
928 if (!loopcnt)
929 dev_err(&dev->pdev->dev, "%s: RxFIFO not Empty\n",
930 __func__);
931 }
932 loopcnt = 10000;
933 while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_NAK) && --loopcnt) {
934 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
935 udelay(5);
936 }
937 if (!loopcnt)
938 dev_err(&dev->pdev->dev, "%s: Clear NAK not set for ep%d%s\n",
939 __func__, ep->num, (ep->in ? "in" : "out"));
940 }
941
942 /**
943 * pch_udc_ep_fifo_flush() - Flush the endpoint fifo
944 * @ep: reference to structure of type pch_udc_ep_regs
945 * @dir: direction of endpoint
946 * 0: endpoint is OUT
947 * !0: endpoint is IN
948 */
949 static void pch_udc_ep_fifo_flush(struct pch_udc_ep *ep, int dir)
950 {
951 if (dir) { /* IN ep */
952 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
953 return;
954 }
955 }
956
957 /**
958 * pch_udc_ep_enable() - This api enables endpoint
959 * @regs: Reference to structure pch_udc_ep_regs
960 * @desc: endpoint descriptor
961 */
962 static void pch_udc_ep_enable(struct pch_udc_ep *ep,
963 struct pch_udc_cfg_data *cfg,
964 const struct usb_endpoint_descriptor *desc)
965 {
966 u32 val = 0;
967 u32 buff_size = 0;
968
969 pch_udc_ep_set_trfr_type(ep, desc->bmAttributes);
970 if (ep->in)
971 buff_size = UDC_EPIN_BUFF_SIZE;
972 else
973 buff_size = UDC_EPOUT_BUFF_SIZE;
974 pch_udc_ep_set_bufsz(ep, buff_size, ep->in);
975 pch_udc_ep_set_maxpkt(ep, usb_endpoint_maxp(desc));
976 pch_udc_ep_set_nak(ep);
977 pch_udc_ep_fifo_flush(ep, ep->in);
978 /* Configure the endpoint */
979 val = ep->num << UDC_CSR_NE_NUM_SHIFT | ep->in << UDC_CSR_NE_DIR_SHIFT |
980 ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) <<
981 UDC_CSR_NE_TYPE_SHIFT) |
982 (cfg->cur_cfg << UDC_CSR_NE_CFG_SHIFT) |
983 (cfg->cur_intf << UDC_CSR_NE_INTF_SHIFT) |
984 (cfg->cur_alt << UDC_CSR_NE_ALT_SHIFT) |
985 usb_endpoint_maxp(desc) << UDC_CSR_NE_MAX_PKT_SHIFT;
986
987 if (ep->in)
988 pch_udc_write_csr(ep->dev, val, UDC_EPIN_IDX(ep->num));
989 else
990 pch_udc_write_csr(ep->dev, val, UDC_EPOUT_IDX(ep->num));
991 }
992
993 /**
994 * pch_udc_ep_disable() - This api disables endpoint
995 * @regs: Reference to structure pch_udc_ep_regs
996 */
997 static void pch_udc_ep_disable(struct pch_udc_ep *ep)
998 {
999 if (ep->in) {
1000 /* flush the fifo */
1001 pch_udc_ep_writel(ep, UDC_EPCTL_F, UDC_EPCTL_ADDR);
1002 /* set NAK */
1003 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
1004 pch_udc_ep_bit_set(ep, UDC_EPSTS_ADDR, UDC_EPSTS_IN);
1005 } else {
1006 /* set NAK */
1007 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
1008 }
1009 /* reset desc pointer */
1010 pch_udc_ep_writel(ep, 0, UDC_DESPTR_ADDR);
1011 }
1012
1013 /**
1014 * pch_udc_wait_ep_stall() - Wait EP stall.
1015 * @dev: Reference to pch_udc_dev structure
1016 */
1017 static void pch_udc_wait_ep_stall(struct pch_udc_ep *ep)
1018 {
1019 unsigned int count = 10000;
1020
1021 /* Wait till idle */
1022 while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_S) && --count)
1023 udelay(5);
1024 if (!count)
1025 dev_err(&ep->dev->pdev->dev, "%s: wait error\n", __func__);
1026 }
1027
1028 /**
1029 * pch_udc_init() - This API initializes usb device controller
1030 * @dev: Rreference to pch_udc_regs structure
1031 */
1032 static void pch_udc_init(struct pch_udc_dev *dev)
1033 {
1034 if (NULL == dev) {
1035 pr_err("%s: Invalid address\n", __func__);
1036 return;
1037 }
1038 /* Soft Reset and Reset PHY */
1039 pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1040 pch_udc_writel(dev, UDC_SRST | UDC_PSRST, UDC_SRST_ADDR);
1041 mdelay(1);
1042 pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1043 pch_udc_writel(dev, 0x00, UDC_SRST_ADDR);
1044 mdelay(1);
1045 /* mask and clear all device interrupts */
1046 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1047 pch_udc_bit_set(dev, UDC_DEVIRQSTS_ADDR, UDC_DEVINT_MSK);
1048
1049 /* mask and clear all ep interrupts */
1050 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1051 pch_udc_bit_set(dev, UDC_EPIRQSTS_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1052
1053 /* enable dynamic CSR programmingi, self powered and device speed */
1054 if (speed_fs)
1055 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1056 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_FS);
1057 else /* defaul high speed */
1058 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1059 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_HS);
1060 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR,
1061 (PCH_UDC_THLEN << UDC_DEVCTL_THLEN_SHIFT) |
1062 (PCH_UDC_BRLEN << UDC_DEVCTL_BRLEN_SHIFT) |
1063 UDC_DEVCTL_MODE | UDC_DEVCTL_BREN |
1064 UDC_DEVCTL_THE);
1065 }
1066
1067 /**
1068 * pch_udc_exit() - This API exit usb device controller
1069 * @dev: Reference to pch_udc_regs structure
1070 */
1071 static void pch_udc_exit(struct pch_udc_dev *dev)
1072 {
1073 /* mask all device interrupts */
1074 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1075 /* mask all ep interrupts */
1076 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1077 /* put device in disconnected state */
1078 pch_udc_set_disconnect(dev);
1079 }
1080
1081 /**
1082 * pch_udc_pcd_get_frame() - This API is invoked to get the current frame number
1083 * @gadget: Reference to the gadget driver
1084 *
1085 * Return codes:
1086 * 0: Success
1087 * -EINVAL: If the gadget passed is NULL
1088 */
1089 static int pch_udc_pcd_get_frame(struct usb_gadget *gadget)
1090 {
1091 struct pch_udc_dev *dev;
1092
1093 if (!gadget)
1094 return -EINVAL;
1095 dev = container_of(gadget, struct pch_udc_dev, gadget);
1096 return pch_udc_get_frame(dev);
1097 }
1098
1099 /**
1100 * pch_udc_pcd_wakeup() - This API is invoked to initiate a remote wakeup
1101 * @gadget: Reference to the gadget driver
1102 *
1103 * Return codes:
1104 * 0: Success
1105 * -EINVAL: If the gadget passed is NULL
1106 */
1107 static int pch_udc_pcd_wakeup(struct usb_gadget *gadget)
1108 {
1109 struct pch_udc_dev *dev;
1110 unsigned long flags;
1111
1112 if (!gadget)
1113 return -EINVAL;
1114 dev = container_of(gadget, struct pch_udc_dev, gadget);
1115 spin_lock_irqsave(&dev->lock, flags);
1116 pch_udc_rmt_wakeup(dev);
1117 spin_unlock_irqrestore(&dev->lock, flags);
1118 return 0;
1119 }
1120
1121 /**
1122 * pch_udc_pcd_selfpowered() - This API is invoked to specify whether the device
1123 * is self powered or not
1124 * @gadget: Reference to the gadget driver
1125 * @value: Specifies self powered or not
1126 *
1127 * Return codes:
1128 * 0: Success
1129 * -EINVAL: If the gadget passed is NULL
1130 */
1131 static int pch_udc_pcd_selfpowered(struct usb_gadget *gadget, int value)
1132 {
1133 struct pch_udc_dev *dev;
1134
1135 if (!gadget)
1136 return -EINVAL;
1137 dev = container_of(gadget, struct pch_udc_dev, gadget);
1138 if (value)
1139 pch_udc_set_selfpowered(dev);
1140 else
1141 pch_udc_clear_selfpowered(dev);
1142 return 0;
1143 }
1144
1145 /**
1146 * pch_udc_pcd_pullup() - This API is invoked to make the device
1147 * visible/invisible to the host
1148 * @gadget: Reference to the gadget driver
1149 * @is_on: Specifies whether the pull up is made active or inactive
1150 *
1151 * Return codes:
1152 * 0: Success
1153 * -EINVAL: If the gadget passed is NULL
1154 */
1155 static int pch_udc_pcd_pullup(struct usb_gadget *gadget, int is_on)
1156 {
1157 struct pch_udc_dev *dev;
1158
1159 if (!gadget)
1160 return -EINVAL;
1161 dev = container_of(gadget, struct pch_udc_dev, gadget);
1162 if (is_on) {
1163 pch_udc_reconnect(dev);
1164 } else {
1165 if (dev->driver && dev->driver->disconnect) {
1166 spin_unlock(&dev->lock);
1167 dev->driver->disconnect(&dev->gadget);
1168 spin_lock(&dev->lock);
1169 }
1170 pch_udc_set_disconnect(dev);
1171 }
1172
1173 return 0;
1174 }
1175
1176 /**
1177 * pch_udc_pcd_vbus_session() - This API is used by a driver for an external
1178 * transceiver (or GPIO) that
1179 * detects a VBUS power session starting/ending
1180 * @gadget: Reference to the gadget driver
1181 * @is_active: specifies whether the session is starting or ending
1182 *
1183 * Return codes:
1184 * 0: Success
1185 * -EINVAL: If the gadget passed is NULL
1186 */
1187 static int pch_udc_pcd_vbus_session(struct usb_gadget *gadget, int is_active)
1188 {
1189 struct pch_udc_dev *dev;
1190
1191 if (!gadget)
1192 return -EINVAL;
1193 dev = container_of(gadget, struct pch_udc_dev, gadget);
1194 pch_udc_vbus_session(dev, is_active);
1195 return 0;
1196 }
1197
1198 /**
1199 * pch_udc_pcd_vbus_draw() - This API is used by gadget drivers during
1200 * SET_CONFIGURATION calls to
1201 * specify how much power the device can consume
1202 * @gadget: Reference to the gadget driver
1203 * @mA: specifies the current limit in 2mA unit
1204 *
1205 * Return codes:
1206 * -EINVAL: If the gadget passed is NULL
1207 * -EOPNOTSUPP:
1208 */
1209 static int pch_udc_pcd_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
1210 {
1211 return -EOPNOTSUPP;
1212 }
1213
1214 static int pch_udc_start(struct usb_gadget_driver *driver,
1215 int (*bind)(struct usb_gadget *));
1216 static int pch_udc_stop(struct usb_gadget_driver *driver);
1217 static const struct usb_gadget_ops pch_udc_ops = {
1218 .get_frame = pch_udc_pcd_get_frame,
1219 .wakeup = pch_udc_pcd_wakeup,
1220 .set_selfpowered = pch_udc_pcd_selfpowered,
1221 .pullup = pch_udc_pcd_pullup,
1222 .vbus_session = pch_udc_pcd_vbus_session,
1223 .vbus_draw = pch_udc_pcd_vbus_draw,
1224 .start = pch_udc_start,
1225 .stop = pch_udc_stop,
1226 };
1227
1228 /**
1229 * complete_req() - This API is invoked from the driver when processing
1230 * of a request is complete
1231 * @ep: Reference to the endpoint structure
1232 * @req: Reference to the request structure
1233 * @status: Indicates the success/failure of completion
1234 */
1235 static void complete_req(struct pch_udc_ep *ep, struct pch_udc_request *req,
1236 int status)
1237 {
1238 struct pch_udc_dev *dev;
1239 unsigned halted = ep->halted;
1240
1241 list_del_init(&req->queue);
1242
1243 /* set new status if pending */
1244 if (req->req.status == -EINPROGRESS)
1245 req->req.status = status;
1246 else
1247 status = req->req.status;
1248
1249 dev = ep->dev;
1250 if (req->dma_mapped) {
1251 if (req->dma == DMA_ADDR_INVALID) {
1252 if (ep->in)
1253 dma_unmap_single(&dev->pdev->dev, req->req.dma,
1254 req->req.length,
1255 DMA_TO_DEVICE);
1256 else
1257 dma_unmap_single(&dev->pdev->dev, req->req.dma,
1258 req->req.length,
1259 DMA_FROM_DEVICE);
1260 req->req.dma = DMA_ADDR_INVALID;
1261 } else {
1262 if (ep->in)
1263 dma_unmap_single(&dev->pdev->dev, req->dma,
1264 req->req.length,
1265 DMA_TO_DEVICE);
1266 else {
1267 dma_unmap_single(&dev->pdev->dev, req->dma,
1268 req->req.length,
1269 DMA_FROM_DEVICE);
1270 memcpy(req->req.buf, req->buf, req->req.length);
1271 }
1272 kfree(req->buf);
1273 req->dma = DMA_ADDR_INVALID;
1274 }
1275 req->dma_mapped = 0;
1276 }
1277 ep->halted = 1;
1278 spin_unlock(&dev->lock);
1279 if (!ep->in)
1280 pch_udc_ep_clear_rrdy(ep);
1281 req->req.complete(&ep->ep, &req->req);
1282 spin_lock(&dev->lock);
1283 ep->halted = halted;
1284 }
1285
1286 /**
1287 * empty_req_queue() - This API empties the request queue of an endpoint
1288 * @ep: Reference to the endpoint structure
1289 */
1290 static void empty_req_queue(struct pch_udc_ep *ep)
1291 {
1292 struct pch_udc_request *req;
1293
1294 ep->halted = 1;
1295 while (!list_empty(&ep->queue)) {
1296 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1297 complete_req(ep, req, -ESHUTDOWN); /* Remove from list */
1298 }
1299 }
1300
1301 /**
1302 * pch_udc_free_dma_chain() - This function frees the DMA chain created
1303 * for the request
1304 * @dev Reference to the driver structure
1305 * @req Reference to the request to be freed
1306 *
1307 * Return codes:
1308 * 0: Success
1309 */
1310 static void pch_udc_free_dma_chain(struct pch_udc_dev *dev,
1311 struct pch_udc_request *req)
1312 {
1313 struct pch_udc_data_dma_desc *td = req->td_data;
1314 unsigned i = req->chain_len;
1315
1316 dma_addr_t addr2;
1317 dma_addr_t addr = (dma_addr_t)td->next;
1318 td->next = 0x00;
1319 for (; i > 1; --i) {
1320 /* do not free first desc., will be done by free for request */
1321 td = phys_to_virt(addr);
1322 addr2 = (dma_addr_t)td->next;
1323 pci_pool_free(dev->data_requests, td, addr);
1324 td->next = 0x00;
1325 addr = addr2;
1326 }
1327 req->chain_len = 1;
1328 }
1329
1330 /**
1331 * pch_udc_create_dma_chain() - This function creates or reinitializes
1332 * a DMA chain
1333 * @ep: Reference to the endpoint structure
1334 * @req: Reference to the request
1335 * @buf_len: The buffer length
1336 * @gfp_flags: Flags to be used while mapping the data buffer
1337 *
1338 * Return codes:
1339 * 0: success,
1340 * -ENOMEM: pci_pool_alloc invocation fails
1341 */
1342 static int pch_udc_create_dma_chain(struct pch_udc_ep *ep,
1343 struct pch_udc_request *req,
1344 unsigned long buf_len,
1345 gfp_t gfp_flags)
1346 {
1347 struct pch_udc_data_dma_desc *td = req->td_data, *last;
1348 unsigned long bytes = req->req.length, i = 0;
1349 dma_addr_t dma_addr;
1350 unsigned len = 1;
1351
1352 if (req->chain_len > 1)
1353 pch_udc_free_dma_chain(ep->dev, req);
1354
1355 if (req->dma == DMA_ADDR_INVALID)
1356 td->dataptr = req->req.dma;
1357 else
1358 td->dataptr = req->dma;
1359
1360 td->status = PCH_UDC_BS_HST_BSY;
1361 for (; ; bytes -= buf_len, ++len) {
1362 td->status = PCH_UDC_BS_HST_BSY | min(buf_len, bytes);
1363 if (bytes <= buf_len)
1364 break;
1365 last = td;
1366 td = pci_pool_alloc(ep->dev->data_requests, gfp_flags,
1367 &dma_addr);
1368 if (!td)
1369 goto nomem;
1370 i += buf_len;
1371 td->dataptr = req->td_data->dataptr + i;
1372 last->next = dma_addr;
1373 }
1374
1375 req->td_data_last = td;
1376 td->status |= PCH_UDC_DMA_LAST;
1377 td->next = req->td_data_phys;
1378 req->chain_len = len;
1379 return 0;
1380
1381 nomem:
1382 if (len > 1) {
1383 req->chain_len = len;
1384 pch_udc_free_dma_chain(ep->dev, req);
1385 }
1386 req->chain_len = 1;
1387 return -ENOMEM;
1388 }
1389
1390 /**
1391 * prepare_dma() - This function creates and initializes the DMA chain
1392 * for the request
1393 * @ep: Reference to the endpoint structure
1394 * @req: Reference to the request
1395 * @gfp: Flag to be used while mapping the data buffer
1396 *
1397 * Return codes:
1398 * 0: Success
1399 * Other 0: linux error number on failure
1400 */
1401 static int prepare_dma(struct pch_udc_ep *ep, struct pch_udc_request *req,
1402 gfp_t gfp)
1403 {
1404 int retval;
1405
1406 /* Allocate and create a DMA chain */
1407 retval = pch_udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
1408 if (retval) {
1409 pr_err("%s: could not create DMA chain:%d\n", __func__, retval);
1410 return retval;
1411 }
1412 if (ep->in)
1413 req->td_data->status = (req->td_data->status &
1414 ~PCH_UDC_BUFF_STS) | PCH_UDC_BS_HST_RDY;
1415 return 0;
1416 }
1417
1418 /**
1419 * process_zlp() - This function process zero length packets
1420 * from the gadget driver
1421 * @ep: Reference to the endpoint structure
1422 * @req: Reference to the request
1423 */
1424 static void process_zlp(struct pch_udc_ep *ep, struct pch_udc_request *req)
1425 {
1426 struct pch_udc_dev *dev = ep->dev;
1427
1428 /* IN zlp's are handled by hardware */
1429 complete_req(ep, req, 0);
1430
1431 /* if set_config or set_intf is waiting for ack by zlp
1432 * then set CSR_DONE
1433 */
1434 if (dev->set_cfg_not_acked) {
1435 pch_udc_set_csr_done(dev);
1436 dev->set_cfg_not_acked = 0;
1437 }
1438 /* setup command is ACK'ed now by zlp */
1439 if (!dev->stall && dev->waiting_zlp_ack) {
1440 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
1441 dev->waiting_zlp_ack = 0;
1442 }
1443 }
1444
1445 /**
1446 * pch_udc_start_rxrequest() - This function starts the receive requirement.
1447 * @ep: Reference to the endpoint structure
1448 * @req: Reference to the request structure
1449 */
1450 static void pch_udc_start_rxrequest(struct pch_udc_ep *ep,
1451 struct pch_udc_request *req)
1452 {
1453 struct pch_udc_data_dma_desc *td_data;
1454
1455 pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
1456 td_data = req->td_data;
1457 /* Set the status bits for all descriptors */
1458 while (1) {
1459 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
1460 PCH_UDC_BS_HST_RDY;
1461 if ((td_data->status & PCH_UDC_DMA_LAST) == PCH_UDC_DMA_LAST)
1462 break;
1463 td_data = phys_to_virt(td_data->next);
1464 }
1465 /* Write the descriptor pointer */
1466 pch_udc_ep_set_ddptr(ep, req->td_data_phys);
1467 req->dma_going = 1;
1468 pch_udc_enable_ep_interrupts(ep->dev, UDC_EPINT_OUT_EP0 << ep->num);
1469 pch_udc_set_dma(ep->dev, DMA_DIR_RX);
1470 pch_udc_ep_clear_nak(ep);
1471 pch_udc_ep_set_rrdy(ep);
1472 }
1473
1474 /**
1475 * pch_udc_pcd_ep_enable() - This API enables the endpoint. It is called
1476 * from gadget driver
1477 * @usbep: Reference to the USB endpoint structure
1478 * @desc: Reference to the USB endpoint descriptor structure
1479 *
1480 * Return codes:
1481 * 0: Success
1482 * -EINVAL:
1483 * -ESHUTDOWN:
1484 */
1485 static int pch_udc_pcd_ep_enable(struct usb_ep *usbep,
1486 const struct usb_endpoint_descriptor *desc)
1487 {
1488 struct pch_udc_ep *ep;
1489 struct pch_udc_dev *dev;
1490 unsigned long iflags;
1491
1492 if (!usbep || (usbep->name == ep0_string) || !desc ||
1493 (desc->bDescriptorType != USB_DT_ENDPOINT) || !desc->wMaxPacketSize)
1494 return -EINVAL;
1495
1496 ep = container_of(usbep, struct pch_udc_ep, ep);
1497 dev = ep->dev;
1498 if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1499 return -ESHUTDOWN;
1500 spin_lock_irqsave(&dev->lock, iflags);
1501 ep->desc = desc;
1502 ep->halted = 0;
1503 pch_udc_ep_enable(ep, &ep->dev->cfg_data, desc);
1504 ep->ep.maxpacket = usb_endpoint_maxp(desc);
1505 pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1506 spin_unlock_irqrestore(&dev->lock, iflags);
1507 return 0;
1508 }
1509
1510 /**
1511 * pch_udc_pcd_ep_disable() - This API disables endpoint and is called
1512 * from gadget driver
1513 * @usbep Reference to the USB endpoint structure
1514 *
1515 * Return codes:
1516 * 0: Success
1517 * -EINVAL:
1518 */
1519 static int pch_udc_pcd_ep_disable(struct usb_ep *usbep)
1520 {
1521 struct pch_udc_ep *ep;
1522 struct pch_udc_dev *dev;
1523 unsigned long iflags;
1524
1525 if (!usbep)
1526 return -EINVAL;
1527
1528 ep = container_of(usbep, struct pch_udc_ep, ep);
1529 dev = ep->dev;
1530 if ((usbep->name == ep0_string) || !ep->desc)
1531 return -EINVAL;
1532
1533 spin_lock_irqsave(&ep->dev->lock, iflags);
1534 empty_req_queue(ep);
1535 ep->halted = 1;
1536 pch_udc_ep_disable(ep);
1537 pch_udc_disable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1538 ep->desc = NULL;
1539 ep->ep.desc = NULL;
1540 INIT_LIST_HEAD(&ep->queue);
1541 spin_unlock_irqrestore(&ep->dev->lock, iflags);
1542 return 0;
1543 }
1544
1545 /**
1546 * pch_udc_alloc_request() - This function allocates request structure.
1547 * It is called by gadget driver
1548 * @usbep: Reference to the USB endpoint structure
1549 * @gfp: Flag to be used while allocating memory
1550 *
1551 * Return codes:
1552 * NULL: Failure
1553 * Allocated address: Success
1554 */
1555 static struct usb_request *pch_udc_alloc_request(struct usb_ep *usbep,
1556 gfp_t gfp)
1557 {
1558 struct pch_udc_request *req;
1559 struct pch_udc_ep *ep;
1560 struct pch_udc_data_dma_desc *dma_desc;
1561 struct pch_udc_dev *dev;
1562
1563 if (!usbep)
1564 return NULL;
1565 ep = container_of(usbep, struct pch_udc_ep, ep);
1566 dev = ep->dev;
1567 req = kzalloc(sizeof *req, gfp);
1568 if (!req)
1569 return NULL;
1570 req->req.dma = DMA_ADDR_INVALID;
1571 req->dma = DMA_ADDR_INVALID;
1572 INIT_LIST_HEAD(&req->queue);
1573 if (!ep->dev->dma_addr)
1574 return &req->req;
1575 /* ep0 in requests are allocated from data pool here */
1576 dma_desc = pci_pool_alloc(ep->dev->data_requests, gfp,
1577 &req->td_data_phys);
1578 if (NULL == dma_desc) {
1579 kfree(req);
1580 return NULL;
1581 }
1582 /* prevent from using desc. - set HOST BUSY */
1583 dma_desc->status |= PCH_UDC_BS_HST_BSY;
1584 dma_desc->dataptr = __constant_cpu_to_le32(DMA_ADDR_INVALID);
1585 req->td_data = dma_desc;
1586 req->td_data_last = dma_desc;
1587 req->chain_len = 1;
1588 return &req->req;
1589 }
1590
1591 /**
1592 * pch_udc_free_request() - This function frees request structure.
1593 * It is called by gadget driver
1594 * @usbep: Reference to the USB endpoint structure
1595 * @usbreq: Reference to the USB request
1596 */
1597 static void pch_udc_free_request(struct usb_ep *usbep,
1598 struct usb_request *usbreq)
1599 {
1600 struct pch_udc_ep *ep;
1601 struct pch_udc_request *req;
1602 struct pch_udc_dev *dev;
1603
1604 if (!usbep || !usbreq)
1605 return;
1606 ep = container_of(usbep, struct pch_udc_ep, ep);
1607 req = container_of(usbreq, struct pch_udc_request, req);
1608 dev = ep->dev;
1609 if (!list_empty(&req->queue))
1610 dev_err(&dev->pdev->dev, "%s: %s req=0x%p queue not empty\n",
1611 __func__, usbep->name, req);
1612 if (req->td_data != NULL) {
1613 if (req->chain_len > 1)
1614 pch_udc_free_dma_chain(ep->dev, req);
1615 pci_pool_free(ep->dev->data_requests, req->td_data,
1616 req->td_data_phys);
1617 }
1618 kfree(req);
1619 }
1620
1621 /**
1622 * pch_udc_pcd_queue() - This function queues a request packet. It is called
1623 * by gadget driver
1624 * @usbep: Reference to the USB endpoint structure
1625 * @usbreq: Reference to the USB request
1626 * @gfp: Flag to be used while mapping the data buffer
1627 *
1628 * Return codes:
1629 * 0: Success
1630 * linux error number: Failure
1631 */
1632 static int pch_udc_pcd_queue(struct usb_ep *usbep, struct usb_request *usbreq,
1633 gfp_t gfp)
1634 {
1635 int retval = 0;
1636 struct pch_udc_ep *ep;
1637 struct pch_udc_dev *dev;
1638 struct pch_udc_request *req;
1639 unsigned long iflags;
1640
1641 if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf)
1642 return -EINVAL;
1643 ep = container_of(usbep, struct pch_udc_ep, ep);
1644 dev = ep->dev;
1645 if (!ep->desc && ep->num)
1646 return -EINVAL;
1647 req = container_of(usbreq, struct pch_udc_request, req);
1648 if (!list_empty(&req->queue))
1649 return -EINVAL;
1650 if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1651 return -ESHUTDOWN;
1652 spin_lock_irqsave(&dev->lock, iflags);
1653 /* map the buffer for dma */
1654 if (usbreq->length &&
1655 ((usbreq->dma == DMA_ADDR_INVALID) || !usbreq->dma)) {
1656 if (!((unsigned long)(usbreq->buf) & 0x03)) {
1657 if (ep->in)
1658 usbreq->dma = dma_map_single(&dev->pdev->dev,
1659 usbreq->buf,
1660 usbreq->length,
1661 DMA_TO_DEVICE);
1662 else
1663 usbreq->dma = dma_map_single(&dev->pdev->dev,
1664 usbreq->buf,
1665 usbreq->length,
1666 DMA_FROM_DEVICE);
1667 } else {
1668 req->buf = kzalloc(usbreq->length, GFP_ATOMIC);
1669 if (!req->buf) {
1670 retval = -ENOMEM;
1671 goto probe_end;
1672 }
1673 if (ep->in) {
1674 memcpy(req->buf, usbreq->buf, usbreq->length);
1675 req->dma = dma_map_single(&dev->pdev->dev,
1676 req->buf,
1677 usbreq->length,
1678 DMA_TO_DEVICE);
1679 } else
1680 req->dma = dma_map_single(&dev->pdev->dev,
1681 req->buf,
1682 usbreq->length,
1683 DMA_FROM_DEVICE);
1684 }
1685 req->dma_mapped = 1;
1686 }
1687 if (usbreq->length > 0) {
1688 retval = prepare_dma(ep, req, GFP_ATOMIC);
1689 if (retval)
1690 goto probe_end;
1691 }
1692 usbreq->actual = 0;
1693 usbreq->status = -EINPROGRESS;
1694 req->dma_done = 0;
1695 if (list_empty(&ep->queue) && !ep->halted) {
1696 /* no pending transfer, so start this req */
1697 if (!usbreq->length) {
1698 process_zlp(ep, req);
1699 retval = 0;
1700 goto probe_end;
1701 }
1702 if (!ep->in) {
1703 pch_udc_start_rxrequest(ep, req);
1704 } else {
1705 /*
1706 * For IN trfr the descriptors will be programmed and
1707 * P bit will be set when
1708 * we get an IN token
1709 */
1710 pch_udc_wait_ep_stall(ep);
1711 pch_udc_ep_clear_nak(ep);
1712 pch_udc_enable_ep_interrupts(ep->dev, (1 << ep->num));
1713 }
1714 }
1715 /* Now add this request to the ep's pending requests */
1716 if (req != NULL)
1717 list_add_tail(&req->queue, &ep->queue);
1718
1719 probe_end:
1720 spin_unlock_irqrestore(&dev->lock, iflags);
1721 return retval;
1722 }
1723
1724 /**
1725 * pch_udc_pcd_dequeue() - This function de-queues a request packet.
1726 * It is called by gadget driver
1727 * @usbep: Reference to the USB endpoint structure
1728 * @usbreq: Reference to the USB request
1729 *
1730 * Return codes:
1731 * 0: Success
1732 * linux error number: Failure
1733 */
1734 static int pch_udc_pcd_dequeue(struct usb_ep *usbep,
1735 struct usb_request *usbreq)
1736 {
1737 struct pch_udc_ep *ep;
1738 struct pch_udc_request *req;
1739 struct pch_udc_dev *dev;
1740 unsigned long flags;
1741 int ret = -EINVAL;
1742
1743 ep = container_of(usbep, struct pch_udc_ep, ep);
1744 dev = ep->dev;
1745 if (!usbep || !usbreq || (!ep->desc && ep->num))
1746 return ret;
1747 req = container_of(usbreq, struct pch_udc_request, req);
1748 spin_lock_irqsave(&ep->dev->lock, flags);
1749 /* make sure it's still queued on this endpoint */
1750 list_for_each_entry(req, &ep->queue, queue) {
1751 if (&req->req == usbreq) {
1752 pch_udc_ep_set_nak(ep);
1753 if (!list_empty(&req->queue))
1754 complete_req(ep, req, -ECONNRESET);
1755 ret = 0;
1756 break;
1757 }
1758 }
1759 spin_unlock_irqrestore(&ep->dev->lock, flags);
1760 return ret;
1761 }
1762
1763 /**
1764 * pch_udc_pcd_set_halt() - This function Sets or clear the endpoint halt
1765 * feature
1766 * @usbep: Reference to the USB endpoint structure
1767 * @halt: Specifies whether to set or clear the feature
1768 *
1769 * Return codes:
1770 * 0: Success
1771 * linux error number: Failure
1772 */
1773 static int pch_udc_pcd_set_halt(struct usb_ep *usbep, int halt)
1774 {
1775 struct pch_udc_ep *ep;
1776 struct pch_udc_dev *dev;
1777 unsigned long iflags;
1778 int ret;
1779
1780 if (!usbep)
1781 return -EINVAL;
1782 ep = container_of(usbep, struct pch_udc_ep, ep);
1783 dev = ep->dev;
1784 if (!ep->desc && !ep->num)
1785 return -EINVAL;
1786 if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
1787 return -ESHUTDOWN;
1788 spin_lock_irqsave(&udc_stall_spinlock, iflags);
1789 if (list_empty(&ep->queue)) {
1790 if (halt) {
1791 if (ep->num == PCH_UDC_EP0)
1792 ep->dev->stall = 1;
1793 pch_udc_ep_set_stall(ep);
1794 pch_udc_enable_ep_interrupts(ep->dev,
1795 PCH_UDC_EPINT(ep->in,
1796 ep->num));
1797 } else {
1798 pch_udc_ep_clear_stall(ep);
1799 }
1800 ret = 0;
1801 } else {
1802 ret = -EAGAIN;
1803 }
1804 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1805 return ret;
1806 }
1807
1808 /**
1809 * pch_udc_pcd_set_wedge() - This function Sets or clear the endpoint
1810 * halt feature
1811 * @usbep: Reference to the USB endpoint structure
1812 * @halt: Specifies whether to set or clear the feature
1813 *
1814 * Return codes:
1815 * 0: Success
1816 * linux error number: Failure
1817 */
1818 static int pch_udc_pcd_set_wedge(struct usb_ep *usbep)
1819 {
1820 struct pch_udc_ep *ep;
1821 struct pch_udc_dev *dev;
1822 unsigned long iflags;
1823 int ret;
1824
1825 if (!usbep)
1826 return -EINVAL;
1827 ep = container_of(usbep, struct pch_udc_ep, ep);
1828 dev = ep->dev;
1829 if (!ep->desc && !ep->num)
1830 return -EINVAL;
1831 if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
1832 return -ESHUTDOWN;
1833 spin_lock_irqsave(&udc_stall_spinlock, iflags);
1834 if (!list_empty(&ep->queue)) {
1835 ret = -EAGAIN;
1836 } else {
1837 if (ep->num == PCH_UDC_EP0)
1838 ep->dev->stall = 1;
1839 pch_udc_ep_set_stall(ep);
1840 pch_udc_enable_ep_interrupts(ep->dev,
1841 PCH_UDC_EPINT(ep->in, ep->num));
1842 ep->dev->prot_stall = 1;
1843 ret = 0;
1844 }
1845 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1846 return ret;
1847 }
1848
1849 /**
1850 * pch_udc_pcd_fifo_flush() - This function Flush the FIFO of specified endpoint
1851 * @usbep: Reference to the USB endpoint structure
1852 */
1853 static void pch_udc_pcd_fifo_flush(struct usb_ep *usbep)
1854 {
1855 struct pch_udc_ep *ep;
1856
1857 if (!usbep)
1858 return;
1859
1860 ep = container_of(usbep, struct pch_udc_ep, ep);
1861 if (ep->desc || !ep->num)
1862 pch_udc_ep_fifo_flush(ep, ep->in);
1863 }
1864
1865 static const struct usb_ep_ops pch_udc_ep_ops = {
1866 .enable = pch_udc_pcd_ep_enable,
1867 .disable = pch_udc_pcd_ep_disable,
1868 .alloc_request = pch_udc_alloc_request,
1869 .free_request = pch_udc_free_request,
1870 .queue = pch_udc_pcd_queue,
1871 .dequeue = pch_udc_pcd_dequeue,
1872 .set_halt = pch_udc_pcd_set_halt,
1873 .set_wedge = pch_udc_pcd_set_wedge,
1874 .fifo_status = NULL,
1875 .fifo_flush = pch_udc_pcd_fifo_flush,
1876 };
1877
1878 /**
1879 * pch_udc_init_setup_buff() - This function initializes the SETUP buffer
1880 * @td_stp: Reference to the SETP buffer structure
1881 */
1882 static void pch_udc_init_setup_buff(struct pch_udc_stp_dma_desc *td_stp)
1883 {
1884 static u32 pky_marker;
1885
1886 if (!td_stp)
1887 return;
1888 td_stp->reserved = ++pky_marker;
1889 memset(&td_stp->request, 0xFF, sizeof td_stp->request);
1890 td_stp->status = PCH_UDC_BS_HST_RDY;
1891 }
1892
1893 /**
1894 * pch_udc_start_next_txrequest() - This function starts
1895 * the next transmission requirement
1896 * @ep: Reference to the endpoint structure
1897 */
1898 static void pch_udc_start_next_txrequest(struct pch_udc_ep *ep)
1899 {
1900 struct pch_udc_request *req;
1901 struct pch_udc_data_dma_desc *td_data;
1902
1903 if (pch_udc_read_ep_control(ep) & UDC_EPCTL_P)
1904 return;
1905
1906 if (list_empty(&ep->queue))
1907 return;
1908
1909 /* next request */
1910 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1911 if (req->dma_going)
1912 return;
1913 if (!req->td_data)
1914 return;
1915 pch_udc_wait_ep_stall(ep);
1916 req->dma_going = 1;
1917 pch_udc_ep_set_ddptr(ep, 0);
1918 td_data = req->td_data;
1919 while (1) {
1920 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
1921 PCH_UDC_BS_HST_RDY;
1922 if ((td_data->status & PCH_UDC_DMA_LAST) == PCH_UDC_DMA_LAST)
1923 break;
1924 td_data = phys_to_virt(td_data->next);
1925 }
1926 pch_udc_ep_set_ddptr(ep, req->td_data_phys);
1927 pch_udc_set_dma(ep->dev, DMA_DIR_TX);
1928 pch_udc_ep_set_pd(ep);
1929 pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1930 pch_udc_ep_clear_nak(ep);
1931 }
1932
1933 /**
1934 * pch_udc_complete_transfer() - This function completes a transfer
1935 * @ep: Reference to the endpoint structure
1936 */
1937 static void pch_udc_complete_transfer(struct pch_udc_ep *ep)
1938 {
1939 struct pch_udc_request *req;
1940 struct pch_udc_dev *dev = ep->dev;
1941
1942 if (list_empty(&ep->queue))
1943 return;
1944 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1945 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
1946 PCH_UDC_BS_DMA_DONE)
1947 return;
1948 if ((req->td_data_last->status & PCH_UDC_RXTX_STS) !=
1949 PCH_UDC_RTS_SUCC) {
1950 dev_err(&dev->pdev->dev, "Invalid RXTX status (0x%08x) "
1951 "epstatus=0x%08x\n",
1952 (req->td_data_last->status & PCH_UDC_RXTX_STS),
1953 (int)(ep->epsts));
1954 return;
1955 }
1956
1957 req->req.actual = req->req.length;
1958 req->td_data_last->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
1959 req->td_data->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
1960 complete_req(ep, req, 0);
1961 req->dma_going = 0;
1962 if (!list_empty(&ep->queue)) {
1963 pch_udc_wait_ep_stall(ep);
1964 pch_udc_ep_clear_nak(ep);
1965 pch_udc_enable_ep_interrupts(ep->dev,
1966 PCH_UDC_EPINT(ep->in, ep->num));
1967 } else {
1968 pch_udc_disable_ep_interrupts(ep->dev,
1969 PCH_UDC_EPINT(ep->in, ep->num));
1970 }
1971 }
1972
1973 /**
1974 * pch_udc_complete_receiver() - This function completes a receiver
1975 * @ep: Reference to the endpoint structure
1976 */
1977 static void pch_udc_complete_receiver(struct pch_udc_ep *ep)
1978 {
1979 struct pch_udc_request *req;
1980 struct pch_udc_dev *dev = ep->dev;
1981 unsigned int count;
1982 struct pch_udc_data_dma_desc *td;
1983 dma_addr_t addr;
1984
1985 if (list_empty(&ep->queue))
1986 return;
1987 /* next request */
1988 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1989 pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
1990 pch_udc_ep_set_ddptr(ep, 0);
1991 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) ==
1992 PCH_UDC_BS_DMA_DONE)
1993 td = req->td_data_last;
1994 else
1995 td = req->td_data;
1996
1997 while (1) {
1998 if ((td->status & PCH_UDC_RXTX_STS) != PCH_UDC_RTS_SUCC) {
1999 dev_err(&dev->pdev->dev, "Invalid RXTX status=0x%08x "
2000 "epstatus=0x%08x\n",
2001 (req->td_data->status & PCH_UDC_RXTX_STS),
2002 (int)(ep->epsts));
2003 return;
2004 }
2005 if ((td->status & PCH_UDC_BUFF_STS) == PCH_UDC_BS_DMA_DONE)
2006 if (td->status | PCH_UDC_DMA_LAST) {
2007 count = td->status & PCH_UDC_RXTX_BYTES;
2008 break;
2009 }
2010 if (td == req->td_data_last) {
2011 dev_err(&dev->pdev->dev, "Not complete RX descriptor");
2012 return;
2013 }
2014 addr = (dma_addr_t)td->next;
2015 td = phys_to_virt(addr);
2016 }
2017 /* on 64k packets the RXBYTES field is zero */
2018 if (!count && (req->req.length == UDC_DMA_MAXPACKET))
2019 count = UDC_DMA_MAXPACKET;
2020 req->td_data->status |= PCH_UDC_DMA_LAST;
2021 td->status |= PCH_UDC_BS_HST_BSY;
2022
2023 req->dma_going = 0;
2024 req->req.actual = count;
2025 complete_req(ep, req, 0);
2026 /* If there is a new/failed requests try that now */
2027 if (!list_empty(&ep->queue)) {
2028 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2029 pch_udc_start_rxrequest(ep, req);
2030 }
2031 }
2032
2033 /**
2034 * pch_udc_svc_data_in() - This function process endpoint interrupts
2035 * for IN endpoints
2036 * @dev: Reference to the device structure
2037 * @ep_num: Endpoint that generated the interrupt
2038 */
2039 static void pch_udc_svc_data_in(struct pch_udc_dev *dev, int ep_num)
2040 {
2041 u32 epsts;
2042 struct pch_udc_ep *ep;
2043
2044 ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2045 epsts = ep->epsts;
2046 ep->epsts = 0;
2047
2048 if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA | UDC_EPSTS_HE |
2049 UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
2050 UDC_EPSTS_RSS | UDC_EPSTS_XFERDONE)))
2051 return;
2052 if ((epsts & UDC_EPSTS_BNA))
2053 return;
2054 if (epsts & UDC_EPSTS_HE)
2055 return;
2056 if (epsts & UDC_EPSTS_RSS) {
2057 pch_udc_ep_set_stall(ep);
2058 pch_udc_enable_ep_interrupts(ep->dev,
2059 PCH_UDC_EPINT(ep->in, ep->num));
2060 }
2061 if (epsts & UDC_EPSTS_RCS) {
2062 if (!dev->prot_stall) {
2063 pch_udc_ep_clear_stall(ep);
2064 } else {
2065 pch_udc_ep_set_stall(ep);
2066 pch_udc_enable_ep_interrupts(ep->dev,
2067 PCH_UDC_EPINT(ep->in, ep->num));
2068 }
2069 }
2070 if (epsts & UDC_EPSTS_TDC)
2071 pch_udc_complete_transfer(ep);
2072 /* On IN interrupt, provide data if we have any */
2073 if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_RSS) &&
2074 !(epsts & UDC_EPSTS_TDC) && !(epsts & UDC_EPSTS_TXEMPTY))
2075 pch_udc_start_next_txrequest(ep);
2076 }
2077
2078 /**
2079 * pch_udc_svc_data_out() - Handles interrupts from OUT endpoint
2080 * @dev: Reference to the device structure
2081 * @ep_num: Endpoint that generated the interrupt
2082 */
2083 static void pch_udc_svc_data_out(struct pch_udc_dev *dev, int ep_num)
2084 {
2085 u32 epsts;
2086 struct pch_udc_ep *ep;
2087 struct pch_udc_request *req = NULL;
2088
2089 ep = &dev->ep[UDC_EPOUT_IDX(ep_num)];
2090 epsts = ep->epsts;
2091 ep->epsts = 0;
2092
2093 if ((epsts & UDC_EPSTS_BNA) && (!list_empty(&ep->queue))) {
2094 /* next request */
2095 req = list_entry(ep->queue.next, struct pch_udc_request,
2096 queue);
2097 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
2098 PCH_UDC_BS_DMA_DONE) {
2099 if (!req->dma_going)
2100 pch_udc_start_rxrequest(ep, req);
2101 return;
2102 }
2103 }
2104 if (epsts & UDC_EPSTS_HE)
2105 return;
2106 if (epsts & UDC_EPSTS_RSS) {
2107 pch_udc_ep_set_stall(ep);
2108 pch_udc_enable_ep_interrupts(ep->dev,
2109 PCH_UDC_EPINT(ep->in, ep->num));
2110 }
2111 if (epsts & UDC_EPSTS_RCS) {
2112 if (!dev->prot_stall) {
2113 pch_udc_ep_clear_stall(ep);
2114 } else {
2115 pch_udc_ep_set_stall(ep);
2116 pch_udc_enable_ep_interrupts(ep->dev,
2117 PCH_UDC_EPINT(ep->in, ep->num));
2118 }
2119 }
2120 if (((epsts & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2121 UDC_EPSTS_OUT_DATA) {
2122 if (ep->dev->prot_stall == 1) {
2123 pch_udc_ep_set_stall(ep);
2124 pch_udc_enable_ep_interrupts(ep->dev,
2125 PCH_UDC_EPINT(ep->in, ep->num));
2126 } else {
2127 pch_udc_complete_receiver(ep);
2128 }
2129 }
2130 if (list_empty(&ep->queue))
2131 pch_udc_set_dma(dev, DMA_DIR_RX);
2132 }
2133
2134 /**
2135 * pch_udc_svc_control_in() - Handle Control IN endpoint interrupts
2136 * @dev: Reference to the device structure
2137 */
2138 static void pch_udc_svc_control_in(struct pch_udc_dev *dev)
2139 {
2140 u32 epsts;
2141 struct pch_udc_ep *ep;
2142 struct pch_udc_ep *ep_out;
2143
2144 ep = &dev->ep[UDC_EP0IN_IDX];
2145 ep_out = &dev->ep[UDC_EP0OUT_IDX];
2146 epsts = ep->epsts;
2147 ep->epsts = 0;
2148
2149 if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA | UDC_EPSTS_HE |
2150 UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
2151 UDC_EPSTS_XFERDONE)))
2152 return;
2153 if ((epsts & UDC_EPSTS_BNA))
2154 return;
2155 if (epsts & UDC_EPSTS_HE)
2156 return;
2157 if ((epsts & UDC_EPSTS_TDC) && (!dev->stall)) {
2158 pch_udc_complete_transfer(ep);
2159 pch_udc_clear_dma(dev, DMA_DIR_RX);
2160 ep_out->td_data->status = (ep_out->td_data->status &
2161 ~PCH_UDC_BUFF_STS) |
2162 PCH_UDC_BS_HST_RDY;
2163 pch_udc_ep_clear_nak(ep_out);
2164 pch_udc_set_dma(dev, DMA_DIR_RX);
2165 pch_udc_ep_set_rrdy(ep_out);
2166 }
2167 /* On IN interrupt, provide data if we have any */
2168 if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_TDC) &&
2169 !(epsts & UDC_EPSTS_TXEMPTY))
2170 pch_udc_start_next_txrequest(ep);
2171 }
2172
2173 /**
2174 * pch_udc_svc_control_out() - Routine that handle Control
2175 * OUT endpoint interrupts
2176 * @dev: Reference to the device structure
2177 */
2178 static void pch_udc_svc_control_out(struct pch_udc_dev *dev)
2179 {
2180 u32 stat;
2181 int setup_supported;
2182 struct pch_udc_ep *ep;
2183
2184 ep = &dev->ep[UDC_EP0OUT_IDX];
2185 stat = ep->epsts;
2186 ep->epsts = 0;
2187
2188 /* If setup data */
2189 if (((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2190 UDC_EPSTS_OUT_SETUP) {
2191 dev->stall = 0;
2192 dev->ep[UDC_EP0IN_IDX].halted = 0;
2193 dev->ep[UDC_EP0OUT_IDX].halted = 0;
2194 dev->setup_data = ep->td_stp->request;
2195 pch_udc_init_setup_buff(ep->td_stp);
2196 pch_udc_clear_dma(dev, DMA_DIR_RX);
2197 pch_udc_ep_fifo_flush(&(dev->ep[UDC_EP0IN_IDX]),
2198 dev->ep[UDC_EP0IN_IDX].in);
2199 if ((dev->setup_data.bRequestType & USB_DIR_IN))
2200 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2201 else /* OUT */
2202 dev->gadget.ep0 = &ep->ep;
2203 spin_unlock(&dev->lock);
2204 /* If Mass storage Reset */
2205 if ((dev->setup_data.bRequestType == 0x21) &&
2206 (dev->setup_data.bRequest == 0xFF))
2207 dev->prot_stall = 0;
2208 /* call gadget with setup data received */
2209 setup_supported = dev->driver->setup(&dev->gadget,
2210 &dev->setup_data);
2211 spin_lock(&dev->lock);
2212
2213 if (dev->setup_data.bRequestType & USB_DIR_IN) {
2214 ep->td_data->status = (ep->td_data->status &
2215 ~PCH_UDC_BUFF_STS) |
2216 PCH_UDC_BS_HST_RDY;
2217 pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2218 }
2219 /* ep0 in returns data on IN phase */
2220 if (setup_supported >= 0 && setup_supported <
2221 UDC_EP0IN_MAX_PKT_SIZE) {
2222 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
2223 /* Gadget would have queued a request when
2224 * we called the setup */
2225 if (!(dev->setup_data.bRequestType & USB_DIR_IN)) {
2226 pch_udc_set_dma(dev, DMA_DIR_RX);
2227 pch_udc_ep_clear_nak(ep);
2228 }
2229 } else if (setup_supported < 0) {
2230 /* if unsupported request, then stall */
2231 pch_udc_ep_set_stall(&(dev->ep[UDC_EP0IN_IDX]));
2232 pch_udc_enable_ep_interrupts(ep->dev,
2233 PCH_UDC_EPINT(ep->in, ep->num));
2234 dev->stall = 0;
2235 pch_udc_set_dma(dev, DMA_DIR_RX);
2236 } else {
2237 dev->waiting_zlp_ack = 1;
2238 }
2239 } else if ((((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2240 UDC_EPSTS_OUT_DATA) && !dev->stall) {
2241 pch_udc_clear_dma(dev, DMA_DIR_RX);
2242 pch_udc_ep_set_ddptr(ep, 0);
2243 if (!list_empty(&ep->queue)) {
2244 ep->epsts = stat;
2245 pch_udc_svc_data_out(dev, PCH_UDC_EP0);
2246 }
2247 pch_udc_set_dma(dev, DMA_DIR_RX);
2248 }
2249 pch_udc_ep_set_rrdy(ep);
2250 }
2251
2252
2253 /**
2254 * pch_udc_postsvc_epinters() - This function enables end point interrupts
2255 * and clears NAK status
2256 * @dev: Reference to the device structure
2257 * @ep_num: End point number
2258 */
2259 static void pch_udc_postsvc_epinters(struct pch_udc_dev *dev, int ep_num)
2260 {
2261 struct pch_udc_ep *ep;
2262 struct pch_udc_request *req;
2263
2264 ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2265 if (!list_empty(&ep->queue)) {
2266 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2267 pch_udc_enable_ep_interrupts(ep->dev,
2268 PCH_UDC_EPINT(ep->in, ep->num));
2269 pch_udc_ep_clear_nak(ep);
2270 }
2271 }
2272
2273 /**
2274 * pch_udc_read_all_epstatus() - This function read all endpoint status
2275 * @dev: Reference to the device structure
2276 * @ep_intr: Status of endpoint interrupt
2277 */
2278 static void pch_udc_read_all_epstatus(struct pch_udc_dev *dev, u32 ep_intr)
2279 {
2280 int i;
2281 struct pch_udc_ep *ep;
2282
2283 for (i = 0; i < PCH_UDC_USED_EP_NUM; i++) {
2284 /* IN */
2285 if (ep_intr & (0x1 << i)) {
2286 ep = &dev->ep[UDC_EPIN_IDX(i)];
2287 ep->epsts = pch_udc_read_ep_status(ep);
2288 pch_udc_clear_ep_status(ep, ep->epsts);
2289 }
2290 /* OUT */
2291 if (ep_intr & (0x10000 << i)) {
2292 ep = &dev->ep[UDC_EPOUT_IDX(i)];
2293 ep->epsts = pch_udc_read_ep_status(ep);
2294 pch_udc_clear_ep_status(ep, ep->epsts);
2295 }
2296 }
2297 }
2298
2299 /**
2300 * pch_udc_activate_control_ep() - This function enables the control endpoints
2301 * for traffic after a reset
2302 * @dev: Reference to the device structure
2303 */
2304 static void pch_udc_activate_control_ep(struct pch_udc_dev *dev)
2305 {
2306 struct pch_udc_ep *ep;
2307 u32 val;
2308
2309 /* Setup the IN endpoint */
2310 ep = &dev->ep[UDC_EP0IN_IDX];
2311 pch_udc_clear_ep_control(ep);
2312 pch_udc_ep_fifo_flush(ep, ep->in);
2313 pch_udc_ep_set_bufsz(ep, UDC_EP0IN_BUFF_SIZE, ep->in);
2314 pch_udc_ep_set_maxpkt(ep, UDC_EP0IN_MAX_PKT_SIZE);
2315 /* Initialize the IN EP Descriptor */
2316 ep->td_data = NULL;
2317 ep->td_stp = NULL;
2318 ep->td_data_phys = 0;
2319 ep->td_stp_phys = 0;
2320
2321 /* Setup the OUT endpoint */
2322 ep = &dev->ep[UDC_EP0OUT_IDX];
2323 pch_udc_clear_ep_control(ep);
2324 pch_udc_ep_fifo_flush(ep, ep->in);
2325 pch_udc_ep_set_bufsz(ep, UDC_EP0OUT_BUFF_SIZE, ep->in);
2326 pch_udc_ep_set_maxpkt(ep, UDC_EP0OUT_MAX_PKT_SIZE);
2327 val = UDC_EP0OUT_MAX_PKT_SIZE << UDC_CSR_NE_MAX_PKT_SHIFT;
2328 pch_udc_write_csr(ep->dev, val, UDC_EP0OUT_IDX);
2329
2330 /* Initialize the SETUP buffer */
2331 pch_udc_init_setup_buff(ep->td_stp);
2332 /* Write the pointer address of dma descriptor */
2333 pch_udc_ep_set_subptr(ep, ep->td_stp_phys);
2334 /* Write the pointer address of Setup descriptor */
2335 pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2336
2337 /* Initialize the dma descriptor */
2338 ep->td_data->status = PCH_UDC_DMA_LAST;
2339 ep->td_data->dataptr = dev->dma_addr;
2340 ep->td_data->next = ep->td_data_phys;
2341
2342 pch_udc_ep_clear_nak(ep);
2343 }
2344
2345
2346 /**
2347 * pch_udc_svc_ur_interrupt() - This function handles a USB reset interrupt
2348 * @dev: Reference to driver structure
2349 */
2350 static void pch_udc_svc_ur_interrupt(struct pch_udc_dev *dev)
2351 {
2352 struct pch_udc_ep *ep;
2353 int i;
2354
2355 pch_udc_clear_dma(dev, DMA_DIR_TX);
2356 pch_udc_clear_dma(dev, DMA_DIR_RX);
2357 /* Mask all endpoint interrupts */
2358 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2359 /* clear all endpoint interrupts */
2360 pch_udc_write_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2361
2362 for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2363 ep = &dev->ep[i];
2364 pch_udc_clear_ep_status(ep, UDC_EPSTS_ALL_CLR_MASK);
2365 pch_udc_clear_ep_control(ep);
2366 pch_udc_ep_set_ddptr(ep, 0);
2367 pch_udc_write_csr(ep->dev, 0x00, i);
2368 }
2369 dev->stall = 0;
2370 dev->prot_stall = 0;
2371 dev->waiting_zlp_ack = 0;
2372 dev->set_cfg_not_acked = 0;
2373
2374 /* disable ep to empty req queue. Skip the control EP's */
2375 for (i = 0; i < (PCH_UDC_USED_EP_NUM*2); i++) {
2376 ep = &dev->ep[i];
2377 pch_udc_ep_set_nak(ep);
2378 pch_udc_ep_fifo_flush(ep, ep->in);
2379 /* Complete request queue */
2380 empty_req_queue(ep);
2381 }
2382 if (dev->driver && dev->driver->disconnect) {
2383 spin_unlock(&dev->lock);
2384 dev->driver->disconnect(&dev->gadget);
2385 spin_lock(&dev->lock);
2386 }
2387 }
2388
2389 /**
2390 * pch_udc_svc_enum_interrupt() - This function handles a USB speed enumeration
2391 * done interrupt
2392 * @dev: Reference to driver structure
2393 */
2394 static void pch_udc_svc_enum_interrupt(struct pch_udc_dev *dev)
2395 {
2396 u32 dev_stat, dev_speed;
2397 u32 speed = USB_SPEED_FULL;
2398
2399 dev_stat = pch_udc_read_device_status(dev);
2400 dev_speed = (dev_stat & UDC_DEVSTS_ENUM_SPEED_MASK) >>
2401 UDC_DEVSTS_ENUM_SPEED_SHIFT;
2402 switch (dev_speed) {
2403 case UDC_DEVSTS_ENUM_SPEED_HIGH:
2404 speed = USB_SPEED_HIGH;
2405 break;
2406 case UDC_DEVSTS_ENUM_SPEED_FULL:
2407 speed = USB_SPEED_FULL;
2408 break;
2409 case UDC_DEVSTS_ENUM_SPEED_LOW:
2410 speed = USB_SPEED_LOW;
2411 break;
2412 default:
2413 BUG();
2414 }
2415 dev->gadget.speed = speed;
2416 pch_udc_activate_control_ep(dev);
2417 pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 | UDC_EPINT_OUT_EP0);
2418 pch_udc_set_dma(dev, DMA_DIR_TX);
2419 pch_udc_set_dma(dev, DMA_DIR_RX);
2420 pch_udc_ep_set_rrdy(&(dev->ep[UDC_EP0OUT_IDX]));
2421
2422 /* enable device interrupts */
2423 pch_udc_enable_interrupts(dev, UDC_DEVINT_UR | UDC_DEVINT_US |
2424 UDC_DEVINT_ES | UDC_DEVINT_ENUM |
2425 UDC_DEVINT_SI | UDC_DEVINT_SC);
2426 }
2427
2428 /**
2429 * pch_udc_svc_intf_interrupt() - This function handles a set interface
2430 * interrupt
2431 * @dev: Reference to driver structure
2432 */
2433 static void pch_udc_svc_intf_interrupt(struct pch_udc_dev *dev)
2434 {
2435 u32 reg, dev_stat = 0;
2436 int i, ret;
2437
2438 dev_stat = pch_udc_read_device_status(dev);
2439 dev->cfg_data.cur_intf = (dev_stat & UDC_DEVSTS_INTF_MASK) >>
2440 UDC_DEVSTS_INTF_SHIFT;
2441 dev->cfg_data.cur_alt = (dev_stat & UDC_DEVSTS_ALT_MASK) >>
2442 UDC_DEVSTS_ALT_SHIFT;
2443 dev->set_cfg_not_acked = 1;
2444 /* Construct the usb request for gadget driver and inform it */
2445 memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2446 dev->setup_data.bRequest = USB_REQ_SET_INTERFACE;
2447 dev->setup_data.bRequestType = USB_RECIP_INTERFACE;
2448 dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_alt);
2449 dev->setup_data.wIndex = cpu_to_le16(dev->cfg_data.cur_intf);
2450 /* programm the Endpoint Cfg registers */
2451 /* Only one end point cfg register */
2452 reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2453 reg = (reg & ~UDC_CSR_NE_INTF_MASK) |
2454 (dev->cfg_data.cur_intf << UDC_CSR_NE_INTF_SHIFT);
2455 reg = (reg & ~UDC_CSR_NE_ALT_MASK) |
2456 (dev->cfg_data.cur_alt << UDC_CSR_NE_ALT_SHIFT);
2457 pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2458 for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2459 /* clear stall bits */
2460 pch_udc_ep_clear_stall(&(dev->ep[i]));
2461 dev->ep[i].halted = 0;
2462 }
2463 dev->stall = 0;
2464 spin_unlock(&dev->lock);
2465 ret = dev->driver->setup(&dev->gadget, &dev->setup_data);
2466 spin_lock(&dev->lock);
2467 }
2468
2469 /**
2470 * pch_udc_svc_cfg_interrupt() - This function handles a set configuration
2471 * interrupt
2472 * @dev: Reference to driver structure
2473 */
2474 static void pch_udc_svc_cfg_interrupt(struct pch_udc_dev *dev)
2475 {
2476 int i, ret;
2477 u32 reg, dev_stat = 0;
2478
2479 dev_stat = pch_udc_read_device_status(dev);
2480 dev->set_cfg_not_acked = 1;
2481 dev->cfg_data.cur_cfg = (dev_stat & UDC_DEVSTS_CFG_MASK) >>
2482 UDC_DEVSTS_CFG_SHIFT;
2483 /* make usb request for gadget driver */
2484 memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2485 dev->setup_data.bRequest = USB_REQ_SET_CONFIGURATION;
2486 dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_cfg);
2487 /* program the NE registers */
2488 /* Only one end point cfg register */
2489 reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2490 reg = (reg & ~UDC_CSR_NE_CFG_MASK) |
2491 (dev->cfg_data.cur_cfg << UDC_CSR_NE_CFG_SHIFT);
2492 pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2493 for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2494 /* clear stall bits */
2495 pch_udc_ep_clear_stall(&(dev->ep[i]));
2496 dev->ep[i].halted = 0;
2497 }
2498 dev->stall = 0;
2499
2500 /* call gadget zero with setup data received */
2501 spin_unlock(&dev->lock);
2502 ret = dev->driver->setup(&dev->gadget, &dev->setup_data);
2503 spin_lock(&dev->lock);
2504 }
2505
2506 /**
2507 * pch_udc_dev_isr() - This function services device interrupts
2508 * by invoking appropriate routines.
2509 * @dev: Reference to the device structure
2510 * @dev_intr: The Device interrupt status.
2511 */
2512 static void pch_udc_dev_isr(struct pch_udc_dev *dev, u32 dev_intr)
2513 {
2514 /* USB Reset Interrupt */
2515 if (dev_intr & UDC_DEVINT_UR)
2516 pch_udc_svc_ur_interrupt(dev);
2517 /* Enumeration Done Interrupt */
2518 if (dev_intr & UDC_DEVINT_ENUM)
2519 pch_udc_svc_enum_interrupt(dev);
2520 /* Set Interface Interrupt */
2521 if (dev_intr & UDC_DEVINT_SI)
2522 pch_udc_svc_intf_interrupt(dev);
2523 /* Set Config Interrupt */
2524 if (dev_intr & UDC_DEVINT_SC)
2525 pch_udc_svc_cfg_interrupt(dev);
2526 /* USB Suspend interrupt */
2527 if (dev_intr & UDC_DEVINT_US) {
2528 if (dev->driver
2529 && dev->driver->suspend) {
2530 spin_unlock(&dev->lock);
2531 dev->driver->suspend(&dev->gadget);
2532 spin_lock(&dev->lock);
2533 }
2534
2535 if (dev->vbus_session == 0) {
2536 if (dev->driver && dev->driver->disconnect) {
2537 spin_unlock(&dev->lock);
2538 dev->driver->disconnect(&dev->gadget);
2539 spin_lock(&dev->lock);
2540 }
2541 pch_udc_reconnect(dev);
2542 }
2543 dev_dbg(&dev->pdev->dev, "USB_SUSPEND\n");
2544 }
2545 /* Clear the SOF interrupt, if enabled */
2546 if (dev_intr & UDC_DEVINT_SOF)
2547 dev_dbg(&dev->pdev->dev, "SOF\n");
2548 /* ES interrupt, IDLE > 3ms on the USB */
2549 if (dev_intr & UDC_DEVINT_ES)
2550 dev_dbg(&dev->pdev->dev, "ES\n");
2551 /* RWKP interrupt */
2552 if (dev_intr & UDC_DEVINT_RWKP)
2553 dev_dbg(&dev->pdev->dev, "RWKP\n");
2554 }
2555
2556 /**
2557 * pch_udc_isr() - This function handles interrupts from the PCH USB Device
2558 * @irq: Interrupt request number
2559 * @dev: Reference to the device structure
2560 */
2561 static irqreturn_t pch_udc_isr(int irq, void *pdev)
2562 {
2563 struct pch_udc_dev *dev = (struct pch_udc_dev *) pdev;
2564 u32 dev_intr, ep_intr;
2565 int i;
2566
2567 dev_intr = pch_udc_read_device_interrupts(dev);
2568 ep_intr = pch_udc_read_ep_interrupts(dev);
2569
2570 /* For a hot plug, this find that the controller is hung up. */
2571 if (dev_intr == ep_intr)
2572 if (dev_intr == pch_udc_readl(dev, UDC_DEVCFG_ADDR)) {
2573 dev_dbg(&dev->pdev->dev, "UDC: Hung up\n");
2574 /* The controller is reset */
2575 pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
2576 return IRQ_HANDLED;
2577 }
2578 if (dev_intr)
2579 /* Clear device interrupts */
2580 pch_udc_write_device_interrupts(dev, dev_intr);
2581 if (ep_intr)
2582 /* Clear ep interrupts */
2583 pch_udc_write_ep_interrupts(dev, ep_intr);
2584 if (!dev_intr && !ep_intr)
2585 return IRQ_NONE;
2586 spin_lock(&dev->lock);
2587 if (dev_intr)
2588 pch_udc_dev_isr(dev, dev_intr);
2589 if (ep_intr) {
2590 pch_udc_read_all_epstatus(dev, ep_intr);
2591 /* Process Control In interrupts, if present */
2592 if (ep_intr & UDC_EPINT_IN_EP0) {
2593 pch_udc_svc_control_in(dev);
2594 pch_udc_postsvc_epinters(dev, 0);
2595 }
2596 /* Process Control Out interrupts, if present */
2597 if (ep_intr & UDC_EPINT_OUT_EP0)
2598 pch_udc_svc_control_out(dev);
2599 /* Process data in end point interrupts */
2600 for (i = 1; i < PCH_UDC_USED_EP_NUM; i++) {
2601 if (ep_intr & (1 << i)) {
2602 pch_udc_svc_data_in(dev, i);
2603 pch_udc_postsvc_epinters(dev, i);
2604 }
2605 }
2606 /* Process data out end point interrupts */
2607 for (i = UDC_EPINT_OUT_SHIFT + 1; i < (UDC_EPINT_OUT_SHIFT +
2608 PCH_UDC_USED_EP_NUM); i++)
2609 if (ep_intr & (1 << i))
2610 pch_udc_svc_data_out(dev, i -
2611 UDC_EPINT_OUT_SHIFT);
2612 }
2613 spin_unlock(&dev->lock);
2614 return IRQ_HANDLED;
2615 }
2616
2617 /**
2618 * pch_udc_setup_ep0() - This function enables control endpoint for traffic
2619 * @dev: Reference to the device structure
2620 */
2621 static void pch_udc_setup_ep0(struct pch_udc_dev *dev)
2622 {
2623 /* enable ep0 interrupts */
2624 pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 |
2625 UDC_EPINT_OUT_EP0);
2626 /* enable device interrupts */
2627 pch_udc_enable_interrupts(dev, UDC_DEVINT_UR | UDC_DEVINT_US |
2628 UDC_DEVINT_ES | UDC_DEVINT_ENUM |
2629 UDC_DEVINT_SI | UDC_DEVINT_SC);
2630 }
2631
2632 /**
2633 * gadget_release() - Free the gadget driver private data
2634 * @pdev reference to struct pci_dev
2635 */
2636 static void gadget_release(struct device *pdev)
2637 {
2638 struct pch_udc_dev *dev = dev_get_drvdata(pdev);
2639
2640 kfree(dev);
2641 }
2642
2643 /**
2644 * pch_udc_pcd_reinit() - This API initializes the endpoint structures
2645 * @dev: Reference to the driver structure
2646 */
2647 static void pch_udc_pcd_reinit(struct pch_udc_dev *dev)
2648 {
2649 const char *const ep_string[] = {
2650 ep0_string, "ep0out", "ep1in", "ep1out", "ep2in", "ep2out",
2651 "ep3in", "ep3out", "ep4in", "ep4out", "ep5in", "ep5out",
2652 "ep6in", "ep6out", "ep7in", "ep7out", "ep8in", "ep8out",
2653 "ep9in", "ep9out", "ep10in", "ep10out", "ep11in", "ep11out",
2654 "ep12in", "ep12out", "ep13in", "ep13out", "ep14in", "ep14out",
2655 "ep15in", "ep15out",
2656 };
2657 int i;
2658
2659 dev->gadget.speed = USB_SPEED_UNKNOWN;
2660 INIT_LIST_HEAD(&dev->gadget.ep_list);
2661
2662 /* Initialize the endpoints structures */
2663 memset(dev->ep, 0, sizeof dev->ep);
2664 for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2665 struct pch_udc_ep *ep = &dev->ep[i];
2666 ep->dev = dev;
2667 ep->halted = 1;
2668 ep->num = i / 2;
2669 ep->in = ~i & 1;
2670 ep->ep.name = ep_string[i];
2671 ep->ep.ops = &pch_udc_ep_ops;
2672 if (ep->in)
2673 ep->offset_addr = ep->num * UDC_EP_REG_SHIFT;
2674 else
2675 ep->offset_addr = (UDC_EPINT_OUT_SHIFT + ep->num) *
2676 UDC_EP_REG_SHIFT;
2677 /* need to set ep->ep.maxpacket and set Default Configuration?*/
2678 ep->ep.maxpacket = UDC_BULK_MAX_PKT_SIZE;
2679 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
2680 INIT_LIST_HEAD(&ep->queue);
2681 }
2682 dev->ep[UDC_EP0IN_IDX].ep.maxpacket = UDC_EP0IN_MAX_PKT_SIZE;
2683 dev->ep[UDC_EP0OUT_IDX].ep.maxpacket = UDC_EP0OUT_MAX_PKT_SIZE;
2684
2685 /* remove ep0 in and out from the list. They have own pointer */
2686 list_del_init(&dev->ep[UDC_EP0IN_IDX].ep.ep_list);
2687 list_del_init(&dev->ep[UDC_EP0OUT_IDX].ep.ep_list);
2688
2689 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2690 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
2691 }
2692
2693 /**
2694 * pch_udc_pcd_init() - This API initializes the driver structure
2695 * @dev: Reference to the driver structure
2696 *
2697 * Return codes:
2698 * 0: Success
2699 */
2700 static int pch_udc_pcd_init(struct pch_udc_dev *dev)
2701 {
2702 pch_udc_init(dev);
2703 pch_udc_pcd_reinit(dev);
2704 return 0;
2705 }
2706
2707 /**
2708 * init_dma_pools() - create dma pools during initialization
2709 * @pdev: reference to struct pci_dev
2710 */
2711 static int init_dma_pools(struct pch_udc_dev *dev)
2712 {
2713 struct pch_udc_stp_dma_desc *td_stp;
2714 struct pch_udc_data_dma_desc *td_data;
2715
2716 /* DMA setup */
2717 dev->data_requests = pci_pool_create("data_requests", dev->pdev,
2718 sizeof(struct pch_udc_data_dma_desc), 0, 0);
2719 if (!dev->data_requests) {
2720 dev_err(&dev->pdev->dev, "%s: can't get request data pool\n",
2721 __func__);
2722 return -ENOMEM;
2723 }
2724
2725 /* dma desc for setup data */
2726 dev->stp_requests = pci_pool_create("setup requests", dev->pdev,
2727 sizeof(struct pch_udc_stp_dma_desc), 0, 0);
2728 if (!dev->stp_requests) {
2729 dev_err(&dev->pdev->dev, "%s: can't get setup request pool\n",
2730 __func__);
2731 return -ENOMEM;
2732 }
2733 /* setup */
2734 td_stp = pci_pool_alloc(dev->stp_requests, GFP_KERNEL,
2735 &dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
2736 if (!td_stp) {
2737 dev_err(&dev->pdev->dev,
2738 "%s: can't allocate setup dma descriptor\n", __func__);
2739 return -ENOMEM;
2740 }
2741 dev->ep[UDC_EP0OUT_IDX].td_stp = td_stp;
2742
2743 /* data: 0 packets !? */
2744 td_data = pci_pool_alloc(dev->data_requests, GFP_KERNEL,
2745 &dev->ep[UDC_EP0OUT_IDX].td_data_phys);
2746 if (!td_data) {
2747 dev_err(&dev->pdev->dev,
2748 "%s: can't allocate data dma descriptor\n", __func__);
2749 return -ENOMEM;
2750 }
2751 dev->ep[UDC_EP0OUT_IDX].td_data = td_data;
2752 dev->ep[UDC_EP0IN_IDX].td_stp = NULL;
2753 dev->ep[UDC_EP0IN_IDX].td_stp_phys = 0;
2754 dev->ep[UDC_EP0IN_IDX].td_data = NULL;
2755 dev->ep[UDC_EP0IN_IDX].td_data_phys = 0;
2756
2757 dev->ep0out_buf = kzalloc(UDC_EP0OUT_BUFF_SIZE * 4, GFP_KERNEL);
2758 if (!dev->ep0out_buf)
2759 return -ENOMEM;
2760 dev->dma_addr = dma_map_single(&dev->pdev->dev, dev->ep0out_buf,
2761 UDC_EP0OUT_BUFF_SIZE * 4,
2762 DMA_FROM_DEVICE);
2763 return 0;
2764 }
2765
2766 static int pch_udc_start(struct usb_gadget_driver *driver,
2767 int (*bind)(struct usb_gadget *))
2768 {
2769 struct pch_udc_dev *dev = pch_udc;
2770 int retval;
2771
2772 if (!driver || (driver->max_speed == USB_SPEED_UNKNOWN) || !bind ||
2773 !driver->setup || !driver->unbind || !driver->disconnect) {
2774 dev_err(&dev->pdev->dev,
2775 "%s: invalid driver parameter\n", __func__);
2776 return -EINVAL;
2777 }
2778
2779 if (!dev)
2780 return -ENODEV;
2781
2782 if (dev->driver) {
2783 dev_err(&dev->pdev->dev, "%s: already bound\n", __func__);
2784 return -EBUSY;
2785 }
2786 driver->driver.bus = NULL;
2787 dev->driver = driver;
2788 dev->gadget.dev.driver = &driver->driver;
2789
2790 /* Invoke the bind routine of the gadget driver */
2791 retval = bind(&dev->gadget);
2792
2793 if (retval) {
2794 dev_err(&dev->pdev->dev, "%s: binding to %s returning %d\n",
2795 __func__, driver->driver.name, retval);
2796 dev->driver = NULL;
2797 dev->gadget.dev.driver = NULL;
2798 return retval;
2799 }
2800 /* get ready for ep0 traffic */
2801 pch_udc_setup_ep0(dev);
2802
2803 /* clear SD */
2804 pch_udc_clear_disconnect(dev);
2805
2806 dev->connected = 1;
2807 return 0;
2808 }
2809
2810 static int pch_udc_stop(struct usb_gadget_driver *driver)
2811 {
2812 struct pch_udc_dev *dev = pch_udc;
2813
2814 if (!dev)
2815 return -ENODEV;
2816
2817 if (!driver || (driver != dev->driver)) {
2818 dev_err(&dev->pdev->dev,
2819 "%s: invalid driver parameter\n", __func__);
2820 return -EINVAL;
2821 }
2822
2823 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
2824
2825 /* Assures that there are no pending requests with this driver */
2826 driver->disconnect(&dev->gadget);
2827 driver->unbind(&dev->gadget);
2828 dev->gadget.dev.driver = NULL;
2829 dev->driver = NULL;
2830 dev->connected = 0;
2831
2832 /* set SD */
2833 pch_udc_set_disconnect(dev);
2834 return 0;
2835 }
2836
2837 static void pch_udc_shutdown(struct pci_dev *pdev)
2838 {
2839 struct pch_udc_dev *dev = pci_get_drvdata(pdev);
2840
2841 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
2842 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2843
2844 /* disable the pullup so the host will think we're gone */
2845 pch_udc_set_disconnect(dev);
2846 }
2847
2848 static void pch_udc_remove(struct pci_dev *pdev)
2849 {
2850 struct pch_udc_dev *dev = pci_get_drvdata(pdev);
2851
2852 usb_del_gadget_udc(&dev->gadget);
2853
2854 /* gadget driver must not be registered */
2855 if (dev->driver)
2856 dev_err(&pdev->dev,
2857 "%s: gadget driver still bound!!!\n", __func__);
2858 /* dma pool cleanup */
2859 if (dev->data_requests)
2860 pci_pool_destroy(dev->data_requests);
2861
2862 if (dev->stp_requests) {
2863 /* cleanup DMA desc's for ep0in */
2864 if (dev->ep[UDC_EP0OUT_IDX].td_stp) {
2865 pci_pool_free(dev->stp_requests,
2866 dev->ep[UDC_EP0OUT_IDX].td_stp,
2867 dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
2868 }
2869 if (dev->ep[UDC_EP0OUT_IDX].td_data) {
2870 pci_pool_free(dev->stp_requests,
2871 dev->ep[UDC_EP0OUT_IDX].td_data,
2872 dev->ep[UDC_EP0OUT_IDX].td_data_phys);
2873 }
2874 pci_pool_destroy(dev->stp_requests);
2875 }
2876
2877 if (dev->dma_addr)
2878 dma_unmap_single(&dev->pdev->dev, dev->dma_addr,
2879 UDC_EP0OUT_BUFF_SIZE * 4, DMA_FROM_DEVICE);
2880 kfree(dev->ep0out_buf);
2881
2882 pch_udc_exit(dev);
2883
2884 if (dev->irq_registered)
2885 free_irq(pdev->irq, dev);
2886 if (dev->base_addr)
2887 iounmap(dev->base_addr);
2888 if (dev->mem_region)
2889 release_mem_region(dev->phys_addr,
2890 pci_resource_len(pdev, PCH_UDC_PCI_BAR));
2891 if (dev->active)
2892 pci_disable_device(pdev);
2893 if (dev->registered)
2894 device_unregister(&dev->gadget.dev);
2895 kfree(dev);
2896 pci_set_drvdata(pdev, NULL);
2897 }
2898
2899 #ifdef CONFIG_PM
2900 static int pch_udc_suspend(struct pci_dev *pdev, pm_message_t state)
2901 {
2902 struct pch_udc_dev *dev = pci_get_drvdata(pdev);
2903
2904 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
2905 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2906
2907 pci_disable_device(pdev);
2908 pci_enable_wake(pdev, PCI_D3hot, 0);
2909
2910 if (pci_save_state(pdev)) {
2911 dev_err(&pdev->dev,
2912 "%s: could not save PCI config state\n", __func__);
2913 return -ENOMEM;
2914 }
2915 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2916 return 0;
2917 }
2918
2919 static int pch_udc_resume(struct pci_dev *pdev)
2920 {
2921 int ret;
2922
2923 pci_set_power_state(pdev, PCI_D0);
2924 pci_restore_state(pdev);
2925 ret = pci_enable_device(pdev);
2926 if (ret) {
2927 dev_err(&pdev->dev, "%s: pci_enable_device failed\n", __func__);
2928 return ret;
2929 }
2930 pci_enable_wake(pdev, PCI_D3hot, 0);
2931 return 0;
2932 }
2933 #else
2934 #define pch_udc_suspend NULL
2935 #define pch_udc_resume NULL
2936 #endif /* CONFIG_PM */
2937
2938 static int pch_udc_probe(struct pci_dev *pdev,
2939 const struct pci_device_id *id)
2940 {
2941 unsigned long resource;
2942 unsigned long len;
2943 int retval;
2944 struct pch_udc_dev *dev;
2945
2946 /* one udc only */
2947 if (pch_udc) {
2948 pr_err("%s: already probed\n", __func__);
2949 return -EBUSY;
2950 }
2951 /* init */
2952 dev = kzalloc(sizeof *dev, GFP_KERNEL);
2953 if (!dev) {
2954 pr_err("%s: no memory for device structure\n", __func__);
2955 return -ENOMEM;
2956 }
2957 /* pci setup */
2958 if (pci_enable_device(pdev) < 0) {
2959 kfree(dev);
2960 pr_err("%s: pci_enable_device failed\n", __func__);
2961 return -ENODEV;
2962 }
2963 dev->active = 1;
2964 pci_set_drvdata(pdev, dev);
2965
2966 /* PCI resource allocation */
2967 resource = pci_resource_start(pdev, 1);
2968 len = pci_resource_len(pdev, 1);
2969
2970 if (!request_mem_region(resource, len, KBUILD_MODNAME)) {
2971 dev_err(&pdev->dev, "%s: pci device used already\n", __func__);
2972 retval = -EBUSY;
2973 goto finished;
2974 }
2975 dev->phys_addr = resource;
2976 dev->mem_region = 1;
2977
2978 dev->base_addr = ioremap_nocache(resource, len);
2979 if (!dev->base_addr) {
2980 pr_err("%s: device memory cannot be mapped\n", __func__);
2981 retval = -ENOMEM;
2982 goto finished;
2983 }
2984 if (!pdev->irq) {
2985 dev_err(&pdev->dev, "%s: irq not set\n", __func__);
2986 retval = -ENODEV;
2987 goto finished;
2988 }
2989 pch_udc = dev;
2990 /* initialize the hardware */
2991 if (pch_udc_pcd_init(dev)) {
2992 retval = -ENODEV;
2993 goto finished;
2994 }
2995 if (request_irq(pdev->irq, pch_udc_isr, IRQF_SHARED, KBUILD_MODNAME,
2996 dev)) {
2997 dev_err(&pdev->dev, "%s: request_irq(%d) fail\n", __func__,
2998 pdev->irq);
2999 retval = -ENODEV;
3000 goto finished;
3001 }
3002 dev->irq = pdev->irq;
3003 dev->irq_registered = 1;
3004
3005 pci_set_master(pdev);
3006 pci_try_set_mwi(pdev);
3007
3008 /* device struct setup */
3009 spin_lock_init(&dev->lock);
3010 dev->pdev = pdev;
3011 dev->gadget.ops = &pch_udc_ops;
3012
3013 retval = init_dma_pools(dev);
3014 if (retval)
3015 goto finished;
3016
3017 dev_set_name(&dev->gadget.dev, "gadget");
3018 dev->gadget.dev.parent = &pdev->dev;
3019 dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
3020 dev->gadget.dev.release = gadget_release;
3021 dev->gadget.name = KBUILD_MODNAME;
3022 dev->gadget.max_speed = USB_SPEED_HIGH;
3023
3024 retval = device_register(&dev->gadget.dev);
3025 if (retval)
3026 goto finished;
3027 dev->registered = 1;
3028
3029 /* Put the device in disconnected state till a driver is bound */
3030 pch_udc_set_disconnect(dev);
3031 retval = usb_add_gadget_udc(&pdev->dev, &dev->gadget);
3032 if (retval)
3033 goto finished;
3034 return 0;
3035
3036 finished:
3037 pch_udc_remove(pdev);
3038 return retval;
3039 }
3040
3041 static DEFINE_PCI_DEVICE_TABLE(pch_udc_pcidev_id) = {
3042 {
3043 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EG20T_UDC),
3044 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3045 .class_mask = 0xffffffff,
3046 },
3047 {
3048 PCI_DEVICE(PCI_VENDOR_ID_ROHM, PCI_DEVICE_ID_ML7213_IOH_UDC),
3049 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3050 .class_mask = 0xffffffff,
3051 },
3052 {
3053 PCI_DEVICE(PCI_VENDOR_ID_ROHM, PCI_DEVICE_ID_ML7831_IOH_UDC),
3054 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3055 .class_mask = 0xffffffff,
3056 },
3057 { 0 },
3058 };
3059
3060 MODULE_DEVICE_TABLE(pci, pch_udc_pcidev_id);
3061
3062
3063 static struct pci_driver pch_udc_driver = {
3064 .name = KBUILD_MODNAME,
3065 .id_table = pch_udc_pcidev_id,
3066 .probe = pch_udc_probe,
3067 .remove = pch_udc_remove,
3068 .suspend = pch_udc_suspend,
3069 .resume = pch_udc_resume,
3070 .shutdown = pch_udc_shutdown,
3071 };
3072
3073 static int __init pch_udc_pci_init(void)
3074 {
3075 return pci_register_driver(&pch_udc_driver);
3076 }
3077 module_init(pch_udc_pci_init);
3078
3079 static void __exit pch_udc_pci_exit(void)
3080 {
3081 pci_unregister_driver(&pch_udc_driver);
3082 }
3083 module_exit(pch_udc_pci_exit);
3084
3085 MODULE_DESCRIPTION("Intel EG20T USB Device Controller");
3086 MODULE_AUTHOR("LAPIS Semiconductor, <tomoya-linux@dsn.lapis-semi.com>");
3087 MODULE_LICENSE("GPL");