Avoid beyond bounds copy while caching ACL
[zen-stable.git] / drivers / usb / gadget / s3c-hsudc.c
blob397d625d57ad54fcfcb85fe52387594b007dfd91
1 /* linux/drivers/usb/gadget/s3c-hsudc.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S3C24XX USB 2.0 High-speed USB controller gadget driver
8 * The S3C24XX USB 2.0 high-speed USB controller supports upto 9 endpoints.
9 * Each endpoint can be configured as either in or out endpoint. Endpoints
10 * can be configured for Bulk or Interrupt transfer mode.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/delay.h>
24 #include <linux/io.h>
25 #include <linux/slab.h>
26 #include <linux/clk.h>
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
29 #include <linux/usb/otg.h>
30 #include <linux/prefetch.h>
31 #include <linux/platform_data/s3c-hsudc.h>
32 #include <linux/regulator/consumer.h>
34 #include <mach/regs-s3c2443-clock.h>
36 #define S3C_HSUDC_REG(x) (x)
38 /* Non-Indexed Registers */
39 #define S3C_IR S3C_HSUDC_REG(0x00) /* Index Register */
40 #define S3C_EIR S3C_HSUDC_REG(0x04) /* EP Intr Status */
41 #define S3C_EIR_EP0 (1<<0)
42 #define S3C_EIER S3C_HSUDC_REG(0x08) /* EP Intr Enable */
43 #define S3C_FAR S3C_HSUDC_REG(0x0c) /* Gadget Address */
44 #define S3C_FNR S3C_HSUDC_REG(0x10) /* Frame Number */
45 #define S3C_EDR S3C_HSUDC_REG(0x14) /* EP Direction */
46 #define S3C_TR S3C_HSUDC_REG(0x18) /* Test Register */
47 #define S3C_SSR S3C_HSUDC_REG(0x1c) /* System Status */
48 #define S3C_SSR_DTZIEN_EN (0xff8f)
49 #define S3C_SSR_ERR (0xff80)
50 #define S3C_SSR_VBUSON (1 << 8)
51 #define S3C_SSR_HSP (1 << 4)
52 #define S3C_SSR_SDE (1 << 3)
53 #define S3C_SSR_RESUME (1 << 2)
54 #define S3C_SSR_SUSPEND (1 << 1)
55 #define S3C_SSR_RESET (1 << 0)
56 #define S3C_SCR S3C_HSUDC_REG(0x20) /* System Control */
57 #define S3C_SCR_DTZIEN_EN (1 << 14)
58 #define S3C_SCR_RRD_EN (1 << 5)
59 #define S3C_SCR_SUS_EN (1 << 1)
60 #define S3C_SCR_RST_EN (1 << 0)
61 #define S3C_EP0SR S3C_HSUDC_REG(0x24) /* EP0 Status */
62 #define S3C_EP0SR_EP0_LWO (1 << 6)
63 #define S3C_EP0SR_STALL (1 << 4)
64 #define S3C_EP0SR_TX_SUCCESS (1 << 1)
65 #define S3C_EP0SR_RX_SUCCESS (1 << 0)
66 #define S3C_EP0CR S3C_HSUDC_REG(0x28) /* EP0 Control */
67 #define S3C_BR(_x) S3C_HSUDC_REG(0x60 + (_x * 4))
69 /* Indexed Registers */
70 #define S3C_ESR S3C_HSUDC_REG(0x2c) /* EPn Status */
71 #define S3C_ESR_FLUSH (1 << 6)
72 #define S3C_ESR_STALL (1 << 5)
73 #define S3C_ESR_LWO (1 << 4)
74 #define S3C_ESR_PSIF_ONE (1 << 2)
75 #define S3C_ESR_PSIF_TWO (2 << 2)
76 #define S3C_ESR_TX_SUCCESS (1 << 1)
77 #define S3C_ESR_RX_SUCCESS (1 << 0)
78 #define S3C_ECR S3C_HSUDC_REG(0x30) /* EPn Control */
79 #define S3C_ECR_DUEN (1 << 7)
80 #define S3C_ECR_FLUSH (1 << 6)
81 #define S3C_ECR_STALL (1 << 1)
82 #define S3C_ECR_IEMS (1 << 0)
83 #define S3C_BRCR S3C_HSUDC_REG(0x34) /* Read Count */
84 #define S3C_BWCR S3C_HSUDC_REG(0x38) /* Write Count */
85 #define S3C_MPR S3C_HSUDC_REG(0x3c) /* Max Pkt Size */
87 #define WAIT_FOR_SETUP (0)
88 #define DATA_STATE_XMIT (1)
89 #define DATA_STATE_RECV (2)
91 static const char * const s3c_hsudc_supply_names[] = {
92 "vdda", /* analog phy supply, 3.3V */
93 "vddi", /* digital phy supply, 1.2V */
94 "vddosc", /* oscillator supply, 1.8V - 3.3V */
97 /**
98 * struct s3c_hsudc_ep - Endpoint representation used by driver.
99 * @ep: USB gadget layer representation of device endpoint.
100 * @name: Endpoint name (as required by ep autoconfiguration).
101 * @dev: Reference to the device controller to which this EP belongs.
102 * @desc: Endpoint descriptor obtained from the gadget driver.
103 * @queue: Transfer request queue for the endpoint.
104 * @stopped: Maintains state of endpoint, set if EP is halted.
105 * @bEndpointAddress: EP address (including direction bit).
106 * @fifo: Base address of EP FIFO.
108 struct s3c_hsudc_ep {
109 struct usb_ep ep;
110 char name[20];
111 struct s3c_hsudc *dev;
112 const struct usb_endpoint_descriptor *desc;
113 struct list_head queue;
114 u8 stopped;
115 u8 wedge;
116 u8 bEndpointAddress;
117 void __iomem *fifo;
121 * struct s3c_hsudc_req - Driver encapsulation of USB gadget transfer request.
122 * @req: Reference to USB gadget transfer request.
123 * @queue: Used for inserting this request to the endpoint request queue.
125 struct s3c_hsudc_req {
126 struct usb_request req;
127 struct list_head queue;
131 * struct s3c_hsudc - Driver's abstraction of the device controller.
132 * @gadget: Instance of usb_gadget which is referenced by gadget driver.
133 * @driver: Reference to currenty active gadget driver.
134 * @dev: The device reference used by probe function.
135 * @lock: Lock to synchronize the usage of Endpoints (EP's are indexed).
136 * @regs: Remapped base address of controller's register space.
137 * @mem_rsrc: Device memory resource used for remapping device register space.
138 * irq: IRQ number used by the controller.
139 * uclk: Reference to the controller clock.
140 * ep0state: Current state of EP0.
141 * ep: List of endpoints supported by the controller.
143 struct s3c_hsudc {
144 struct usb_gadget gadget;
145 struct usb_gadget_driver *driver;
146 struct device *dev;
147 struct s3c24xx_hsudc_platdata *pd;
148 struct otg_transceiver *transceiver;
149 struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsudc_supply_names)];
150 spinlock_t lock;
151 void __iomem *regs;
152 struct resource *mem_rsrc;
153 int irq;
154 struct clk *uclk;
155 int ep0state;
156 struct s3c_hsudc_ep ep[];
159 #define ep_maxpacket(_ep) ((_ep)->ep.maxpacket)
160 #define ep_is_in(_ep) ((_ep)->bEndpointAddress & USB_DIR_IN)
161 #define ep_index(_ep) ((_ep)->bEndpointAddress & \
162 USB_ENDPOINT_NUMBER_MASK)
164 static const char driver_name[] = "s3c-udc";
165 static const char ep0name[] = "ep0-control";
167 static inline struct s3c_hsudc_req *our_req(struct usb_request *req)
169 return container_of(req, struct s3c_hsudc_req, req);
172 static inline struct s3c_hsudc_ep *our_ep(struct usb_ep *ep)
174 return container_of(ep, struct s3c_hsudc_ep, ep);
177 static inline struct s3c_hsudc *to_hsudc(struct usb_gadget *gadget)
179 return container_of(gadget, struct s3c_hsudc, gadget);
182 static inline void set_index(struct s3c_hsudc *hsudc, int ep_addr)
184 ep_addr &= USB_ENDPOINT_NUMBER_MASK;
185 writel(ep_addr, hsudc->regs + S3C_IR);
188 static inline void __orr32(void __iomem *ptr, u32 val)
190 writel(readl(ptr) | val, ptr);
193 static void s3c_hsudc_init_phy(void)
195 u32 cfg;
197 cfg = readl(S3C2443_PWRCFG) | S3C2443_PWRCFG_USBPHY;
198 writel(cfg, S3C2443_PWRCFG);
200 cfg = readl(S3C2443_URSTCON);
201 cfg |= (S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
202 writel(cfg, S3C2443_URSTCON);
203 mdelay(1);
205 cfg = readl(S3C2443_URSTCON);
206 cfg &= ~(S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
207 writel(cfg, S3C2443_URSTCON);
209 cfg = readl(S3C2443_PHYCTRL);
210 cfg &= ~(S3C2443_PHYCTRL_CLKSEL | S3C2443_PHYCTRL_DSPORT);
211 cfg |= (S3C2443_PHYCTRL_EXTCLK | S3C2443_PHYCTRL_PLLSEL);
212 writel(cfg, S3C2443_PHYCTRL);
214 cfg = readl(S3C2443_PHYPWR);
215 cfg &= ~(S3C2443_PHYPWR_FSUSPEND | S3C2443_PHYPWR_PLL_PWRDN |
216 S3C2443_PHYPWR_XO_ON | S3C2443_PHYPWR_PLL_REFCLK |
217 S3C2443_PHYPWR_ANALOG_PD);
218 cfg |= S3C2443_PHYPWR_COMMON_ON;
219 writel(cfg, S3C2443_PHYPWR);
221 cfg = readl(S3C2443_UCLKCON);
222 cfg |= (S3C2443_UCLKCON_DETECT_VBUS | S3C2443_UCLKCON_FUNC_CLKEN |
223 S3C2443_UCLKCON_TCLKEN);
224 writel(cfg, S3C2443_UCLKCON);
227 static void s3c_hsudc_uninit_phy(void)
229 u32 cfg;
231 cfg = readl(S3C2443_PWRCFG) & ~S3C2443_PWRCFG_USBPHY;
232 writel(cfg, S3C2443_PWRCFG);
234 writel(S3C2443_PHYPWR_FSUSPEND, S3C2443_PHYPWR);
236 cfg = readl(S3C2443_UCLKCON) & ~S3C2443_UCLKCON_FUNC_CLKEN;
237 writel(cfg, S3C2443_UCLKCON);
241 * s3c_hsudc_complete_request - Complete a transfer request.
242 * @hsep: Endpoint to which the request belongs.
243 * @hsreq: Transfer request to be completed.
244 * @status: Transfer completion status for the transfer request.
246 static void s3c_hsudc_complete_request(struct s3c_hsudc_ep *hsep,
247 struct s3c_hsudc_req *hsreq, int status)
249 unsigned int stopped = hsep->stopped;
250 struct s3c_hsudc *hsudc = hsep->dev;
252 list_del_init(&hsreq->queue);
253 hsreq->req.status = status;
255 if (!ep_index(hsep)) {
256 hsudc->ep0state = WAIT_FOR_SETUP;
257 hsep->bEndpointAddress &= ~USB_DIR_IN;
260 hsep->stopped = 1;
261 spin_unlock(&hsudc->lock);
262 if (hsreq->req.complete != NULL)
263 hsreq->req.complete(&hsep->ep, &hsreq->req);
264 spin_lock(&hsudc->lock);
265 hsep->stopped = stopped;
269 * s3c_hsudc_nuke_ep - Terminate all requests queued for a endpoint.
270 * @hsep: Endpoint for which queued requests have to be terminated.
271 * @status: Transfer completion status for the transfer request.
273 static void s3c_hsudc_nuke_ep(struct s3c_hsudc_ep *hsep, int status)
275 struct s3c_hsudc_req *hsreq;
277 while (!list_empty(&hsep->queue)) {
278 hsreq = list_entry(hsep->queue.next,
279 struct s3c_hsudc_req, queue);
280 s3c_hsudc_complete_request(hsep, hsreq, status);
285 * s3c_hsudc_stop_activity - Stop activity on all endpoints.
286 * @hsudc: Device controller for which EP activity is to be stopped.
287 * @driver: Reference to the gadget driver which is currently active.
289 * All the endpoints are stopped and any pending transfer requests if any on
290 * the endpoint are terminated.
292 static void s3c_hsudc_stop_activity(struct s3c_hsudc *hsudc)
294 struct s3c_hsudc_ep *hsep;
295 int epnum;
297 hsudc->gadget.speed = USB_SPEED_UNKNOWN;
299 for (epnum = 0; epnum < hsudc->pd->epnum; epnum++) {
300 hsep = &hsudc->ep[epnum];
301 hsep->stopped = 1;
302 s3c_hsudc_nuke_ep(hsep, -ESHUTDOWN);
307 * s3c_hsudc_read_setup_pkt - Read the received setup packet from EP0 fifo.
308 * @hsudc: Device controller from which setup packet is to be read.
309 * @buf: The buffer into which the setup packet is read.
311 * The setup packet received in the EP0 fifo is read and stored into a
312 * given buffer address.
315 static void s3c_hsudc_read_setup_pkt(struct s3c_hsudc *hsudc, u16 *buf)
317 int count;
319 count = readl(hsudc->regs + S3C_BRCR);
320 while (count--)
321 *buf++ = (u16)readl(hsudc->regs + S3C_BR(0));
323 writel(S3C_EP0SR_RX_SUCCESS, hsudc->regs + S3C_EP0SR);
327 * s3c_hsudc_write_fifo - Write next chunk of transfer data to EP fifo.
328 * @hsep: Endpoint to which the data is to be written.
329 * @hsreq: Transfer request from which the next chunk of data is written.
331 * Write the next chunk of data from a transfer request to the endpoint FIFO.
332 * If the transfer request completes, 1 is returned, otherwise 0 is returned.
334 static int s3c_hsudc_write_fifo(struct s3c_hsudc_ep *hsep,
335 struct s3c_hsudc_req *hsreq)
337 u16 *buf;
338 u32 max = ep_maxpacket(hsep);
339 u32 count, length;
340 bool is_last;
341 void __iomem *fifo = hsep->fifo;
343 buf = hsreq->req.buf + hsreq->req.actual;
344 prefetch(buf);
346 length = hsreq->req.length - hsreq->req.actual;
347 length = min(length, max);
348 hsreq->req.actual += length;
350 writel(length, hsep->dev->regs + S3C_BWCR);
351 for (count = 0; count < length; count += 2)
352 writel(*buf++, fifo);
354 if (count != max) {
355 is_last = true;
356 } else {
357 if (hsreq->req.length != hsreq->req.actual || hsreq->req.zero)
358 is_last = false;
359 else
360 is_last = true;
363 if (is_last) {
364 s3c_hsudc_complete_request(hsep, hsreq, 0);
365 return 1;
368 return 0;
372 * s3c_hsudc_read_fifo - Read the next chunk of data from EP fifo.
373 * @hsep: Endpoint from which the data is to be read.
374 * @hsreq: Transfer request to which the next chunk of data read is written.
376 * Read the next chunk of data from the endpoint FIFO and a write it to the
377 * transfer request buffer. If the transfer request completes, 1 is returned,
378 * otherwise 0 is returned.
380 static int s3c_hsudc_read_fifo(struct s3c_hsudc_ep *hsep,
381 struct s3c_hsudc_req *hsreq)
383 struct s3c_hsudc *hsudc = hsep->dev;
384 u32 csr, offset;
385 u16 *buf, word;
386 u32 buflen, rcnt, rlen;
387 void __iomem *fifo = hsep->fifo;
388 u32 is_short = 0;
390 offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR;
391 csr = readl(hsudc->regs + offset);
392 if (!(csr & S3C_ESR_RX_SUCCESS))
393 return -EINVAL;
395 buf = hsreq->req.buf + hsreq->req.actual;
396 prefetchw(buf);
397 buflen = hsreq->req.length - hsreq->req.actual;
399 rcnt = readl(hsudc->regs + S3C_BRCR);
400 rlen = (csr & S3C_ESR_LWO) ? (rcnt * 2 - 1) : (rcnt * 2);
402 hsreq->req.actual += min(rlen, buflen);
403 is_short = (rlen < hsep->ep.maxpacket);
405 while (rcnt-- != 0) {
406 word = (u16)readl(fifo);
407 if (buflen) {
408 *buf++ = word;
409 buflen--;
410 } else {
411 hsreq->req.status = -EOVERFLOW;
415 writel(S3C_ESR_RX_SUCCESS, hsudc->regs + offset);
417 if (is_short || hsreq->req.actual == hsreq->req.length) {
418 s3c_hsudc_complete_request(hsep, hsreq, 0);
419 return 1;
422 return 0;
426 * s3c_hsudc_epin_intr - Handle in-endpoint interrupt.
427 * @hsudc - Device controller for which the interrupt is to be handled.
428 * @ep_idx - Endpoint number on which an interrupt is pending.
430 * Handles interrupt for a in-endpoint. The interrupts that are handled are
431 * stall and data transmit complete interrupt.
433 static void s3c_hsudc_epin_intr(struct s3c_hsudc *hsudc, u32 ep_idx)
435 struct s3c_hsudc_ep *hsep = &hsudc->ep[ep_idx];
436 struct s3c_hsudc_req *hsreq;
437 u32 csr;
439 csr = readl((u32)hsudc->regs + S3C_ESR);
440 if (csr & S3C_ESR_STALL) {
441 writel(S3C_ESR_STALL, hsudc->regs + S3C_ESR);
442 return;
445 if (csr & S3C_ESR_TX_SUCCESS) {
446 writel(S3C_ESR_TX_SUCCESS, hsudc->regs + S3C_ESR);
447 if (list_empty(&hsep->queue))
448 return;
450 hsreq = list_entry(hsep->queue.next,
451 struct s3c_hsudc_req, queue);
452 if ((s3c_hsudc_write_fifo(hsep, hsreq) == 0) &&
453 (csr & S3C_ESR_PSIF_TWO))
454 s3c_hsudc_write_fifo(hsep, hsreq);
459 * s3c_hsudc_epout_intr - Handle out-endpoint interrupt.
460 * @hsudc - Device controller for which the interrupt is to be handled.
461 * @ep_idx - Endpoint number on which an interrupt is pending.
463 * Handles interrupt for a out-endpoint. The interrupts that are handled are
464 * stall, flush and data ready interrupt.
466 static void s3c_hsudc_epout_intr(struct s3c_hsudc *hsudc, u32 ep_idx)
468 struct s3c_hsudc_ep *hsep = &hsudc->ep[ep_idx];
469 struct s3c_hsudc_req *hsreq;
470 u32 csr;
472 csr = readl((u32)hsudc->regs + S3C_ESR);
473 if (csr & S3C_ESR_STALL) {
474 writel(S3C_ESR_STALL, hsudc->regs + S3C_ESR);
475 return;
478 if (csr & S3C_ESR_FLUSH) {
479 __orr32(hsudc->regs + S3C_ECR, S3C_ECR_FLUSH);
480 return;
483 if (csr & S3C_ESR_RX_SUCCESS) {
484 if (list_empty(&hsep->queue))
485 return;
487 hsreq = list_entry(hsep->queue.next,
488 struct s3c_hsudc_req, queue);
489 if (((s3c_hsudc_read_fifo(hsep, hsreq)) == 0) &&
490 (csr & S3C_ESR_PSIF_TWO))
491 s3c_hsudc_read_fifo(hsep, hsreq);
495 /** s3c_hsudc_set_halt - Set or clear a endpoint halt.
496 * @_ep: Endpoint on which halt has to be set or cleared.
497 * @value: 1 for setting halt on endpoint, 0 to clear halt.
499 * Set or clear endpoint halt. If halt is set, the endpoint is stopped.
500 * If halt is cleared, for in-endpoints, if there are any pending
501 * transfer requests, transfers are started.
503 static int s3c_hsudc_set_halt(struct usb_ep *_ep, int value)
505 struct s3c_hsudc_ep *hsep = our_ep(_ep);
506 struct s3c_hsudc *hsudc = hsep->dev;
507 struct s3c_hsudc_req *hsreq;
508 unsigned long irqflags;
509 u32 ecr;
510 u32 offset;
512 if (value && ep_is_in(hsep) && !list_empty(&hsep->queue))
513 return -EAGAIN;
515 spin_lock_irqsave(&hsudc->lock, irqflags);
516 set_index(hsudc, ep_index(hsep));
517 offset = (ep_index(hsep)) ? S3C_ECR : S3C_EP0CR;
518 ecr = readl(hsudc->regs + offset);
520 if (value) {
521 ecr |= S3C_ECR_STALL;
522 if (ep_index(hsep))
523 ecr |= S3C_ECR_FLUSH;
524 hsep->stopped = 1;
525 } else {
526 ecr &= ~S3C_ECR_STALL;
527 hsep->stopped = hsep->wedge = 0;
529 writel(ecr, hsudc->regs + offset);
531 if (ep_is_in(hsep) && !list_empty(&hsep->queue) && !value) {
532 hsreq = list_entry(hsep->queue.next,
533 struct s3c_hsudc_req, queue);
534 if (hsreq)
535 s3c_hsudc_write_fifo(hsep, hsreq);
538 spin_unlock_irqrestore(&hsudc->lock, irqflags);
539 return 0;
542 /** s3c_hsudc_set_wedge - Sets the halt feature with the clear requests ignored
543 * @_ep: Endpoint on which wedge has to be set.
545 * Sets the halt feature with the clear requests ignored.
547 static int s3c_hsudc_set_wedge(struct usb_ep *_ep)
549 struct s3c_hsudc_ep *hsep = our_ep(_ep);
551 if (!hsep)
552 return -EINVAL;
554 hsep->wedge = 1;
555 return usb_ep_set_halt(_ep);
558 /** s3c_hsudc_handle_reqfeat - Handle set feature or clear feature requests.
559 * @_ep: Device controller on which the set/clear feature needs to be handled.
560 * @ctrl: Control request as received on the endpoint 0.
562 * Handle set feature or clear feature control requests on the control endpoint.
564 static int s3c_hsudc_handle_reqfeat(struct s3c_hsudc *hsudc,
565 struct usb_ctrlrequest *ctrl)
567 struct s3c_hsudc_ep *hsep;
568 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
569 u8 ep_num = ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK;
571 if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
572 hsep = &hsudc->ep[ep_num];
573 switch (le16_to_cpu(ctrl->wValue)) {
574 case USB_ENDPOINT_HALT:
575 if (set || (!set && !hsep->wedge))
576 s3c_hsudc_set_halt(&hsep->ep, set);
577 return 0;
581 return -ENOENT;
585 * s3c_hsudc_process_req_status - Handle get status control request.
586 * @hsudc: Device controller on which get status request has be handled.
587 * @ctrl: Control request as received on the endpoint 0.
589 * Handle get status control request received on control endpoint.
591 static void s3c_hsudc_process_req_status(struct s3c_hsudc *hsudc,
592 struct usb_ctrlrequest *ctrl)
594 struct s3c_hsudc_ep *hsep0 = &hsudc->ep[0];
595 struct s3c_hsudc_req hsreq;
596 struct s3c_hsudc_ep *hsep;
597 __le16 reply;
598 u8 epnum;
600 switch (ctrl->bRequestType & USB_RECIP_MASK) {
601 case USB_RECIP_DEVICE:
602 reply = cpu_to_le16(0);
603 break;
605 case USB_RECIP_INTERFACE:
606 reply = cpu_to_le16(0);
607 break;
609 case USB_RECIP_ENDPOINT:
610 epnum = le16_to_cpu(ctrl->wIndex) & USB_ENDPOINT_NUMBER_MASK;
611 hsep = &hsudc->ep[epnum];
612 reply = cpu_to_le16(hsep->stopped ? 1 : 0);
613 break;
616 INIT_LIST_HEAD(&hsreq.queue);
617 hsreq.req.length = 2;
618 hsreq.req.buf = &reply;
619 hsreq.req.actual = 0;
620 hsreq.req.complete = NULL;
621 s3c_hsudc_write_fifo(hsep0, &hsreq);
625 * s3c_hsudc_process_setup - Process control request received on endpoint 0.
626 * @hsudc: Device controller on which control request has been received.
628 * Read the control request received on endpoint 0, decode it and handle
629 * the request.
631 static void s3c_hsudc_process_setup(struct s3c_hsudc *hsudc)
633 struct s3c_hsudc_ep *hsep = &hsudc->ep[0];
634 struct usb_ctrlrequest ctrl = {0};
635 int ret;
637 s3c_hsudc_nuke_ep(hsep, -EPROTO);
638 s3c_hsudc_read_setup_pkt(hsudc, (u16 *)&ctrl);
640 if (ctrl.bRequestType & USB_DIR_IN) {
641 hsep->bEndpointAddress |= USB_DIR_IN;
642 hsudc->ep0state = DATA_STATE_XMIT;
643 } else {
644 hsep->bEndpointAddress &= ~USB_DIR_IN;
645 hsudc->ep0state = DATA_STATE_RECV;
648 switch (ctrl.bRequest) {
649 case USB_REQ_SET_ADDRESS:
650 if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
651 break;
652 hsudc->ep0state = WAIT_FOR_SETUP;
653 return;
655 case USB_REQ_GET_STATUS:
656 if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD)
657 break;
658 s3c_hsudc_process_req_status(hsudc, &ctrl);
659 return;
661 case USB_REQ_SET_FEATURE:
662 case USB_REQ_CLEAR_FEATURE:
663 if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD)
664 break;
665 s3c_hsudc_handle_reqfeat(hsudc, &ctrl);
666 hsudc->ep0state = WAIT_FOR_SETUP;
667 return;
670 if (hsudc->driver) {
671 spin_unlock(&hsudc->lock);
672 ret = hsudc->driver->setup(&hsudc->gadget, &ctrl);
673 spin_lock(&hsudc->lock);
675 if (ctrl.bRequest == USB_REQ_SET_CONFIGURATION) {
676 hsep->bEndpointAddress &= ~USB_DIR_IN;
677 hsudc->ep0state = WAIT_FOR_SETUP;
680 if (ret < 0) {
681 dev_err(hsudc->dev, "setup failed, returned %d\n",
682 ret);
683 s3c_hsudc_set_halt(&hsep->ep, 1);
684 hsudc->ep0state = WAIT_FOR_SETUP;
685 hsep->bEndpointAddress &= ~USB_DIR_IN;
690 /** s3c_hsudc_handle_ep0_intr - Handle endpoint 0 interrupt.
691 * @hsudc: Device controller on which endpoint 0 interrupt has occured.
693 * Handle endpoint 0 interrupt when it occurs. EP0 interrupt could occur
694 * when a stall handshake is sent to host or data is sent/received on
695 * endpoint 0.
697 static void s3c_hsudc_handle_ep0_intr(struct s3c_hsudc *hsudc)
699 struct s3c_hsudc_ep *hsep = &hsudc->ep[0];
700 struct s3c_hsudc_req *hsreq;
701 u32 csr = readl(hsudc->regs + S3C_EP0SR);
702 u32 ecr;
704 if (csr & S3C_EP0SR_STALL) {
705 ecr = readl(hsudc->regs + S3C_EP0CR);
706 ecr &= ~(S3C_ECR_STALL | S3C_ECR_FLUSH);
707 writel(ecr, hsudc->regs + S3C_EP0CR);
709 writel(S3C_EP0SR_STALL, hsudc->regs + S3C_EP0SR);
710 hsep->stopped = 0;
712 s3c_hsudc_nuke_ep(hsep, -ECONNABORTED);
713 hsudc->ep0state = WAIT_FOR_SETUP;
714 hsep->bEndpointAddress &= ~USB_DIR_IN;
715 return;
718 if (csr & S3C_EP0SR_TX_SUCCESS) {
719 writel(S3C_EP0SR_TX_SUCCESS, hsudc->regs + S3C_EP0SR);
720 if (ep_is_in(hsep)) {
721 if (list_empty(&hsep->queue))
722 return;
724 hsreq = list_entry(hsep->queue.next,
725 struct s3c_hsudc_req, queue);
726 s3c_hsudc_write_fifo(hsep, hsreq);
730 if (csr & S3C_EP0SR_RX_SUCCESS) {
731 if (hsudc->ep0state == WAIT_FOR_SETUP)
732 s3c_hsudc_process_setup(hsudc);
733 else {
734 if (!ep_is_in(hsep)) {
735 if (list_empty(&hsep->queue))
736 return;
737 hsreq = list_entry(hsep->queue.next,
738 struct s3c_hsudc_req, queue);
739 s3c_hsudc_read_fifo(hsep, hsreq);
746 * s3c_hsudc_ep_enable - Enable a endpoint.
747 * @_ep: The endpoint to be enabled.
748 * @desc: Endpoint descriptor.
750 * Enables a endpoint when called from the gadget driver. Endpoint stall if
751 * any is cleared, transfer type is configured and endpoint interrupt is
752 * enabled.
754 static int s3c_hsudc_ep_enable(struct usb_ep *_ep,
755 const struct usb_endpoint_descriptor *desc)
757 struct s3c_hsudc_ep *hsep;
758 struct s3c_hsudc *hsudc;
759 unsigned long flags;
760 u32 ecr = 0;
762 hsep = container_of(_ep, struct s3c_hsudc_ep, ep);
763 if (!_ep || !desc || hsep->desc || _ep->name == ep0name
764 || desc->bDescriptorType != USB_DT_ENDPOINT
765 || hsep->bEndpointAddress != desc->bEndpointAddress
766 || ep_maxpacket(hsep) < usb_endpoint_maxp(desc))
767 return -EINVAL;
769 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
770 && usb_endpoint_maxp(desc) != ep_maxpacket(hsep))
771 || !desc->wMaxPacketSize)
772 return -ERANGE;
774 hsudc = hsep->dev;
775 if (!hsudc->driver || hsudc->gadget.speed == USB_SPEED_UNKNOWN)
776 return -ESHUTDOWN;
778 spin_lock_irqsave(&hsudc->lock, flags);
780 set_index(hsudc, hsep->bEndpointAddress);
781 ecr |= ((usb_endpoint_xfer_int(desc)) ? S3C_ECR_IEMS : S3C_ECR_DUEN);
782 writel(ecr, hsudc->regs + S3C_ECR);
784 hsep->stopped = hsep->wedge = 0;
785 hsep->desc = desc;
786 hsep->ep.maxpacket = usb_endpoint_maxp(desc);
788 s3c_hsudc_set_halt(_ep, 0);
789 __set_bit(ep_index(hsep), hsudc->regs + S3C_EIER);
791 spin_unlock_irqrestore(&hsudc->lock, flags);
792 return 0;
796 * s3c_hsudc_ep_disable - Disable a endpoint.
797 * @_ep: The endpoint to be disabled.
798 * @desc: Endpoint descriptor.
800 * Disables a endpoint when called from the gadget driver.
802 static int s3c_hsudc_ep_disable(struct usb_ep *_ep)
804 struct s3c_hsudc_ep *hsep = our_ep(_ep);
805 struct s3c_hsudc *hsudc = hsep->dev;
806 unsigned long flags;
808 if (!_ep || !hsep->desc)
809 return -EINVAL;
811 spin_lock_irqsave(&hsudc->lock, flags);
813 set_index(hsudc, hsep->bEndpointAddress);
814 __clear_bit(ep_index(hsep), hsudc->regs + S3C_EIER);
816 s3c_hsudc_nuke_ep(hsep, -ESHUTDOWN);
818 hsep->desc = 0;
819 hsep->ep.desc = NULL;
820 hsep->stopped = 1;
822 spin_unlock_irqrestore(&hsudc->lock, flags);
823 return 0;
827 * s3c_hsudc_alloc_request - Allocate a new request.
828 * @_ep: Endpoint for which request is allocated (not used).
829 * @gfp_flags: Flags used for the allocation.
831 * Allocates a single transfer request structure when called from gadget driver.
833 static struct usb_request *s3c_hsudc_alloc_request(struct usb_ep *_ep,
834 gfp_t gfp_flags)
836 struct s3c_hsudc_req *hsreq;
838 hsreq = kzalloc(sizeof *hsreq, gfp_flags);
839 if (!hsreq)
840 return 0;
842 INIT_LIST_HEAD(&hsreq->queue);
843 return &hsreq->req;
847 * s3c_hsudc_free_request - Deallocate a request.
848 * @ep: Endpoint for which request is deallocated (not used).
849 * @_req: Request to be deallocated.
851 * Allocates a single transfer request structure when called from gadget driver.
853 static void s3c_hsudc_free_request(struct usb_ep *ep, struct usb_request *_req)
855 struct s3c_hsudc_req *hsreq;
857 hsreq = container_of(_req, struct s3c_hsudc_req, req);
858 WARN_ON(!list_empty(&hsreq->queue));
859 kfree(hsreq);
863 * s3c_hsudc_queue - Queue a transfer request for the endpoint.
864 * @_ep: Endpoint for which the request is queued.
865 * @_req: Request to be queued.
866 * @gfp_flags: Not used.
868 * Start or enqueue a request for a endpoint when called from gadget driver.
870 static int s3c_hsudc_queue(struct usb_ep *_ep, struct usb_request *_req,
871 gfp_t gfp_flags)
873 struct s3c_hsudc_req *hsreq;
874 struct s3c_hsudc_ep *hsep;
875 struct s3c_hsudc *hsudc;
876 unsigned long flags;
877 u32 offset;
878 u32 csr;
880 hsreq = container_of(_req, struct s3c_hsudc_req, req);
881 if ((!_req || !_req->complete || !_req->buf ||
882 !list_empty(&hsreq->queue)))
883 return -EINVAL;
885 hsep = container_of(_ep, struct s3c_hsudc_ep, ep);
886 hsudc = hsep->dev;
887 if (!hsudc->driver || hsudc->gadget.speed == USB_SPEED_UNKNOWN)
888 return -ESHUTDOWN;
890 spin_lock_irqsave(&hsudc->lock, flags);
891 set_index(hsudc, hsep->bEndpointAddress);
893 _req->status = -EINPROGRESS;
894 _req->actual = 0;
896 if (!ep_index(hsep) && _req->length == 0) {
897 hsudc->ep0state = WAIT_FOR_SETUP;
898 s3c_hsudc_complete_request(hsep, hsreq, 0);
899 spin_unlock_irqrestore(&hsudc->lock, flags);
900 return 0;
903 if (list_empty(&hsep->queue) && !hsep->stopped) {
904 offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR;
905 if (ep_is_in(hsep)) {
906 csr = readl((u32)hsudc->regs + offset);
907 if (!(csr & S3C_ESR_TX_SUCCESS) &&
908 (s3c_hsudc_write_fifo(hsep, hsreq) == 1))
909 hsreq = 0;
910 } else {
911 csr = readl((u32)hsudc->regs + offset);
912 if ((csr & S3C_ESR_RX_SUCCESS)
913 && (s3c_hsudc_read_fifo(hsep, hsreq) == 1))
914 hsreq = 0;
918 if (hsreq != 0)
919 list_add_tail(&hsreq->queue, &hsep->queue);
921 spin_unlock_irqrestore(&hsudc->lock, flags);
922 return 0;
926 * s3c_hsudc_dequeue - Dequeue a transfer request from an endpoint.
927 * @_ep: Endpoint from which the request is dequeued.
928 * @_req: Request to be dequeued.
930 * Dequeue a request from a endpoint when called from gadget driver.
932 static int s3c_hsudc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
934 struct s3c_hsudc_ep *hsep = our_ep(_ep);
935 struct s3c_hsudc *hsudc = hsep->dev;
936 struct s3c_hsudc_req *hsreq;
937 unsigned long flags;
939 hsep = container_of(_ep, struct s3c_hsudc_ep, ep);
940 if (!_ep || hsep->ep.name == ep0name)
941 return -EINVAL;
943 spin_lock_irqsave(&hsudc->lock, flags);
945 list_for_each_entry(hsreq, &hsep->queue, queue) {
946 if (&hsreq->req == _req)
947 break;
949 if (&hsreq->req != _req) {
950 spin_unlock_irqrestore(&hsudc->lock, flags);
951 return -EINVAL;
954 set_index(hsudc, hsep->bEndpointAddress);
955 s3c_hsudc_complete_request(hsep, hsreq, -ECONNRESET);
957 spin_unlock_irqrestore(&hsudc->lock, flags);
958 return 0;
961 static struct usb_ep_ops s3c_hsudc_ep_ops = {
962 .enable = s3c_hsudc_ep_enable,
963 .disable = s3c_hsudc_ep_disable,
964 .alloc_request = s3c_hsudc_alloc_request,
965 .free_request = s3c_hsudc_free_request,
966 .queue = s3c_hsudc_queue,
967 .dequeue = s3c_hsudc_dequeue,
968 .set_halt = s3c_hsudc_set_halt,
969 .set_wedge = s3c_hsudc_set_wedge,
973 * s3c_hsudc_initep - Initialize a endpoint to default state.
974 * @hsudc - Reference to the device controller.
975 * @hsep - Endpoint to be initialized.
976 * @epnum - Address to be assigned to the endpoint.
978 * Initialize a endpoint with default configuration.
980 static void s3c_hsudc_initep(struct s3c_hsudc *hsudc,
981 struct s3c_hsudc_ep *hsep, int epnum)
983 char *dir;
985 if ((epnum % 2) == 0) {
986 dir = "out";
987 } else {
988 dir = "in";
989 hsep->bEndpointAddress = USB_DIR_IN;
992 hsep->bEndpointAddress |= epnum;
993 if (epnum)
994 snprintf(hsep->name, sizeof(hsep->name), "ep%d%s", epnum, dir);
995 else
996 snprintf(hsep->name, sizeof(hsep->name), "%s", ep0name);
998 INIT_LIST_HEAD(&hsep->queue);
999 INIT_LIST_HEAD(&hsep->ep.ep_list);
1000 if (epnum)
1001 list_add_tail(&hsep->ep.ep_list, &hsudc->gadget.ep_list);
1003 hsep->dev = hsudc;
1004 hsep->ep.name = hsep->name;
1005 hsep->ep.maxpacket = epnum ? 512 : 64;
1006 hsep->ep.ops = &s3c_hsudc_ep_ops;
1007 hsep->fifo = hsudc->regs + S3C_BR(epnum);
1008 hsep->desc = 0;
1009 hsep->ep.desc = NULL;
1010 hsep->stopped = 0;
1011 hsep->wedge = 0;
1013 set_index(hsudc, epnum);
1014 writel(hsep->ep.maxpacket, hsudc->regs + S3C_MPR);
1018 * s3c_hsudc_setup_ep - Configure all endpoints to default state.
1019 * @hsudc: Reference to device controller.
1021 * Configures all endpoints to default state.
1023 static void s3c_hsudc_setup_ep(struct s3c_hsudc *hsudc)
1025 int epnum;
1027 hsudc->ep0state = WAIT_FOR_SETUP;
1028 INIT_LIST_HEAD(&hsudc->gadget.ep_list);
1029 for (epnum = 0; epnum < hsudc->pd->epnum; epnum++)
1030 s3c_hsudc_initep(hsudc, &hsudc->ep[epnum], epnum);
1034 * s3c_hsudc_reconfig - Reconfigure the device controller to default state.
1035 * @hsudc: Reference to device controller.
1037 * Reconfigures the device controller registers to a default state.
1039 static void s3c_hsudc_reconfig(struct s3c_hsudc *hsudc)
1041 writel(0xAA, hsudc->regs + S3C_EDR);
1042 writel(1, hsudc->regs + S3C_EIER);
1043 writel(0, hsudc->regs + S3C_TR);
1044 writel(S3C_SCR_DTZIEN_EN | S3C_SCR_RRD_EN | S3C_SCR_SUS_EN |
1045 S3C_SCR_RST_EN, hsudc->regs + S3C_SCR);
1046 writel(0, hsudc->regs + S3C_EP0CR);
1048 s3c_hsudc_setup_ep(hsudc);
1052 * s3c_hsudc_irq - Interrupt handler for device controller.
1053 * @irq: Not used.
1054 * @_dev: Reference to the device controller.
1056 * Interrupt handler for the device controller. This handler handles controller
1057 * interrupts and endpoint interrupts.
1059 static irqreturn_t s3c_hsudc_irq(int irq, void *_dev)
1061 struct s3c_hsudc *hsudc = _dev;
1062 struct s3c_hsudc_ep *hsep;
1063 u32 ep_intr;
1064 u32 sys_status;
1065 u32 ep_idx;
1067 spin_lock(&hsudc->lock);
1069 sys_status = readl(hsudc->regs + S3C_SSR);
1070 ep_intr = readl(hsudc->regs + S3C_EIR) & 0x3FF;
1072 if (!ep_intr && !(sys_status & S3C_SSR_DTZIEN_EN)) {
1073 spin_unlock(&hsudc->lock);
1074 return IRQ_HANDLED;
1077 if (sys_status) {
1078 if (sys_status & S3C_SSR_VBUSON)
1079 writel(S3C_SSR_VBUSON, hsudc->regs + S3C_SSR);
1081 if (sys_status & S3C_SSR_ERR)
1082 writel(S3C_SSR_ERR, hsudc->regs + S3C_SSR);
1084 if (sys_status & S3C_SSR_SDE) {
1085 writel(S3C_SSR_SDE, hsudc->regs + S3C_SSR);
1086 hsudc->gadget.speed = (sys_status & S3C_SSR_HSP) ?
1087 USB_SPEED_HIGH : USB_SPEED_FULL;
1090 if (sys_status & S3C_SSR_SUSPEND) {
1091 writel(S3C_SSR_SUSPEND, hsudc->regs + S3C_SSR);
1092 if (hsudc->gadget.speed != USB_SPEED_UNKNOWN
1093 && hsudc->driver && hsudc->driver->suspend)
1094 hsudc->driver->suspend(&hsudc->gadget);
1097 if (sys_status & S3C_SSR_RESUME) {
1098 writel(S3C_SSR_RESUME, hsudc->regs + S3C_SSR);
1099 if (hsudc->gadget.speed != USB_SPEED_UNKNOWN
1100 && hsudc->driver && hsudc->driver->resume)
1101 hsudc->driver->resume(&hsudc->gadget);
1104 if (sys_status & S3C_SSR_RESET) {
1105 writel(S3C_SSR_RESET, hsudc->regs + S3C_SSR);
1106 for (ep_idx = 0; ep_idx < hsudc->pd->epnum; ep_idx++) {
1107 hsep = &hsudc->ep[ep_idx];
1108 hsep->stopped = 1;
1109 s3c_hsudc_nuke_ep(hsep, -ECONNRESET);
1111 s3c_hsudc_reconfig(hsudc);
1112 hsudc->ep0state = WAIT_FOR_SETUP;
1116 if (ep_intr & S3C_EIR_EP0) {
1117 writel(S3C_EIR_EP0, hsudc->regs + S3C_EIR);
1118 set_index(hsudc, 0);
1119 s3c_hsudc_handle_ep0_intr(hsudc);
1122 ep_intr >>= 1;
1123 ep_idx = 1;
1124 while (ep_intr) {
1125 if (ep_intr & 1) {
1126 hsep = &hsudc->ep[ep_idx];
1127 set_index(hsudc, ep_idx);
1128 writel(1 << ep_idx, hsudc->regs + S3C_EIR);
1129 if (ep_is_in(hsep))
1130 s3c_hsudc_epin_intr(hsudc, ep_idx);
1131 else
1132 s3c_hsudc_epout_intr(hsudc, ep_idx);
1134 ep_intr >>= 1;
1135 ep_idx++;
1138 spin_unlock(&hsudc->lock);
1139 return IRQ_HANDLED;
1142 static int s3c_hsudc_start(struct usb_gadget *gadget,
1143 struct usb_gadget_driver *driver)
1145 struct s3c_hsudc *hsudc = to_hsudc(gadget);
1146 int ret;
1148 if (!driver
1149 || driver->max_speed < USB_SPEED_FULL
1150 || !driver->setup)
1151 return -EINVAL;
1153 if (!hsudc)
1154 return -ENODEV;
1156 if (hsudc->driver)
1157 return -EBUSY;
1159 hsudc->driver = driver;
1160 hsudc->gadget.dev.driver = &driver->driver;
1162 ret = regulator_bulk_enable(ARRAY_SIZE(hsudc->supplies),
1163 hsudc->supplies);
1164 if (ret != 0) {
1165 dev_err(hsudc->dev, "failed to enable supplies: %d\n", ret);
1166 goto err_supplies;
1169 /* connect to bus through transceiver */
1170 if (hsudc->transceiver) {
1171 ret = otg_set_peripheral(hsudc->transceiver, &hsudc->gadget);
1172 if (ret) {
1173 dev_err(hsudc->dev, "%s: can't bind to transceiver\n",
1174 hsudc->gadget.name);
1175 goto err_otg;
1179 enable_irq(hsudc->irq);
1180 dev_info(hsudc->dev, "bound driver %s\n", driver->driver.name);
1182 s3c_hsudc_reconfig(hsudc);
1183 s3c_hsudc_init_phy();
1184 if (hsudc->pd->gpio_init)
1185 hsudc->pd->gpio_init();
1187 return 0;
1188 err_otg:
1189 regulator_bulk_disable(ARRAY_SIZE(hsudc->supplies), hsudc->supplies);
1190 err_supplies:
1191 hsudc->driver = NULL;
1192 hsudc->gadget.dev.driver = NULL;
1193 return ret;
1196 static int s3c_hsudc_stop(struct usb_gadget *gadget,
1197 struct usb_gadget_driver *driver)
1199 struct s3c_hsudc *hsudc = to_hsudc(gadget);
1200 unsigned long flags;
1202 if (!hsudc)
1203 return -ENODEV;
1205 if (!driver || driver != hsudc->driver)
1206 return -EINVAL;
1208 spin_lock_irqsave(&hsudc->lock, flags);
1209 hsudc->driver = NULL;
1210 hsudc->gadget.dev.driver = NULL;
1211 hsudc->gadget.speed = USB_SPEED_UNKNOWN;
1212 s3c_hsudc_uninit_phy();
1213 if (hsudc->pd->gpio_uninit)
1214 hsudc->pd->gpio_uninit();
1215 s3c_hsudc_stop_activity(hsudc);
1216 spin_unlock_irqrestore(&hsudc->lock, flags);
1218 if (hsudc->transceiver)
1219 (void) otg_set_peripheral(hsudc->transceiver, NULL);
1221 disable_irq(hsudc->irq);
1223 regulator_bulk_disable(ARRAY_SIZE(hsudc->supplies), hsudc->supplies);
1225 dev_info(hsudc->dev, "unregistered gadget driver '%s'\n",
1226 driver->driver.name);
1227 return 0;
1230 static inline u32 s3c_hsudc_read_frameno(struct s3c_hsudc *hsudc)
1232 return readl(hsudc->regs + S3C_FNR) & 0x3FF;
1235 static int s3c_hsudc_gadget_getframe(struct usb_gadget *gadget)
1237 return s3c_hsudc_read_frameno(to_hsudc(gadget));
1240 static int s3c_hsudc_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1242 struct s3c_hsudc *hsudc = to_hsudc(gadget);
1244 if (!hsudc)
1245 return -ENODEV;
1247 if (hsudc->transceiver)
1248 return otg_set_power(hsudc->transceiver, mA);
1250 return -EOPNOTSUPP;
1253 static struct usb_gadget_ops s3c_hsudc_gadget_ops = {
1254 .get_frame = s3c_hsudc_gadget_getframe,
1255 .udc_start = s3c_hsudc_start,
1256 .udc_stop = s3c_hsudc_stop,
1257 .vbus_draw = s3c_hsudc_vbus_draw,
1260 static int __devinit s3c_hsudc_probe(struct platform_device *pdev)
1262 struct device *dev = &pdev->dev;
1263 struct resource *res;
1264 struct s3c_hsudc *hsudc;
1265 struct s3c24xx_hsudc_platdata *pd = pdev->dev.platform_data;
1266 int ret, i;
1268 hsudc = kzalloc(sizeof(struct s3c_hsudc) +
1269 sizeof(struct s3c_hsudc_ep) * pd->epnum,
1270 GFP_KERNEL);
1271 if (!hsudc) {
1272 dev_err(dev, "cannot allocate memory\n");
1273 return -ENOMEM;
1276 platform_set_drvdata(pdev, dev);
1277 hsudc->dev = dev;
1278 hsudc->pd = pdev->dev.platform_data;
1280 hsudc->transceiver = otg_get_transceiver();
1282 for (i = 0; i < ARRAY_SIZE(hsudc->supplies); i++)
1283 hsudc->supplies[i].supply = s3c_hsudc_supply_names[i];
1285 ret = regulator_bulk_get(dev, ARRAY_SIZE(hsudc->supplies),
1286 hsudc->supplies);
1287 if (ret != 0) {
1288 dev_err(dev, "failed to request supplies: %d\n", ret);
1289 goto err_supplies;
1292 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1293 if (!res) {
1294 dev_err(dev, "unable to obtain driver resource data\n");
1295 ret = -ENODEV;
1296 goto err_res;
1299 hsudc->mem_rsrc = request_mem_region(res->start, resource_size(res),
1300 dev_name(&pdev->dev));
1301 if (!hsudc->mem_rsrc) {
1302 dev_err(dev, "failed to reserve register area\n");
1303 ret = -ENODEV;
1304 goto err_res;
1307 hsudc->regs = ioremap(res->start, resource_size(res));
1308 if (!hsudc->regs) {
1309 dev_err(dev, "error mapping device register area\n");
1310 ret = -EBUSY;
1311 goto err_remap;
1314 spin_lock_init(&hsudc->lock);
1316 dev_set_name(&hsudc->gadget.dev, "gadget");
1318 hsudc->gadget.max_speed = USB_SPEED_HIGH;
1319 hsudc->gadget.ops = &s3c_hsudc_gadget_ops;
1320 hsudc->gadget.name = dev_name(dev);
1321 hsudc->gadget.dev.parent = dev;
1322 hsudc->gadget.dev.dma_mask = dev->dma_mask;
1323 hsudc->gadget.ep0 = &hsudc->ep[0].ep;
1325 hsudc->gadget.is_otg = 0;
1326 hsudc->gadget.is_a_peripheral = 0;
1327 hsudc->gadget.speed = USB_SPEED_UNKNOWN;
1329 s3c_hsudc_setup_ep(hsudc);
1331 ret = platform_get_irq(pdev, 0);
1332 if (ret < 0) {
1333 dev_err(dev, "unable to obtain IRQ number\n");
1334 goto err_irq;
1336 hsudc->irq = ret;
1338 ret = request_irq(hsudc->irq, s3c_hsudc_irq, 0, driver_name, hsudc);
1339 if (ret < 0) {
1340 dev_err(dev, "irq request failed\n");
1341 goto err_irq;
1344 hsudc->uclk = clk_get(&pdev->dev, "usb-device");
1345 if (IS_ERR(hsudc->uclk)) {
1346 dev_err(dev, "failed to find usb-device clock source\n");
1347 ret = PTR_ERR(hsudc->uclk);
1348 goto err_clk;
1350 clk_enable(hsudc->uclk);
1352 local_irq_disable();
1354 disable_irq(hsudc->irq);
1355 local_irq_enable();
1357 ret = device_register(&hsudc->gadget.dev);
1358 if (ret) {
1359 put_device(&hsudc->gadget.dev);
1360 goto err_add_device;
1363 ret = usb_add_gadget_udc(&pdev->dev, &hsudc->gadget);
1364 if (ret)
1365 goto err_add_udc;
1367 return 0;
1368 err_add_udc:
1369 device_unregister(&hsudc->gadget.dev);
1370 err_add_device:
1371 clk_disable(hsudc->uclk);
1372 clk_put(hsudc->uclk);
1373 err_clk:
1374 free_irq(hsudc->irq, hsudc);
1375 err_irq:
1376 iounmap(hsudc->regs);
1378 err_remap:
1379 release_mem_region(res->start, resource_size(res));
1380 err_res:
1381 if (hsudc->transceiver)
1382 otg_put_transceiver(hsudc->transceiver);
1384 regulator_bulk_free(ARRAY_SIZE(hsudc->supplies), hsudc->supplies);
1385 err_supplies:
1386 kfree(hsudc);
1387 return ret;
1390 static struct platform_driver s3c_hsudc_driver = {
1391 .driver = {
1392 .owner = THIS_MODULE,
1393 .name = "s3c-hsudc",
1395 .probe = s3c_hsudc_probe,
1398 module_platform_driver(s3c_hsudc_driver);
1400 MODULE_DESCRIPTION("Samsung S3C24XX USB high-speed controller driver");
1401 MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
1402 MODULE_LICENSE("GPL");
1403 MODULE_ALIAS("platform:s3c-hsudc");