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Avoid beyond bounds copy while caching ACL
[zen-stable.git] / drivers / video / omap2 / dss / dispc.c
blobe1626a1d5c451ffe0d3b829326ddf462423f5274
1 /*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #define DSS_SUBSYS_NAME "DISPC"
24
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/export.h>
29 #include <linux/clk.h>
30 #include <linux/io.h>
31 #include <linux/jiffies.h>
32 #include <linux/seq_file.h>
33 #include <linux/delay.h>
34 #include <linux/workqueue.h>
35 #include <linux/hardirq.h>
36 #include <linux/interrupt.h>
37 #include <linux/platform_device.h>
38 #include <linux/pm_runtime.h>
39
40 #include <plat/sram.h>
41 #include <plat/clock.h>
42
43 #include <video/omapdss.h>
44
45 #include "dss.h"
46 #include "dss_features.h"
47 #include "dispc.h"
48
49 /* DISPC */
50 #define DISPC_SZ_REGS SZ_4K
51
52 #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
53 DISPC_IRQ_OCP_ERR | \
54 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
55 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
56 DISPC_IRQ_SYNC_LOST | \
57 DISPC_IRQ_SYNC_LOST_DIGIT)
58
59 #define DISPC_MAX_NR_ISRS 8
60
61 struct omap_dispc_isr_data {
62 omap_dispc_isr_t isr;
63 void *arg;
64 u32 mask;
65 };
66
67 enum omap_burst_size {
68 BURST_SIZE_X2 = 0,
69 BURST_SIZE_X4 = 1,
70 BURST_SIZE_X8 = 2,
71 };
72
73 #define REG_GET(idx, start, end) \
74 FLD_GET(dispc_read_reg(idx), start, end)
75
76 #define REG_FLD_MOD(idx, val, start, end) \
77 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
78
79 struct dispc_irq_stats {
80 unsigned long last_reset;
81 unsigned irq_count;
82 unsigned irqs[32];
83 };
84
85 static struct {
86 struct platform_device *pdev;
87 void __iomem *base;
88
89 int ctx_loss_cnt;
90
91 int irq;
92 struct clk *dss_clk;
93
94 u32 fifo_size[MAX_DSS_OVERLAYS];
95
96 spinlock_t irq_lock;
97 u32 irq_error_mask;
98 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
99 u32 error_irqs;
100 struct work_struct error_work;
101
102 bool ctx_valid;
103 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
104
105 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
106 spinlock_t irq_stats_lock;
107 struct dispc_irq_stats irq_stats;
108 #endif
109 } dispc;
110
111 enum omap_color_component {
112 /* used for all color formats for OMAP3 and earlier
113 * and for RGB and Y color component on OMAP4
114 */
115 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
116 /* used for UV component for
117 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
118 * color formats on OMAP4
119 */
120 DISPC_COLOR_COMPONENT_UV = 1 << 1,
121 };
122
123 static void _omap_dispc_set_irqs(void);
124
125 static inline void dispc_write_reg(const u16 idx, u32 val)
126 {
127 __raw_writel(val, dispc.base + idx);
128 }
129
130 static inline u32 dispc_read_reg(const u16 idx)
131 {
132 return __raw_readl(dispc.base + idx);
133 }
134
135 static int dispc_get_ctx_loss_count(void)
136 {
137 struct device *dev = &dispc.pdev->dev;
138 struct omap_display_platform_data *pdata = dev->platform_data;
139 struct omap_dss_board_info *board_data = pdata->board_data;
140 int cnt;
141
142 if (!board_data->get_context_loss_count)
143 return -ENOENT;
144
145 cnt = board_data->get_context_loss_count(dev);
146
147 WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt);
148
149 return cnt;
150 }
151
152 #define SR(reg) \
153 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
154 #define RR(reg) \
155 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
156
157 static void dispc_save_context(void)
158 {
159 int i, j;
160
161 DSSDBG("dispc_save_context\n");
162
163 SR(IRQENABLE);
164 SR(CONTROL);
165 SR(CONFIG);
166 SR(LINE_NUMBER);
167 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
168 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
169 SR(GLOBAL_ALPHA);
170 if (dss_has_feature(FEAT_MGR_LCD2)) {
171 SR(CONTROL2);
172 SR(CONFIG2);
173 }
174
175 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
176 SR(DEFAULT_COLOR(i));
177 SR(TRANS_COLOR(i));
178 SR(SIZE_MGR(i));
179 if (i == OMAP_DSS_CHANNEL_DIGIT)
180 continue;
181 SR(TIMING_H(i));
182 SR(TIMING_V(i));
183 SR(POL_FREQ(i));
184 SR(DIVISORo(i));
185
186 SR(DATA_CYCLE1(i));
187 SR(DATA_CYCLE2(i));
188 SR(DATA_CYCLE3(i));
189
190 if (dss_has_feature(FEAT_CPR)) {
191 SR(CPR_COEF_R(i));
192 SR(CPR_COEF_G(i));
193 SR(CPR_COEF_B(i));
194 }
195 }
196
197 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
198 SR(OVL_BA0(i));
199 SR(OVL_BA1(i));
200 SR(OVL_POSITION(i));
201 SR(OVL_SIZE(i));
202 SR(OVL_ATTRIBUTES(i));
203 SR(OVL_FIFO_THRESHOLD(i));
204 SR(OVL_ROW_INC(i));
205 SR(OVL_PIXEL_INC(i));
206 if (dss_has_feature(FEAT_PRELOAD))
207 SR(OVL_PRELOAD(i));
208 if (i == OMAP_DSS_GFX) {
209 SR(OVL_WINDOW_SKIP(i));
210 SR(OVL_TABLE_BA(i));
211 continue;
212 }
213 SR(OVL_FIR(i));
214 SR(OVL_PICTURE_SIZE(i));
215 SR(OVL_ACCU0(i));
216 SR(OVL_ACCU1(i));
217
218 for (j = 0; j < 8; j++)
219 SR(OVL_FIR_COEF_H(i, j));
220
221 for (j = 0; j < 8; j++)
222 SR(OVL_FIR_COEF_HV(i, j));
223
224 for (j = 0; j < 5; j++)
225 SR(OVL_CONV_COEF(i, j));
226
227 if (dss_has_feature(FEAT_FIR_COEF_V)) {
228 for (j = 0; j < 8; j++)
229 SR(OVL_FIR_COEF_V(i, j));
230 }
231
232 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
233 SR(OVL_BA0_UV(i));
234 SR(OVL_BA1_UV(i));
235 SR(OVL_FIR2(i));
236 SR(OVL_ACCU2_0(i));
237 SR(OVL_ACCU2_1(i));
238
239 for (j = 0; j < 8; j++)
240 SR(OVL_FIR_COEF_H2(i, j));
241
242 for (j = 0; j < 8; j++)
243 SR(OVL_FIR_COEF_HV2(i, j));
244
245 for (j = 0; j < 8; j++)
246 SR(OVL_FIR_COEF_V2(i, j));
247 }
248 if (dss_has_feature(FEAT_ATTR2))
249 SR(OVL_ATTRIBUTES2(i));
250 }
251
252 if (dss_has_feature(FEAT_CORE_CLK_DIV))
253 SR(DIVISOR);
254
255 dispc.ctx_loss_cnt = dispc_get_ctx_loss_count();
256 dispc.ctx_valid = true;
257
258 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
259 }
260
261 static void dispc_restore_context(void)
262 {
263 int i, j, ctx;
264
265 DSSDBG("dispc_restore_context\n");
266
267 if (!dispc.ctx_valid)
268 return;
269
270 ctx = dispc_get_ctx_loss_count();
271
272 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
273 return;
274
275 DSSDBG("ctx_loss_count: saved %d, current %d\n",
276 dispc.ctx_loss_cnt, ctx);
277
278 /*RR(IRQENABLE);*/
279 /*RR(CONTROL);*/
280 RR(CONFIG);
281 RR(LINE_NUMBER);
282 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
283 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
284 RR(GLOBAL_ALPHA);
285 if (dss_has_feature(FEAT_MGR_LCD2))
286 RR(CONFIG2);
287
288 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
289 RR(DEFAULT_COLOR(i));
290 RR(TRANS_COLOR(i));
291 RR(SIZE_MGR(i));
292 if (i == OMAP_DSS_CHANNEL_DIGIT)
293 continue;
294 RR(TIMING_H(i));
295 RR(TIMING_V(i));
296 RR(POL_FREQ(i));
297 RR(DIVISORo(i));
298
299 RR(DATA_CYCLE1(i));
300 RR(DATA_CYCLE2(i));
301 RR(DATA_CYCLE3(i));
302
303 if (dss_has_feature(FEAT_CPR)) {
304 RR(CPR_COEF_R(i));
305 RR(CPR_COEF_G(i));
306 RR(CPR_COEF_B(i));
307 }
308 }
309
310 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
311 RR(OVL_BA0(i));
312 RR(OVL_BA1(i));
313 RR(OVL_POSITION(i));
314 RR(OVL_SIZE(i));
315 RR(OVL_ATTRIBUTES(i));
316 RR(OVL_FIFO_THRESHOLD(i));
317 RR(OVL_ROW_INC(i));
318 RR(OVL_PIXEL_INC(i));
319 if (dss_has_feature(FEAT_PRELOAD))
320 RR(OVL_PRELOAD(i));
321 if (i == OMAP_DSS_GFX) {
322 RR(OVL_WINDOW_SKIP(i));
323 RR(OVL_TABLE_BA(i));
324 continue;
325 }
326 RR(OVL_FIR(i));
327 RR(OVL_PICTURE_SIZE(i));
328 RR(OVL_ACCU0(i));
329 RR(OVL_ACCU1(i));
330
331 for (j = 0; j < 8; j++)
332 RR(OVL_FIR_COEF_H(i, j));
333
334 for (j = 0; j < 8; j++)
335 RR(OVL_FIR_COEF_HV(i, j));
336
337 for (j = 0; j < 5; j++)
338 RR(OVL_CONV_COEF(i, j));
339
340 if (dss_has_feature(FEAT_FIR_COEF_V)) {
341 for (j = 0; j < 8; j++)
342 RR(OVL_FIR_COEF_V(i, j));
343 }
344
345 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
346 RR(OVL_BA0_UV(i));
347 RR(OVL_BA1_UV(i));
348 RR(OVL_FIR2(i));
349 RR(OVL_ACCU2_0(i));
350 RR(OVL_ACCU2_1(i));
351
352 for (j = 0; j < 8; j++)
353 RR(OVL_FIR_COEF_H2(i, j));
354
355 for (j = 0; j < 8; j++)
356 RR(OVL_FIR_COEF_HV2(i, j));
357
358 for (j = 0; j < 8; j++)
359 RR(OVL_FIR_COEF_V2(i, j));
360 }
361 if (dss_has_feature(FEAT_ATTR2))
362 RR(OVL_ATTRIBUTES2(i));
363 }
364
365 if (dss_has_feature(FEAT_CORE_CLK_DIV))
366 RR(DIVISOR);
367
368 /* enable last, because LCD & DIGIT enable are here */
369 RR(CONTROL);
370 if (dss_has_feature(FEAT_MGR_LCD2))
371 RR(CONTROL2);
372 /* clear spurious SYNC_LOST_DIGIT interrupts */
373 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
374
375 /*
376 * enable last so IRQs won't trigger before
377 * the context is fully restored
378 */
379 RR(IRQENABLE);
380
381 DSSDBG("context restored\n");
382 }
383
384 #undef SR
385 #undef RR
386
387 int dispc_runtime_get(void)
388 {
389 int r;
390
391 DSSDBG("dispc_runtime_get\n");
392
393 r = pm_runtime_get_sync(&dispc.pdev->dev);
394 WARN_ON(r < 0);
395 return r < 0 ? r : 0;
396 }
397
398 void dispc_runtime_put(void)
399 {
400 int r;
401
402 DSSDBG("dispc_runtime_put\n");
403
404 r = pm_runtime_put_sync(&dispc.pdev->dev);
405 WARN_ON(r < 0);
406 }
407
408 static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
409 {
410 if (channel == OMAP_DSS_CHANNEL_LCD ||
411 channel == OMAP_DSS_CHANNEL_LCD2)
412 return true;
413 else
414 return false;
415 }
416
417 static struct omap_dss_device *dispc_mgr_get_device(enum omap_channel channel)
418 {
419 struct omap_overlay_manager *mgr =
420 omap_dss_get_overlay_manager(channel);
421
422 return mgr ? mgr->device : NULL;
423 }
424
425 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
426 {
427 switch (channel) {
428 case OMAP_DSS_CHANNEL_LCD:
429 return DISPC_IRQ_VSYNC;
430 case OMAP_DSS_CHANNEL_LCD2:
431 return DISPC_IRQ_VSYNC2;
432 case OMAP_DSS_CHANNEL_DIGIT:
433 return DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN;
434 default:
435 BUG();
436 }
437 }
438
439 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
440 {
441 switch (channel) {
442 case OMAP_DSS_CHANNEL_LCD:
443 return DISPC_IRQ_FRAMEDONE;
444 case OMAP_DSS_CHANNEL_LCD2:
445 return DISPC_IRQ_FRAMEDONE2;
446 case OMAP_DSS_CHANNEL_DIGIT:
447 return 0;
448 default:
449 BUG();
450 }
451 }
452
453 bool dispc_mgr_go_busy(enum omap_channel channel)
454 {
455 int bit;
456
457 if (dispc_mgr_is_lcd(channel))
458 bit = 5; /* GOLCD */
459 else
460 bit = 6; /* GODIGIT */
461
462 if (channel == OMAP_DSS_CHANNEL_LCD2)
463 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
464 else
465 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
466 }
467
468 void dispc_mgr_go(enum omap_channel channel)
469 {
470 int bit;
471 bool enable_bit, go_bit;
472
473 if (dispc_mgr_is_lcd(channel))
474 bit = 0; /* LCDENABLE */
475 else
476 bit = 1; /* DIGITALENABLE */
477
478 /* if the channel is not enabled, we don't need GO */
479 if (channel == OMAP_DSS_CHANNEL_LCD2)
480 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
481 else
482 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
483
484 if (!enable_bit)
485 return;
486
487 if (dispc_mgr_is_lcd(channel))
488 bit = 5; /* GOLCD */
489 else
490 bit = 6; /* GODIGIT */
491
492 if (channel == OMAP_DSS_CHANNEL_LCD2)
493 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
494 else
495 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
496
497 if (go_bit) {
498 DSSERR("GO bit not down for channel %d\n", channel);
499 return;
500 }
501
502 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
503 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
504
505 if (channel == OMAP_DSS_CHANNEL_LCD2)
506 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
507 else
508 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
509 }
510
511 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
512 {
513 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
514 }
515
516 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
517 {
518 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
519 }
520
521 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
522 {
523 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
524 }
525
526 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
527 {
528 BUG_ON(plane == OMAP_DSS_GFX);
529
530 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
531 }
532
533 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
534 u32 value)
535 {
536 BUG_ON(plane == OMAP_DSS_GFX);
537
538 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
539 }
540
541 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
542 {
543 BUG_ON(plane == OMAP_DSS_GFX);
544
545 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
546 }
547
548 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
549 int fir_vinc, int five_taps,
550 enum omap_color_component color_comp)
551 {
552 const struct dispc_coef *h_coef, *v_coef;
553 int i;
554
555 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
556 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
557
558 for (i = 0; i < 8; i++) {
559 u32 h, hv;
560
561 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
562 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
563 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
564 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
565 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
566 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
567 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
568 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
569
570 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
571 dispc_ovl_write_firh_reg(plane, i, h);
572 dispc_ovl_write_firhv_reg(plane, i, hv);
573 } else {
574 dispc_ovl_write_firh2_reg(plane, i, h);
575 dispc_ovl_write_firhv2_reg(plane, i, hv);
576 }
577
578 }
579
580 if (five_taps) {
581 for (i = 0; i < 8; i++) {
582 u32 v;
583 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
584 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
585 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
586 dispc_ovl_write_firv_reg(plane, i, v);
587 else
588 dispc_ovl_write_firv2_reg(plane, i, v);
589 }
590 }
591 }
592
593 static void _dispc_setup_color_conv_coef(void)
594 {
595 int i;
596 const struct color_conv_coef {
597 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
598 int full_range;
599 } ctbl_bt601_5 = {
600 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
601 };
602
603 const struct color_conv_coef *ct;
604
605 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
606
607 ct = &ctbl_bt601_5;
608
609 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
610 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
611 CVAL(ct->rcr, ct->ry));
612 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
613 CVAL(ct->gy, ct->rcb));
614 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
615 CVAL(ct->gcb, ct->gcr));
616 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
617 CVAL(ct->bcr, ct->by));
618 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
619 CVAL(0, ct->bcb));
620
621 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
622 11, 11);
623 }
624
625 #undef CVAL
626 }
627
628
629 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
630 {
631 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
632 }
633
634 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
635 {
636 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
637 }
638
639 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
640 {
641 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
642 }
643
644 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
645 {
646 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
647 }
648
649 static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
650 {
651 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
652
653 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
654 }
655
656 static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
657 {
658 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
659
660 if (plane == OMAP_DSS_GFX)
661 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
662 else
663 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
664 }
665
666 static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
667 {
668 u32 val;
669
670 BUG_ON(plane == OMAP_DSS_GFX);
671
672 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
673
674 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
675 }
676
677 static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder)
678 {
679 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
680
681 if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
682 return;
683
684 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
685 }
686
687 static void dispc_ovl_enable_zorder_planes(void)
688 {
689 int i;
690
691 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
692 return;
693
694 for (i = 0; i < dss_feat_get_num_ovls(); i++)
695 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
696 }
697
698 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
699 {
700 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
701
702 if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
703 return;
704
705 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
706 }
707
708 static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
709 {
710 static const unsigned shifts[] = { 0, 8, 16, 24, };
711 int shift;
712 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
713
714 if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
715 return;
716
717 shift = shifts[plane];
718 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
719 }
720
721 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
722 {
723 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
724 }
725
726 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
727 {
728 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
729 }
730
731 static void dispc_ovl_set_color_mode(enum omap_plane plane,
732 enum omap_color_mode color_mode)
733 {
734 u32 m = 0;
735 if (plane != OMAP_DSS_GFX) {
736 switch (color_mode) {
737 case OMAP_DSS_COLOR_NV12:
738 m = 0x0; break;
739 case OMAP_DSS_COLOR_RGB12U:
740 m = 0x1; break;
741 case OMAP_DSS_COLOR_RGBA16:
742 m = 0x2; break;
743 case OMAP_DSS_COLOR_RGBX16:
744 m = 0x4; break;
745 case OMAP_DSS_COLOR_ARGB16:
746 m = 0x5; break;
747 case OMAP_DSS_COLOR_RGB16:
748 m = 0x6; break;
749 case OMAP_DSS_COLOR_ARGB16_1555:
750 m = 0x7; break;
751 case OMAP_DSS_COLOR_RGB24U:
752 m = 0x8; break;
753 case OMAP_DSS_COLOR_RGB24P:
754 m = 0x9; break;
755 case OMAP_DSS_COLOR_YUV2:
756 m = 0xa; break;
757 case OMAP_DSS_COLOR_UYVY:
758 m = 0xb; break;
759 case OMAP_DSS_COLOR_ARGB32:
760 m = 0xc; break;
761 case OMAP_DSS_COLOR_RGBA32:
762 m = 0xd; break;
763 case OMAP_DSS_COLOR_RGBX32:
764 m = 0xe; break;
765 case OMAP_DSS_COLOR_XRGB16_1555:
766 m = 0xf; break;
767 default:
768 BUG(); break;
769 }
770 } else {
771 switch (color_mode) {
772 case OMAP_DSS_COLOR_CLUT1:
773 m = 0x0; break;
774 case OMAP_DSS_COLOR_CLUT2:
775 m = 0x1; break;
776 case OMAP_DSS_COLOR_CLUT4:
777 m = 0x2; break;
778 case OMAP_DSS_COLOR_CLUT8:
779 m = 0x3; break;
780 case OMAP_DSS_COLOR_RGB12U:
781 m = 0x4; break;
782 case OMAP_DSS_COLOR_ARGB16:
783 m = 0x5; break;
784 case OMAP_DSS_COLOR_RGB16:
785 m = 0x6; break;
786 case OMAP_DSS_COLOR_ARGB16_1555:
787 m = 0x7; break;
788 case OMAP_DSS_COLOR_RGB24U:
789 m = 0x8; break;
790 case OMAP_DSS_COLOR_RGB24P:
791 m = 0x9; break;
792 case OMAP_DSS_COLOR_YUV2:
793 m = 0xa; break;
794 case OMAP_DSS_COLOR_UYVY:
795 m = 0xb; break;
796 case OMAP_DSS_COLOR_ARGB32:
797 m = 0xc; break;
798 case OMAP_DSS_COLOR_RGBA32:
799 m = 0xd; break;
800 case OMAP_DSS_COLOR_RGBX32:
801 m = 0xe; break;
802 case OMAP_DSS_COLOR_XRGB16_1555:
803 m = 0xf; break;
804 default:
805 BUG(); break;
806 }
807 }
808
809 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
810 }
811
812 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
813 {
814 int shift;
815 u32 val;
816 int chan = 0, chan2 = 0;
817
818 switch (plane) {
819 case OMAP_DSS_GFX:
820 shift = 8;
821 break;
822 case OMAP_DSS_VIDEO1:
823 case OMAP_DSS_VIDEO2:
824 case OMAP_DSS_VIDEO3:
825 shift = 16;
826 break;
827 default:
828 BUG();
829 return;
830 }
831
832 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
833 if (dss_has_feature(FEAT_MGR_LCD2)) {
834 switch (channel) {
835 case OMAP_DSS_CHANNEL_LCD:
836 chan = 0;
837 chan2 = 0;
838 break;
839 case OMAP_DSS_CHANNEL_DIGIT:
840 chan = 1;
841 chan2 = 0;
842 break;
843 case OMAP_DSS_CHANNEL_LCD2:
844 chan = 0;
845 chan2 = 1;
846 break;
847 default:
848 BUG();
849 }
850
851 val = FLD_MOD(val, chan, shift, shift);
852 val = FLD_MOD(val, chan2, 31, 30);
853 } else {
854 val = FLD_MOD(val, channel, shift, shift);
855 }
856 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
857 }
858
859 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
860 {
861 int shift;
862 u32 val;
863 enum omap_channel channel;
864
865 switch (plane) {
866 case OMAP_DSS_GFX:
867 shift = 8;
868 break;
869 case OMAP_DSS_VIDEO1:
870 case OMAP_DSS_VIDEO2:
871 case OMAP_DSS_VIDEO3:
872 shift = 16;
873 break;
874 default:
875 BUG();
876 }
877
878 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
879
880 if (dss_has_feature(FEAT_MGR_LCD2)) {
881 if (FLD_GET(val, 31, 30) == 0)
882 channel = FLD_GET(val, shift, shift);
883 else
884 channel = OMAP_DSS_CHANNEL_LCD2;
885 } else {
886 channel = FLD_GET(val, shift, shift);
887 }
888
889 return channel;
890 }
891
892 static void dispc_ovl_set_burst_size(enum omap_plane plane,
893 enum omap_burst_size burst_size)
894 {
895 static const unsigned shifts[] = { 6, 14, 14, 14, };
896 int shift;
897
898 shift = shifts[plane];
899 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
900 }
901
902 static void dispc_configure_burst_sizes(void)
903 {
904 int i;
905 const int burst_size = BURST_SIZE_X8;
906
907 /* Configure burst size always to maximum size */
908 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
909 dispc_ovl_set_burst_size(i, burst_size);
910 }
911
912 u32 dispc_ovl_get_burst_size(enum omap_plane plane)
913 {
914 unsigned unit = dss_feat_get_burst_size_unit();
915 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
916 return unit * 8;
917 }
918
919 void dispc_enable_gamma_table(bool enable)
920 {
921 /*
922 * This is partially implemented to support only disabling of
923 * the gamma table.
924 */
925 if (enable) {
926 DSSWARN("Gamma table enabling for TV not yet supported");
927 return;
928 }
929
930 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
931 }
932
933 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
934 {
935 u16 reg;
936
937 if (channel == OMAP_DSS_CHANNEL_LCD)
938 reg = DISPC_CONFIG;
939 else if (channel == OMAP_DSS_CHANNEL_LCD2)
940 reg = DISPC_CONFIG2;
941 else
942 return;
943
944 REG_FLD_MOD(reg, enable, 15, 15);
945 }
946
947 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
948 struct omap_dss_cpr_coefs *coefs)
949 {
950 u32 coef_r, coef_g, coef_b;
951
952 if (!dispc_mgr_is_lcd(channel))
953 return;
954
955 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
956 FLD_VAL(coefs->rb, 9, 0);
957 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
958 FLD_VAL(coefs->gb, 9, 0);
959 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
960 FLD_VAL(coefs->bb, 9, 0);
961
962 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
963 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
964 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
965 }
966
967 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
968 {
969 u32 val;
970
971 BUG_ON(plane == OMAP_DSS_GFX);
972
973 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
974 val = FLD_MOD(val, enable, 9, 9);
975 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
976 }
977
978 static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
979 {
980 static const unsigned shifts[] = { 5, 10, 10, 10 };
981 int shift;
982
983 shift = shifts[plane];
984 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
985 }
986
987 void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
988 {
989 u32 val;
990 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
991 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
992 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
993 }
994
995 void dispc_set_digit_size(u16 width, u16 height)
996 {
997 u32 val;
998 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
999 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1000 dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
1001 }
1002
1003 static void dispc_read_plane_fifo_sizes(void)
1004 {
1005 u32 size;
1006 int plane;
1007 u8 start, end;
1008 u32 unit;
1009
1010 unit = dss_feat_get_buffer_size_unit();
1011
1012 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1013
1014 for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
1015 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1016 size *= unit;
1017 dispc.fifo_size[plane] = size;
1018 }
1019 }
1020
1021 u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1022 {
1023 return dispc.fifo_size[plane];
1024 }
1025
1026 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1027 {
1028 u8 hi_start, hi_end, lo_start, lo_end;
1029 u32 unit;
1030
1031 unit = dss_feat_get_buffer_size_unit();
1032
1033 WARN_ON(low % unit != 0);
1034 WARN_ON(high % unit != 0);
1035
1036 low /= unit;
1037 high /= unit;
1038
1039 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1040 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1041
1042 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1043 plane,
1044 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1045 lo_start, lo_end),
1046 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1047 hi_start, hi_end),
1048 low, high);
1049
1050 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1051 FLD_VAL(high, hi_start, hi_end) |
1052 FLD_VAL(low, lo_start, lo_end));
1053 }
1054
1055 void dispc_enable_fifomerge(bool enable)
1056 {
1057 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1058 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1059 }
1060
1061 static void dispc_ovl_set_fir(enum omap_plane plane,
1062 int hinc, int vinc,
1063 enum omap_color_component color_comp)
1064 {
1065 u32 val;
1066
1067 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1068 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1069
1070 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1071 &hinc_start, &hinc_end);
1072 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1073 &vinc_start, &vinc_end);
1074 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1075 FLD_VAL(hinc, hinc_start, hinc_end);
1076
1077 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1078 } else {
1079 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1080 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1081 }
1082 }
1083
1084 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1085 {
1086 u32 val;
1087 u8 hor_start, hor_end, vert_start, vert_end;
1088
1089 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1090 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1091
1092 val = FLD_VAL(vaccu, vert_start, vert_end) |
1093 FLD_VAL(haccu, hor_start, hor_end);
1094
1095 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1096 }
1097
1098 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1099 {
1100 u32 val;
1101 u8 hor_start, hor_end, vert_start, vert_end;
1102
1103 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1104 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1105
1106 val = FLD_VAL(vaccu, vert_start, vert_end) |
1107 FLD_VAL(haccu, hor_start, hor_end);
1108
1109 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1110 }
1111
1112 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1113 int vaccu)
1114 {
1115 u32 val;
1116
1117 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1118 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1119 }
1120
1121 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1122 int vaccu)
1123 {
1124 u32 val;
1125
1126 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1127 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1128 }
1129
1130 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1131 u16 orig_width, u16 orig_height,
1132 u16 out_width, u16 out_height,
1133 bool five_taps, u8 rotation,
1134 enum omap_color_component color_comp)
1135 {
1136 int fir_hinc, fir_vinc;
1137
1138 fir_hinc = 1024 * orig_width / out_width;
1139 fir_vinc = 1024 * orig_height / out_height;
1140
1141 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1142 color_comp);
1143 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1144 }
1145
1146 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1147 u16 orig_width, u16 orig_height,
1148 u16 out_width, u16 out_height,
1149 bool ilace, bool five_taps,
1150 bool fieldmode, enum omap_color_mode color_mode,
1151 u8 rotation)
1152 {
1153 int accu0 = 0;
1154 int accu1 = 0;
1155 u32 l;
1156
1157 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1158 out_width, out_height, five_taps,
1159 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1160 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1161
1162 /* RESIZEENABLE and VERTICALTAPS */
1163 l &= ~((0x3 << 5) | (0x1 << 21));
1164 l |= (orig_width != out_width) ? (1 << 5) : 0;
1165 l |= (orig_height != out_height) ? (1 << 6) : 0;
1166 l |= five_taps ? (1 << 21) : 0;
1167
1168 /* VRESIZECONF and HRESIZECONF */
1169 if (dss_has_feature(FEAT_RESIZECONF)) {
1170 l &= ~(0x3 << 7);
1171 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1172 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1173 }
1174
1175 /* LINEBUFFERSPLIT */
1176 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1177 l &= ~(0x1 << 22);
1178 l |= five_taps ? (1 << 22) : 0;
1179 }
1180
1181 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1182
1183 /*
1184 * field 0 = even field = bottom field
1185 * field 1 = odd field = top field
1186 */
1187 if (ilace && !fieldmode) {
1188 accu1 = 0;
1189 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1190 if (accu0 >= 1024/2) {
1191 accu1 = 1024/2;
1192 accu0 -= accu1;
1193 }
1194 }
1195
1196 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1197 dispc_ovl_set_vid_accu1(plane, 0, accu1);
1198 }
1199
1200 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1201 u16 orig_width, u16 orig_height,
1202 u16 out_width, u16 out_height,
1203 bool ilace, bool five_taps,
1204 bool fieldmode, enum omap_color_mode color_mode,
1205 u8 rotation)
1206 {
1207 int scale_x = out_width != orig_width;
1208 int scale_y = out_height != orig_height;
1209
1210 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1211 return;
1212 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1213 color_mode != OMAP_DSS_COLOR_UYVY &&
1214 color_mode != OMAP_DSS_COLOR_NV12)) {
1215 /* reset chroma resampling for RGB formats */
1216 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1217 return;
1218 }
1219 switch (color_mode) {
1220 case OMAP_DSS_COLOR_NV12:
1221 /* UV is subsampled by 2 vertically*/
1222 orig_height >>= 1;
1223 /* UV is subsampled by 2 horz.*/
1224 orig_width >>= 1;
1225 break;
1226 case OMAP_DSS_COLOR_YUV2:
1227 case OMAP_DSS_COLOR_UYVY:
1228 /*For YUV422 with 90/270 rotation,
1229 *we don't upsample chroma
1230 */
1231 if (rotation == OMAP_DSS_ROT_0 ||
1232 rotation == OMAP_DSS_ROT_180)
1233 /* UV is subsampled by 2 hrz*/
1234 orig_width >>= 1;
1235 /* must use FIR for YUV422 if rotated */
1236 if (rotation != OMAP_DSS_ROT_0)
1237 scale_x = scale_y = true;
1238 break;
1239 default:
1240 BUG();
1241 }
1242
1243 if (out_width != orig_width)
1244 scale_x = true;
1245 if (out_height != orig_height)
1246 scale_y = true;
1247
1248 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1249 out_width, out_height, five_taps,
1250 rotation, DISPC_COLOR_COMPONENT_UV);
1251
1252 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1253 (scale_x || scale_y) ? 1 : 0, 8, 8);
1254 /* set H scaling */
1255 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1256 /* set V scaling */
1257 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1258
1259 dispc_ovl_set_vid_accu2_0(plane, 0x80, 0);
1260 dispc_ovl_set_vid_accu2_1(plane, 0x80, 0);
1261 }
1262
1263 static void dispc_ovl_set_scaling(enum omap_plane plane,
1264 u16 orig_width, u16 orig_height,
1265 u16 out_width, u16 out_height,
1266 bool ilace, bool five_taps,
1267 bool fieldmode, enum omap_color_mode color_mode,
1268 u8 rotation)
1269 {
1270 BUG_ON(plane == OMAP_DSS_GFX);
1271
1272 dispc_ovl_set_scaling_common(plane,
1273 orig_width, orig_height,
1274 out_width, out_height,
1275 ilace, five_taps,
1276 fieldmode, color_mode,
1277 rotation);
1278
1279 dispc_ovl_set_scaling_uv(plane,
1280 orig_width, orig_height,
1281 out_width, out_height,
1282 ilace, five_taps,
1283 fieldmode, color_mode,
1284 rotation);
1285 }
1286
1287 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1288 bool mirroring, enum omap_color_mode color_mode)
1289 {
1290 bool row_repeat = false;
1291 int vidrot = 0;
1292
1293 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1294 color_mode == OMAP_DSS_COLOR_UYVY) {
1295
1296 if (mirroring) {
1297 switch (rotation) {
1298 case OMAP_DSS_ROT_0:
1299 vidrot = 2;
1300 break;
1301 case OMAP_DSS_ROT_90:
1302 vidrot = 1;
1303 break;
1304 case OMAP_DSS_ROT_180:
1305 vidrot = 0;
1306 break;
1307 case OMAP_DSS_ROT_270:
1308 vidrot = 3;
1309 break;
1310 }
1311 } else {
1312 switch (rotation) {
1313 case OMAP_DSS_ROT_0:
1314 vidrot = 0;
1315 break;
1316 case OMAP_DSS_ROT_90:
1317 vidrot = 1;
1318 break;
1319 case OMAP_DSS_ROT_180:
1320 vidrot = 2;
1321 break;
1322 case OMAP_DSS_ROT_270:
1323 vidrot = 3;
1324 break;
1325 }
1326 }
1327
1328 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1329 row_repeat = true;
1330 else
1331 row_repeat = false;
1332 }
1333
1334 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1335 if (dss_has_feature(FEAT_ROWREPEATENABLE))
1336 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1337 row_repeat ? 1 : 0, 18, 18);
1338 }
1339
1340 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1341 {
1342 switch (color_mode) {
1343 case OMAP_DSS_COLOR_CLUT1:
1344 return 1;
1345 case OMAP_DSS_COLOR_CLUT2:
1346 return 2;
1347 case OMAP_DSS_COLOR_CLUT4:
1348 return 4;
1349 case OMAP_DSS_COLOR_CLUT8:
1350 case OMAP_DSS_COLOR_NV12:
1351 return 8;
1352 case OMAP_DSS_COLOR_RGB12U:
1353 case OMAP_DSS_COLOR_RGB16:
1354 case OMAP_DSS_COLOR_ARGB16:
1355 case OMAP_DSS_COLOR_YUV2:
1356 case OMAP_DSS_COLOR_UYVY:
1357 case OMAP_DSS_COLOR_RGBA16:
1358 case OMAP_DSS_COLOR_RGBX16:
1359 case OMAP_DSS_COLOR_ARGB16_1555:
1360 case OMAP_DSS_COLOR_XRGB16_1555:
1361 return 16;
1362 case OMAP_DSS_COLOR_RGB24P:
1363 return 24;
1364 case OMAP_DSS_COLOR_RGB24U:
1365 case OMAP_DSS_COLOR_ARGB32:
1366 case OMAP_DSS_COLOR_RGBA32:
1367 case OMAP_DSS_COLOR_RGBX32:
1368 return 32;
1369 default:
1370 BUG();
1371 }
1372 }
1373
1374 static s32 pixinc(int pixels, u8 ps)
1375 {
1376 if (pixels == 1)
1377 return 1;
1378 else if (pixels > 1)
1379 return 1 + (pixels - 1) * ps;
1380 else if (pixels < 0)
1381 return 1 - (-pixels + 1) * ps;
1382 else
1383 BUG();
1384 }
1385
1386 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1387 u16 screen_width,
1388 u16 width, u16 height,
1389 enum omap_color_mode color_mode, bool fieldmode,
1390 unsigned int field_offset,
1391 unsigned *offset0, unsigned *offset1,
1392 s32 *row_inc, s32 *pix_inc)
1393 {
1394 u8 ps;
1395
1396 /* FIXME CLUT formats */
1397 switch (color_mode) {
1398 case OMAP_DSS_COLOR_CLUT1:
1399 case OMAP_DSS_COLOR_CLUT2:
1400 case OMAP_DSS_COLOR_CLUT4:
1401 case OMAP_DSS_COLOR_CLUT8:
1402 BUG();
1403 return;
1404 case OMAP_DSS_COLOR_YUV2:
1405 case OMAP_DSS_COLOR_UYVY:
1406 ps = 4;
1407 break;
1408 default:
1409 ps = color_mode_to_bpp(color_mode) / 8;
1410 break;
1411 }
1412
1413 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1414 width, height);
1415
1416 /*
1417 * field 0 = even field = bottom field
1418 * field 1 = odd field = top field
1419 */
1420 switch (rotation + mirror * 4) {
1421 case OMAP_DSS_ROT_0:
1422 case OMAP_DSS_ROT_180:
1423 /*
1424 * If the pixel format is YUV or UYVY divide the width
1425 * of the image by 2 for 0 and 180 degree rotation.
1426 */
1427 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1428 color_mode == OMAP_DSS_COLOR_UYVY)
1429 width = width >> 1;
1430 case OMAP_DSS_ROT_90:
1431 case OMAP_DSS_ROT_270:
1432 *offset1 = 0;
1433 if (field_offset)
1434 *offset0 = field_offset * screen_width * ps;
1435 else
1436 *offset0 = 0;
1437
1438 *row_inc = pixinc(1 + (screen_width - width) +
1439 (fieldmode ? screen_width : 0),
1440 ps);
1441 *pix_inc = pixinc(1, ps);
1442 break;
1443
1444 case OMAP_DSS_ROT_0 + 4:
1445 case OMAP_DSS_ROT_180 + 4:
1446 /* If the pixel format is YUV or UYVY divide the width
1447 * of the image by 2 for 0 degree and 180 degree
1448 */
1449 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1450 color_mode == OMAP_DSS_COLOR_UYVY)
1451 width = width >> 1;
1452 case OMAP_DSS_ROT_90 + 4:
1453 case OMAP_DSS_ROT_270 + 4:
1454 *offset1 = 0;
1455 if (field_offset)
1456 *offset0 = field_offset * screen_width * ps;
1457 else
1458 *offset0 = 0;
1459 *row_inc = pixinc(1 - (screen_width + width) -
1460 (fieldmode ? screen_width : 0),
1461 ps);
1462 *pix_inc = pixinc(1, ps);
1463 break;
1464
1465 default:
1466 BUG();
1467 }
1468 }
1469
1470 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1471 u16 screen_width,
1472 u16 width, u16 height,
1473 enum omap_color_mode color_mode, bool fieldmode,
1474 unsigned int field_offset,
1475 unsigned *offset0, unsigned *offset1,
1476 s32 *row_inc, s32 *pix_inc)
1477 {
1478 u8 ps;
1479 u16 fbw, fbh;
1480
1481 /* FIXME CLUT formats */
1482 switch (color_mode) {
1483 case OMAP_DSS_COLOR_CLUT1:
1484 case OMAP_DSS_COLOR_CLUT2:
1485 case OMAP_DSS_COLOR_CLUT4:
1486 case OMAP_DSS_COLOR_CLUT8:
1487 BUG();
1488 return;
1489 default:
1490 ps = color_mode_to_bpp(color_mode) / 8;
1491 break;
1492 }
1493
1494 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1495 width, height);
1496
1497 /* width & height are overlay sizes, convert to fb sizes */
1498
1499 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1500 fbw = width;
1501 fbh = height;
1502 } else {
1503 fbw = height;
1504 fbh = width;
1505 }
1506
1507 /*
1508 * field 0 = even field = bottom field
1509 * field 1 = odd field = top field
1510 */
1511 switch (rotation + mirror * 4) {
1512 case OMAP_DSS_ROT_0:
1513 *offset1 = 0;
1514 if (field_offset)
1515 *offset0 = *offset1 + field_offset * screen_width * ps;
1516 else
1517 *offset0 = *offset1;
1518 *row_inc = pixinc(1 + (screen_width - fbw) +
1519 (fieldmode ? screen_width : 0),
1520 ps);
1521 *pix_inc = pixinc(1, ps);
1522 break;
1523 case OMAP_DSS_ROT_90:
1524 *offset1 = screen_width * (fbh - 1) * ps;
1525 if (field_offset)
1526 *offset0 = *offset1 + field_offset * ps;
1527 else
1528 *offset0 = *offset1;
1529 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1530 (fieldmode ? 1 : 0), ps);
1531 *pix_inc = pixinc(-screen_width, ps);
1532 break;
1533 case OMAP_DSS_ROT_180:
1534 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1535 if (field_offset)
1536 *offset0 = *offset1 - field_offset * screen_width * ps;
1537 else
1538 *offset0 = *offset1;
1539 *row_inc = pixinc(-1 -
1540 (screen_width - fbw) -
1541 (fieldmode ? screen_width : 0),
1542 ps);
1543 *pix_inc = pixinc(-1, ps);
1544 break;
1545 case OMAP_DSS_ROT_270:
1546 *offset1 = (fbw - 1) * ps;
1547 if (field_offset)
1548 *offset0 = *offset1 - field_offset * ps;
1549 else
1550 *offset0 = *offset1;
1551 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1552 (fieldmode ? 1 : 0), ps);
1553 *pix_inc = pixinc(screen_width, ps);
1554 break;
1555
1556 /* mirroring */
1557 case OMAP_DSS_ROT_0 + 4:
1558 *offset1 = (fbw - 1) * ps;
1559 if (field_offset)
1560 *offset0 = *offset1 + field_offset * screen_width * ps;
1561 else
1562 *offset0 = *offset1;
1563 *row_inc = pixinc(screen_width * 2 - 1 +
1564 (fieldmode ? screen_width : 0),
1565 ps);
1566 *pix_inc = pixinc(-1, ps);
1567 break;
1568
1569 case OMAP_DSS_ROT_90 + 4:
1570 *offset1 = 0;
1571 if (field_offset)
1572 *offset0 = *offset1 + field_offset * ps;
1573 else
1574 *offset0 = *offset1;
1575 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1576 (fieldmode ? 1 : 0),
1577 ps);
1578 *pix_inc = pixinc(screen_width, ps);
1579 break;
1580
1581 case OMAP_DSS_ROT_180 + 4:
1582 *offset1 = screen_width * (fbh - 1) * ps;
1583 if (field_offset)
1584 *offset0 = *offset1 - field_offset * screen_width * ps;
1585 else
1586 *offset0 = *offset1;
1587 *row_inc = pixinc(1 - screen_width * 2 -
1588 (fieldmode ? screen_width : 0),
1589 ps);
1590 *pix_inc = pixinc(1, ps);
1591 break;
1592
1593 case OMAP_DSS_ROT_270 + 4:
1594 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1595 if (field_offset)
1596 *offset0 = *offset1 - field_offset * ps;
1597 else
1598 *offset0 = *offset1;
1599 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1600 (fieldmode ? 1 : 0),
1601 ps);
1602 *pix_inc = pixinc(-screen_width, ps);
1603 break;
1604
1605 default:
1606 BUG();
1607 }
1608 }
1609
1610 static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1611 u16 height, u16 out_width, u16 out_height,
1612 enum omap_color_mode color_mode)
1613 {
1614 u32 fclk = 0;
1615 u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
1616
1617 if (height <= out_height && width <= out_width)
1618 return (unsigned long) pclk;
1619
1620 if (height > out_height) {
1621 struct omap_dss_device *dssdev = dispc_mgr_get_device(channel);
1622 unsigned int ppl = dssdev->panel.timings.x_res;
1623
1624 tmp = pclk * height * out_width;
1625 do_div(tmp, 2 * out_height * ppl);
1626 fclk = tmp;
1627
1628 if (height > 2 * out_height) {
1629 if (ppl == out_width)
1630 return 0;
1631
1632 tmp = pclk * (height - 2 * out_height) * out_width;
1633 do_div(tmp, 2 * out_height * (ppl - out_width));
1634 fclk = max(fclk, (u32) tmp);
1635 }
1636 }
1637
1638 if (width > out_width) {
1639 tmp = pclk * width;
1640 do_div(tmp, out_width);
1641 fclk = max(fclk, (u32) tmp);
1642
1643 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1644 fclk <<= 1;
1645 }
1646
1647 return fclk;
1648 }
1649
1650 static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1651 u16 height, u16 out_width, u16 out_height)
1652 {
1653 unsigned int hf, vf;
1654
1655 /*
1656 * FIXME how to determine the 'A' factor
1657 * for the no downscaling case ?
1658 */
1659
1660 if (width > 3 * out_width)
1661 hf = 4;
1662 else if (width > 2 * out_width)
1663 hf = 3;
1664 else if (width > out_width)
1665 hf = 2;
1666 else
1667 hf = 1;
1668
1669 if (height > out_height)
1670 vf = 2;
1671 else
1672 vf = 1;
1673
1674 if (cpu_is_omap24xx()) {
1675 if (vf > 1 && hf > 1)
1676 return dispc_mgr_pclk_rate(channel) * 4;
1677 else
1678 return dispc_mgr_pclk_rate(channel) * 2;
1679 } else if (cpu_is_omap34xx()) {
1680 return dispc_mgr_pclk_rate(channel) * vf * hf;
1681 } else {
1682 return dispc_mgr_pclk_rate(channel) * hf;
1683 }
1684 }
1685
1686 static int dispc_ovl_calc_scaling(enum omap_plane plane,
1687 enum omap_channel channel, u16 width, u16 height,
1688 u16 out_width, u16 out_height,
1689 enum omap_color_mode color_mode, bool *five_taps)
1690 {
1691 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
1692 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
1693 const int maxsinglelinewidth =
1694 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
1695 unsigned long fclk = 0;
1696
1697 if (width == out_width && height == out_height)
1698 return 0;
1699
1700 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
1701 return -EINVAL;
1702
1703 if (out_width < width / maxdownscale ||
1704 out_width > width * 8)
1705 return -EINVAL;
1706
1707 if (out_height < height / maxdownscale ||
1708 out_height > height * 8)
1709 return -EINVAL;
1710
1711 if (cpu_is_omap24xx()) {
1712 if (width > maxsinglelinewidth)
1713 DSSERR("Cannot scale max input width exceeded");
1714 *five_taps = false;
1715 fclk = calc_fclk(channel, width, height, out_width,
1716 out_height);
1717 } else if (cpu_is_omap34xx()) {
1718 if (width > (maxsinglelinewidth * 2)) {
1719 DSSERR("Cannot setup scaling");
1720 DSSERR("width exceeds maximum width possible");
1721 return -EINVAL;
1722 }
1723 fclk = calc_fclk_five_taps(channel, width, height, out_width,
1724 out_height, color_mode);
1725 if (width > maxsinglelinewidth) {
1726 if (height > out_height && height < out_height * 2)
1727 *five_taps = false;
1728 else {
1729 DSSERR("cannot setup scaling with five taps");
1730 return -EINVAL;
1731 }
1732 }
1733 if (!*five_taps)
1734 fclk = calc_fclk(channel, width, height, out_width,
1735 out_height);
1736 } else {
1737 if (width > maxsinglelinewidth) {
1738 DSSERR("Cannot scale width exceeds max line width");
1739 return -EINVAL;
1740 }
1741 fclk = calc_fclk(channel, width, height, out_width,
1742 out_height);
1743 }
1744
1745 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1746 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1747
1748 if (!fclk || fclk > dispc_fclk_rate()) {
1749 DSSERR("failed to set up scaling, "
1750 "required fclk rate = %lu Hz, "
1751 "current fclk rate = %lu Hz\n",
1752 fclk, dispc_fclk_rate());
1753 return -EINVAL;
1754 }
1755
1756 return 0;
1757 }
1758
1759 int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
1760 bool ilace, bool replication)
1761 {
1762 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
1763 bool five_taps = true;
1764 bool fieldmode = 0;
1765 int r, cconv = 0;
1766 unsigned offset0, offset1;
1767 s32 row_inc;
1768 s32 pix_inc;
1769 u16 frame_height = oi->height;
1770 unsigned int field_offset = 0;
1771 u16 outw, outh;
1772 enum omap_channel channel;
1773
1774 channel = dispc_ovl_get_channel_out(plane);
1775
1776 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
1777 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d\n",
1778 plane, oi->paddr, oi->p_uv_addr,
1779 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
1780 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
1781 oi->mirror, ilace, channel, replication);
1782
1783 if (oi->paddr == 0)
1784 return -EINVAL;
1785
1786 outw = oi->out_width == 0 ? oi->width : oi->out_width;
1787 outh = oi->out_height == 0 ? oi->height : oi->out_height;
1788
1789 if (ilace && oi->height == outh)
1790 fieldmode = 1;
1791
1792 if (ilace) {
1793 if (fieldmode)
1794 oi->height /= 2;
1795 oi->pos_y /= 2;
1796 outh /= 2;
1797
1798 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1799 "out_height %d\n",
1800 oi->height, oi->pos_y, outh);
1801 }
1802
1803 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
1804 return -EINVAL;
1805
1806 r = dispc_ovl_calc_scaling(plane, channel, oi->width, oi->height,
1807 outw, outh, oi->color_mode,
1808 &five_taps);
1809 if (r)
1810 return r;
1811
1812 if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
1813 oi->color_mode == OMAP_DSS_COLOR_UYVY ||
1814 oi->color_mode == OMAP_DSS_COLOR_NV12)
1815 cconv = 1;
1816
1817 if (ilace && !fieldmode) {
1818 /*
1819 * when downscaling the bottom field may have to start several
1820 * source lines below the top field. Unfortunately ACCUI
1821 * registers will only hold the fractional part of the offset
1822 * so the integer part must be added to the base address of the
1823 * bottom field.
1824 */
1825 if (!oi->height || oi->height == outh)
1826 field_offset = 0;
1827 else
1828 field_offset = oi->height / outh / 2;
1829 }
1830
1831 /* Fields are independent but interleaved in memory. */
1832 if (fieldmode)
1833 field_offset = 1;
1834
1835 if (oi->rotation_type == OMAP_DSS_ROT_DMA)
1836 calc_dma_rotation_offset(oi->rotation, oi->mirror,
1837 oi->screen_width, oi->width, frame_height,
1838 oi->color_mode, fieldmode, field_offset,
1839 &offset0, &offset1, &row_inc, &pix_inc);
1840 else
1841 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
1842 oi->screen_width, oi->width, frame_height,
1843 oi->color_mode, fieldmode, field_offset,
1844 &offset0, &offset1, &row_inc, &pix_inc);
1845
1846 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1847 offset0, offset1, row_inc, pix_inc);
1848
1849 dispc_ovl_set_color_mode(plane, oi->color_mode);
1850
1851 dispc_ovl_set_ba0(plane, oi->paddr + offset0);
1852 dispc_ovl_set_ba1(plane, oi->paddr + offset1);
1853
1854 if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
1855 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
1856 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
1857 }
1858
1859
1860 dispc_ovl_set_row_inc(plane, row_inc);
1861 dispc_ovl_set_pix_inc(plane, pix_inc);
1862
1863 DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, oi->width,
1864 oi->height, outw, outh);
1865
1866 dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
1867
1868 dispc_ovl_set_pic_size(plane, oi->width, oi->height);
1869
1870 if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
1871 dispc_ovl_set_scaling(plane, oi->width, oi->height,
1872 outw, outh,
1873 ilace, five_taps, fieldmode,
1874 oi->color_mode, oi->rotation);
1875 dispc_ovl_set_vid_size(plane, outw, outh);
1876 dispc_ovl_set_vid_color_conv(plane, cconv);
1877 }
1878
1879 dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
1880 oi->color_mode);
1881
1882 dispc_ovl_set_zorder(plane, oi->zorder);
1883 dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
1884 dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
1885
1886 dispc_ovl_enable_replication(plane, replication);
1887
1888 return 0;
1889 }
1890
1891 int dispc_ovl_enable(enum omap_plane plane, bool enable)
1892 {
1893 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
1894
1895 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
1896
1897 return 0;
1898 }
1899
1900 static void dispc_disable_isr(void *data, u32 mask)
1901 {
1902 struct completion *compl = data;
1903 complete(compl);
1904 }
1905
1906 static void _enable_lcd_out(enum omap_channel channel, bool enable)
1907 {
1908 if (channel == OMAP_DSS_CHANNEL_LCD2) {
1909 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1910 /* flush posted write */
1911 dispc_read_reg(DISPC_CONTROL2);
1912 } else {
1913 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1914 dispc_read_reg(DISPC_CONTROL);
1915 }
1916 }
1917
1918 static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
1919 {
1920 struct completion frame_done_completion;
1921 bool is_on;
1922 int r;
1923 u32 irq;
1924
1925 /* When we disable LCD output, we need to wait until frame is done.
1926 * Otherwise the DSS is still working, and turning off the clocks
1927 * prevents DSS from going to OFF mode */
1928 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1929 REG_GET(DISPC_CONTROL2, 0, 0) :
1930 REG_GET(DISPC_CONTROL, 0, 0);
1931
1932 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1933 DISPC_IRQ_FRAMEDONE;
1934
1935 if (!enable && is_on) {
1936 init_completion(&frame_done_completion);
1937
1938 r = omap_dispc_register_isr(dispc_disable_isr,
1939 &frame_done_completion, irq);
1940
1941 if (r)
1942 DSSERR("failed to register FRAMEDONE isr\n");
1943 }
1944
1945 _enable_lcd_out(channel, enable);
1946
1947 if (!enable && is_on) {
1948 if (!wait_for_completion_timeout(&frame_done_completion,
1949 msecs_to_jiffies(100)))
1950 DSSERR("timeout waiting for FRAME DONE\n");
1951
1952 r = omap_dispc_unregister_isr(dispc_disable_isr,
1953 &frame_done_completion, irq);
1954
1955 if (r)
1956 DSSERR("failed to unregister FRAMEDONE isr\n");
1957 }
1958 }
1959
1960 static void _enable_digit_out(bool enable)
1961 {
1962 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1963 /* flush posted write */
1964 dispc_read_reg(DISPC_CONTROL);
1965 }
1966
1967 static void dispc_mgr_enable_digit_out(bool enable)
1968 {
1969 struct completion frame_done_completion;
1970 enum dss_hdmi_venc_clk_source_select src;
1971 int r, i;
1972 u32 irq_mask;
1973 int num_irqs;
1974
1975 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
1976 return;
1977
1978 src = dss_get_hdmi_venc_clk_source();
1979
1980 if (enable) {
1981 unsigned long flags;
1982 /* When we enable digit output, we'll get an extra digit
1983 * sync lost interrupt, that we need to ignore */
1984 spin_lock_irqsave(&dispc.irq_lock, flags);
1985 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1986 _omap_dispc_set_irqs();
1987 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1988 }
1989
1990 /* When we disable digit output, we need to wait until fields are done.
1991 * Otherwise the DSS is still working, and turning off the clocks
1992 * prevents DSS from going to OFF mode. And when enabling, we need to
1993 * wait for the extra sync losts */
1994 init_completion(&frame_done_completion);
1995
1996 if (src == DSS_HDMI_M_PCLK && enable == false) {
1997 irq_mask = DISPC_IRQ_FRAMEDONETV;
1998 num_irqs = 1;
1999 } else {
2000 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2001 /* XXX I understand from TRM that we should only wait for the
2002 * current field to complete. But it seems we have to wait for
2003 * both fields */
2004 num_irqs = 2;
2005 }
2006
2007 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
2008 irq_mask);
2009 if (r)
2010 DSSERR("failed to register %x isr\n", irq_mask);
2011
2012 _enable_digit_out(enable);
2013
2014 for (i = 0; i < num_irqs; ++i) {
2015 if (!wait_for_completion_timeout(&frame_done_completion,
2016 msecs_to_jiffies(100)))
2017 DSSERR("timeout waiting for digit out to %s\n",
2018 enable ? "start" : "stop");
2019 }
2020
2021 r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2022 irq_mask);
2023 if (r)
2024 DSSERR("failed to unregister %x isr\n", irq_mask);
2025
2026 if (enable) {
2027 unsigned long flags;
2028 spin_lock_irqsave(&dispc.irq_lock, flags);
2029 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
2030 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2031 _omap_dispc_set_irqs();
2032 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2033 }
2034 }
2035
2036 bool dispc_mgr_is_enabled(enum omap_channel channel)
2037 {
2038 if (channel == OMAP_DSS_CHANNEL_LCD)
2039 return !!REG_GET(DISPC_CONTROL, 0, 0);
2040 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2041 return !!REG_GET(DISPC_CONTROL, 1, 1);
2042 else if (channel == OMAP_DSS_CHANNEL_LCD2)
2043 return !!REG_GET(DISPC_CONTROL2, 0, 0);
2044 else
2045 BUG();
2046 }
2047
2048 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2049 {
2050 if (dispc_mgr_is_lcd(channel))
2051 dispc_mgr_enable_lcd_out(channel, enable);
2052 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2053 dispc_mgr_enable_digit_out(enable);
2054 else
2055 BUG();
2056 }
2057
2058 void dispc_lcd_enable_signal_polarity(bool act_high)
2059 {
2060 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2061 return;
2062
2063 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2064 }
2065
2066 void dispc_lcd_enable_signal(bool enable)
2067 {
2068 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2069 return;
2070
2071 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2072 }
2073
2074 void dispc_pck_free_enable(bool enable)
2075 {
2076 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2077 return;
2078
2079 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2080 }
2081
2082 void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2083 {
2084 if (channel == OMAP_DSS_CHANNEL_LCD2)
2085 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2086 else
2087 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
2088 }
2089
2090
2091 void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
2092 enum omap_lcd_display_type type)
2093 {
2094 int mode;
2095
2096 switch (type) {
2097 case OMAP_DSS_LCD_DISPLAY_STN:
2098 mode = 0;
2099 break;
2100
2101 case OMAP_DSS_LCD_DISPLAY_TFT:
2102 mode = 1;
2103 break;
2104
2105 default:
2106 BUG();
2107 return;
2108 }
2109
2110 if (channel == OMAP_DSS_CHANNEL_LCD2)
2111 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2112 else
2113 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
2114 }
2115
2116 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2117 {
2118 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2119 }
2120
2121
2122 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2123 {
2124 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2125 }
2126
2127 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2128 enum omap_dss_trans_key_type type,
2129 u32 trans_key)
2130 {
2131 if (ch == OMAP_DSS_CHANNEL_LCD)
2132 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2133 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2134 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2135 else /* OMAP_DSS_CHANNEL_LCD2 */
2136 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
2137
2138 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2139 }
2140
2141 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2142 {
2143 if (ch == OMAP_DSS_CHANNEL_LCD)
2144 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2145 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2146 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2147 else /* OMAP_DSS_CHANNEL_LCD2 */
2148 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
2149 }
2150
2151 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2152 bool enable)
2153 {
2154 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2155 return;
2156
2157 if (ch == OMAP_DSS_CHANNEL_LCD)
2158 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2159 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2160 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2161 }
2162
2163 void dispc_mgr_setup(enum omap_channel channel,
2164 struct omap_overlay_manager_info *info)
2165 {
2166 dispc_mgr_set_default_color(channel, info->default_color);
2167 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2168 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2169 dispc_mgr_enable_alpha_fixed_zorder(channel,
2170 info->partial_alpha_enabled);
2171 if (dss_has_feature(FEAT_CPR)) {
2172 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2173 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2174 }
2175 }
2176
2177 void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2178 {
2179 int code;
2180
2181 switch (data_lines) {
2182 case 12:
2183 code = 0;
2184 break;
2185 case 16:
2186 code = 1;
2187 break;
2188 case 18:
2189 code = 2;
2190 break;
2191 case 24:
2192 code = 3;
2193 break;
2194 default:
2195 BUG();
2196 return;
2197 }
2198
2199 if (channel == OMAP_DSS_CHANNEL_LCD2)
2200 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2201 else
2202 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2203 }
2204
2205 void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2206 {
2207 u32 l;
2208 int gpout0, gpout1;
2209
2210 switch (mode) {
2211 case DSS_IO_PAD_MODE_RESET:
2212 gpout0 = 0;
2213 gpout1 = 0;
2214 break;
2215 case DSS_IO_PAD_MODE_RFBI:
2216 gpout0 = 1;
2217 gpout1 = 0;
2218 break;
2219 case DSS_IO_PAD_MODE_BYPASS:
2220 gpout0 = 1;
2221 gpout1 = 1;
2222 break;
2223 default:
2224 BUG();
2225 return;
2226 }
2227
2228 l = dispc_read_reg(DISPC_CONTROL);
2229 l = FLD_MOD(l, gpout0, 15, 15);
2230 l = FLD_MOD(l, gpout1, 16, 16);
2231 dispc_write_reg(DISPC_CONTROL, l);
2232 }
2233
2234 void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2235 {
2236 if (channel == OMAP_DSS_CHANNEL_LCD2)
2237 REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
2238 else
2239 REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
2240 }
2241
2242 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2243 int vsw, int vfp, int vbp)
2244 {
2245 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2246 if (hsw < 1 || hsw > 64 ||
2247 hfp < 1 || hfp > 256 ||
2248 hbp < 1 || hbp > 256 ||
2249 vsw < 1 || vsw > 64 ||
2250 vfp < 0 || vfp > 255 ||
2251 vbp < 0 || vbp > 255)
2252 return false;
2253 } else {
2254 if (hsw < 1 || hsw > 256 ||
2255 hfp < 1 || hfp > 4096 ||
2256 hbp < 1 || hbp > 4096 ||
2257 vsw < 1 || vsw > 256 ||
2258 vfp < 0 || vfp > 4095 ||
2259 vbp < 0 || vbp > 4095)
2260 return false;
2261 }
2262
2263 return true;
2264 }
2265
2266 bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2267 {
2268 return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2269 timings->hbp, timings->vsw,
2270 timings->vfp, timings->vbp);
2271 }
2272
2273 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
2274 int hfp, int hbp, int vsw, int vfp, int vbp)
2275 {
2276 u32 timing_h, timing_v;
2277
2278 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2279 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2280 FLD_VAL(hbp-1, 27, 20);
2281
2282 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2283 FLD_VAL(vbp, 27, 20);
2284 } else {
2285 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2286 FLD_VAL(hbp-1, 31, 20);
2287
2288 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2289 FLD_VAL(vbp, 31, 20);
2290 }
2291
2292 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2293 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2294 }
2295
2296 /* change name to mode? */
2297 void dispc_mgr_set_lcd_timings(enum omap_channel channel,
2298 struct omap_video_timings *timings)
2299 {
2300 unsigned xtot, ytot;
2301 unsigned long ht, vt;
2302
2303 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2304 timings->hbp, timings->vsw,
2305 timings->vfp, timings->vbp))
2306 BUG();
2307
2308 _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
2309 timings->hbp, timings->vsw, timings->vfp,
2310 timings->vbp);
2311
2312 dispc_mgr_set_lcd_size(channel, timings->x_res, timings->y_res);
2313
2314 xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2315 ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2316
2317 ht = (timings->pixel_clock * 1000) / xtot;
2318 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2319
2320 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2321 timings->y_res);
2322 DSSDBG("pck %u\n", timings->pixel_clock);
2323 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2324 timings->hsw, timings->hfp, timings->hbp,
2325 timings->vsw, timings->vfp, timings->vbp);
2326
2327 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2328 }
2329
2330 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2331 u16 pck_div)
2332 {
2333 BUG_ON(lck_div < 1);
2334 BUG_ON(pck_div < 1);
2335
2336 dispc_write_reg(DISPC_DIVISORo(channel),
2337 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2338 }
2339
2340 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2341 int *pck_div)
2342 {
2343 u32 l;
2344 l = dispc_read_reg(DISPC_DIVISORo(channel));
2345 *lck_div = FLD_GET(l, 23, 16);
2346 *pck_div = FLD_GET(l, 7, 0);
2347 }
2348
2349 unsigned long dispc_fclk_rate(void)
2350 {
2351 struct platform_device *dsidev;
2352 unsigned long r = 0;
2353
2354 switch (dss_get_dispc_clk_source()) {
2355 case OMAP_DSS_CLK_SRC_FCK:
2356 r = clk_get_rate(dispc.dss_clk);
2357 break;
2358 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2359 dsidev = dsi_get_dsidev_from_id(0);
2360 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2361 break;
2362 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2363 dsidev = dsi_get_dsidev_from_id(1);
2364 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2365 break;
2366 default:
2367 BUG();
2368 }
2369
2370 return r;
2371 }
2372
2373 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
2374 {
2375 struct platform_device *dsidev;
2376 int lcd;
2377 unsigned long r;
2378 u32 l;
2379
2380 l = dispc_read_reg(DISPC_DIVISORo(channel));
2381
2382 lcd = FLD_GET(l, 23, 16);
2383
2384 switch (dss_get_lcd_clk_source(channel)) {
2385 case OMAP_DSS_CLK_SRC_FCK:
2386 r = clk_get_rate(dispc.dss_clk);
2387 break;
2388 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2389 dsidev = dsi_get_dsidev_from_id(0);
2390 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2391 break;
2392 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2393 dsidev = dsi_get_dsidev_from_id(1);
2394 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2395 break;
2396 default:
2397 BUG();
2398 }
2399
2400 return r / lcd;
2401 }
2402
2403 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
2404 {
2405 unsigned long r;
2406
2407 if (dispc_mgr_is_lcd(channel)) {
2408 int pcd;
2409 u32 l;
2410
2411 l = dispc_read_reg(DISPC_DIVISORo(channel));
2412
2413 pcd = FLD_GET(l, 7, 0);
2414
2415 r = dispc_mgr_lclk_rate(channel);
2416
2417 return r / pcd;
2418 } else {
2419 struct omap_dss_device *dssdev =
2420 dispc_mgr_get_device(channel);
2421
2422 switch (dssdev->type) {
2423 case OMAP_DISPLAY_TYPE_VENC:
2424 return venc_get_pixel_clock();
2425 case OMAP_DISPLAY_TYPE_HDMI:
2426 return hdmi_get_pixel_clock();
2427 default:
2428 BUG();
2429 }
2430 }
2431 }
2432
2433 void dispc_dump_clocks(struct seq_file *s)
2434 {
2435 int lcd, pcd;
2436 u32 l;
2437 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2438 enum omap_dss_clk_source lcd_clk_src;
2439
2440 if (dispc_runtime_get())
2441 return;
2442
2443 seq_printf(s, "- DISPC -\n");
2444
2445 seq_printf(s, "dispc fclk source = %s (%s)\n",
2446 dss_get_generic_clk_source_name(dispc_clk_src),
2447 dss_feat_get_clk_source_name(dispc_clk_src));
2448
2449 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2450
2451 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2452 seq_printf(s, "- DISPC-CORE-CLK -\n");
2453 l = dispc_read_reg(DISPC_DIVISOR);
2454 lcd = FLD_GET(l, 23, 16);
2455
2456 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2457 (dispc_fclk_rate()/lcd), lcd);
2458 }
2459 seq_printf(s, "- LCD1 -\n");
2460
2461 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2462
2463 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2464 dss_get_generic_clk_source_name(lcd_clk_src),
2465 dss_feat_get_clk_source_name(lcd_clk_src));
2466
2467 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2468
2469 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2470 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2471 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2472 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2473 if (dss_has_feature(FEAT_MGR_LCD2)) {
2474 seq_printf(s, "- LCD2 -\n");
2475
2476 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2477
2478 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2479 dss_get_generic_clk_source_name(lcd_clk_src),
2480 dss_feat_get_clk_source_name(lcd_clk_src));
2481
2482 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
2483
2484 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2485 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2486 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2487 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2488 }
2489
2490 dispc_runtime_put();
2491 }
2492
2493 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2494 void dispc_dump_irqs(struct seq_file *s)
2495 {
2496 unsigned long flags;
2497 struct dispc_irq_stats stats;
2498
2499 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2500
2501 stats = dispc.irq_stats;
2502 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2503 dispc.irq_stats.last_reset = jiffies;
2504
2505 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2506
2507 seq_printf(s, "period %u ms\n",
2508 jiffies_to_msecs(jiffies - stats.last_reset));
2509
2510 seq_printf(s, "irqs %d\n", stats.irq_count);
2511 #define PIS(x) \
2512 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2513
2514 PIS(FRAMEDONE);
2515 PIS(VSYNC);
2516 PIS(EVSYNC_EVEN);
2517 PIS(EVSYNC_ODD);
2518 PIS(ACBIAS_COUNT_STAT);
2519 PIS(PROG_LINE_NUM);
2520 PIS(GFX_FIFO_UNDERFLOW);
2521 PIS(GFX_END_WIN);
2522 PIS(PAL_GAMMA_MASK);
2523 PIS(OCP_ERR);
2524 PIS(VID1_FIFO_UNDERFLOW);
2525 PIS(VID1_END_WIN);
2526 PIS(VID2_FIFO_UNDERFLOW);
2527 PIS(VID2_END_WIN);
2528 if (dss_feat_get_num_ovls() > 3) {
2529 PIS(VID3_FIFO_UNDERFLOW);
2530 PIS(VID3_END_WIN);
2531 }
2532 PIS(SYNC_LOST);
2533 PIS(SYNC_LOST_DIGIT);
2534 PIS(WAKEUP);
2535 if (dss_has_feature(FEAT_MGR_LCD2)) {
2536 PIS(FRAMEDONE2);
2537 PIS(VSYNC2);
2538 PIS(ACBIAS_COUNT_STAT2);
2539 PIS(SYNC_LOST2);
2540 }
2541 #undef PIS
2542 }
2543 #endif
2544
2545 void dispc_dump_regs(struct seq_file *s)
2546 {
2547 int i, j;
2548 const char *mgr_names[] = {
2549 [OMAP_DSS_CHANNEL_LCD] = "LCD",
2550 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
2551 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
2552 };
2553 const char *ovl_names[] = {
2554 [OMAP_DSS_GFX] = "GFX",
2555 [OMAP_DSS_VIDEO1] = "VID1",
2556 [OMAP_DSS_VIDEO2] = "VID2",
2557 [OMAP_DSS_VIDEO3] = "VID3",
2558 };
2559 const char **p_names;
2560
2561 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
2562
2563 if (dispc_runtime_get())
2564 return;
2565
2566 /* DISPC common registers */
2567 DUMPREG(DISPC_REVISION);
2568 DUMPREG(DISPC_SYSCONFIG);
2569 DUMPREG(DISPC_SYSSTATUS);
2570 DUMPREG(DISPC_IRQSTATUS);
2571 DUMPREG(DISPC_IRQENABLE);
2572 DUMPREG(DISPC_CONTROL);
2573 DUMPREG(DISPC_CONFIG);
2574 DUMPREG(DISPC_CAPABLE);
2575 DUMPREG(DISPC_LINE_STATUS);
2576 DUMPREG(DISPC_LINE_NUMBER);
2577 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
2578 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
2579 DUMPREG(DISPC_GLOBAL_ALPHA);
2580 if (dss_has_feature(FEAT_MGR_LCD2)) {
2581 DUMPREG(DISPC_CONTROL2);
2582 DUMPREG(DISPC_CONFIG2);
2583 }
2584
2585 #undef DUMPREG
2586
2587 #define DISPC_REG(i, name) name(i)
2588 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2589 48 - strlen(#r) - strlen(p_names[i]), " ", \
2590 dispc_read_reg(DISPC_REG(i, r)))
2591
2592 p_names = mgr_names;
2593
2594 /* DISPC channel specific registers */
2595 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2596 DUMPREG(i, DISPC_DEFAULT_COLOR);
2597 DUMPREG(i, DISPC_TRANS_COLOR);
2598 DUMPREG(i, DISPC_SIZE_MGR);
2599
2600 if (i == OMAP_DSS_CHANNEL_DIGIT)
2601 continue;
2602
2603 DUMPREG(i, DISPC_DEFAULT_COLOR);
2604 DUMPREG(i, DISPC_TRANS_COLOR);
2605 DUMPREG(i, DISPC_TIMING_H);
2606 DUMPREG(i, DISPC_TIMING_V);
2607 DUMPREG(i, DISPC_POL_FREQ);
2608 DUMPREG(i, DISPC_DIVISORo);
2609 DUMPREG(i, DISPC_SIZE_MGR);
2610
2611 DUMPREG(i, DISPC_DATA_CYCLE1);
2612 DUMPREG(i, DISPC_DATA_CYCLE2);
2613 DUMPREG(i, DISPC_DATA_CYCLE3);
2614
2615 if (dss_has_feature(FEAT_CPR)) {
2616 DUMPREG(i, DISPC_CPR_COEF_R);
2617 DUMPREG(i, DISPC_CPR_COEF_G);
2618 DUMPREG(i, DISPC_CPR_COEF_B);
2619 }
2620 }
2621
2622 p_names = ovl_names;
2623
2624 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2625 DUMPREG(i, DISPC_OVL_BA0);
2626 DUMPREG(i, DISPC_OVL_BA1);
2627 DUMPREG(i, DISPC_OVL_POSITION);
2628 DUMPREG(i, DISPC_OVL_SIZE);
2629 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2630 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2631 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2632 DUMPREG(i, DISPC_OVL_ROW_INC);
2633 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2634 if (dss_has_feature(FEAT_PRELOAD))
2635 DUMPREG(i, DISPC_OVL_PRELOAD);
2636
2637 if (i == OMAP_DSS_GFX) {
2638 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2639 DUMPREG(i, DISPC_OVL_TABLE_BA);
2640 continue;
2641 }
2642
2643 DUMPREG(i, DISPC_OVL_FIR);
2644 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2645 DUMPREG(i, DISPC_OVL_ACCU0);
2646 DUMPREG(i, DISPC_OVL_ACCU1);
2647 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2648 DUMPREG(i, DISPC_OVL_BA0_UV);
2649 DUMPREG(i, DISPC_OVL_BA1_UV);
2650 DUMPREG(i, DISPC_OVL_FIR2);
2651 DUMPREG(i, DISPC_OVL_ACCU2_0);
2652 DUMPREG(i, DISPC_OVL_ACCU2_1);
2653 }
2654 if (dss_has_feature(FEAT_ATTR2))
2655 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2656 if (dss_has_feature(FEAT_PRELOAD))
2657 DUMPREG(i, DISPC_OVL_PRELOAD);
2658 }
2659
2660 #undef DISPC_REG
2661 #undef DUMPREG
2662
2663 #define DISPC_REG(plane, name, i) name(plane, i)
2664 #define DUMPREG(plane, name, i) \
2665 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2666 46 - strlen(#name) - strlen(p_names[plane]), " ", \
2667 dispc_read_reg(DISPC_REG(plane, name, i)))
2668
2669 /* Video pipeline coefficient registers */
2670
2671 /* start from OMAP_DSS_VIDEO1 */
2672 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2673 for (j = 0; j < 8; j++)
2674 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
2675
2676 for (j = 0; j < 8; j++)
2677 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
2678
2679 for (j = 0; j < 5; j++)
2680 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
2681
2682 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2683 for (j = 0; j < 8; j++)
2684 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2685 }
2686
2687 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2688 for (j = 0; j < 8; j++)
2689 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
2690
2691 for (j = 0; j < 8; j++)
2692 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
2693
2694 for (j = 0; j < 8; j++)
2695 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
2696 }
2697 }
2698
2699 dispc_runtime_put();
2700
2701 #undef DISPC_REG
2702 #undef DUMPREG
2703 }
2704
2705 static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
2706 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
2707 u8 acb)
2708 {
2709 u32 l = 0;
2710
2711 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2712 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2713
2714 l |= FLD_VAL(onoff, 17, 17);
2715 l |= FLD_VAL(rf, 16, 16);
2716 l |= FLD_VAL(ieo, 15, 15);
2717 l |= FLD_VAL(ipc, 14, 14);
2718 l |= FLD_VAL(ihs, 13, 13);
2719 l |= FLD_VAL(ivs, 12, 12);
2720 l |= FLD_VAL(acbi, 11, 8);
2721 l |= FLD_VAL(acb, 7, 0);
2722
2723 dispc_write_reg(DISPC_POL_FREQ(channel), l);
2724 }
2725
2726 void dispc_mgr_set_pol_freq(enum omap_channel channel,
2727 enum omap_panel_config config, u8 acbi, u8 acb)
2728 {
2729 _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
2730 (config & OMAP_DSS_LCD_RF) != 0,
2731 (config & OMAP_DSS_LCD_IEO) != 0,
2732 (config & OMAP_DSS_LCD_IPC) != 0,
2733 (config & OMAP_DSS_LCD_IHS) != 0,
2734 (config & OMAP_DSS_LCD_IVS) != 0,
2735 acbi, acb);
2736 }
2737
2738 /* with fck as input clock rate, find dispc dividers that produce req_pck */
2739 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2740 struct dispc_clock_info *cinfo)
2741 {
2742 u16 pcd_min, pcd_max;
2743 unsigned long best_pck;
2744 u16 best_ld, cur_ld;
2745 u16 best_pd, cur_pd;
2746
2747 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
2748 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
2749
2750 if (!is_tft)
2751 pcd_min = 3;
2752
2753 best_pck = 0;
2754 best_ld = 0;
2755 best_pd = 0;
2756
2757 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2758 unsigned long lck = fck / cur_ld;
2759
2760 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
2761 unsigned long pck = lck / cur_pd;
2762 long old_delta = abs(best_pck - req_pck);
2763 long new_delta = abs(pck - req_pck);
2764
2765 if (best_pck == 0 || new_delta < old_delta) {
2766 best_pck = pck;
2767 best_ld = cur_ld;
2768 best_pd = cur_pd;
2769
2770 if (pck == req_pck)
2771 goto found;
2772 }
2773
2774 if (pck < req_pck)
2775 break;
2776 }
2777
2778 if (lck / pcd_min < req_pck)
2779 break;
2780 }
2781
2782 found:
2783 cinfo->lck_div = best_ld;
2784 cinfo->pck_div = best_pd;
2785 cinfo->lck = fck / cinfo->lck_div;
2786 cinfo->pck = cinfo->lck / cinfo->pck_div;
2787 }
2788
2789 /* calculate clock rates using dividers in cinfo */
2790 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2791 struct dispc_clock_info *cinfo)
2792 {
2793 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2794 return -EINVAL;
2795 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
2796 return -EINVAL;
2797
2798 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2799 cinfo->pck = cinfo->lck / cinfo->pck_div;
2800
2801 return 0;
2802 }
2803
2804 int dispc_mgr_set_clock_div(enum omap_channel channel,
2805 struct dispc_clock_info *cinfo)
2806 {
2807 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2808 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2809
2810 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
2811
2812 return 0;
2813 }
2814
2815 int dispc_mgr_get_clock_div(enum omap_channel channel,
2816 struct dispc_clock_info *cinfo)
2817 {
2818 unsigned long fck;
2819
2820 fck = dispc_fclk_rate();
2821
2822 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2823 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
2824
2825 cinfo->lck = fck / cinfo->lck_div;
2826 cinfo->pck = cinfo->lck / cinfo->pck_div;
2827
2828 return 0;
2829 }
2830
2831 /* dispc.irq_lock has to be locked by the caller */
2832 static void _omap_dispc_set_irqs(void)
2833 {
2834 u32 mask;
2835 u32 old_mask;
2836 int i;
2837 struct omap_dispc_isr_data *isr_data;
2838
2839 mask = dispc.irq_error_mask;
2840
2841 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2842 isr_data = &dispc.registered_isr[i];
2843
2844 if (isr_data->isr == NULL)
2845 continue;
2846
2847 mask |= isr_data->mask;
2848 }
2849
2850 old_mask = dispc_read_reg(DISPC_IRQENABLE);
2851 /* clear the irqstatus for newly enabled irqs */
2852 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2853
2854 dispc_write_reg(DISPC_IRQENABLE, mask);
2855 }
2856
2857 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2858 {
2859 int i;
2860 int ret;
2861 unsigned long flags;
2862 struct omap_dispc_isr_data *isr_data;
2863
2864 if (isr == NULL)
2865 return -EINVAL;
2866
2867 spin_lock_irqsave(&dispc.irq_lock, flags);
2868
2869 /* check for duplicate entry */
2870 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2871 isr_data = &dispc.registered_isr[i];
2872 if (isr_data->isr == isr && isr_data->arg == arg &&
2873 isr_data->mask == mask) {
2874 ret = -EINVAL;
2875 goto err;
2876 }
2877 }
2878
2879 isr_data = NULL;
2880 ret = -EBUSY;
2881
2882 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2883 isr_data = &dispc.registered_isr[i];
2884
2885 if (isr_data->isr != NULL)
2886 continue;
2887
2888 isr_data->isr = isr;
2889 isr_data->arg = arg;
2890 isr_data->mask = mask;
2891 ret = 0;
2892
2893 break;
2894 }
2895
2896 if (ret)
2897 goto err;
2898
2899 _omap_dispc_set_irqs();
2900
2901 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2902
2903 return 0;
2904 err:
2905 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2906
2907 return ret;
2908 }
2909 EXPORT_SYMBOL(omap_dispc_register_isr);
2910
2911 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2912 {
2913 int i;
2914 unsigned long flags;
2915 int ret = -EINVAL;
2916 struct omap_dispc_isr_data *isr_data;
2917
2918 spin_lock_irqsave(&dispc.irq_lock, flags);
2919
2920 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2921 isr_data = &dispc.registered_isr[i];
2922 if (isr_data->isr != isr || isr_data->arg != arg ||
2923 isr_data->mask != mask)
2924 continue;
2925
2926 /* found the correct isr */
2927
2928 isr_data->isr = NULL;
2929 isr_data->arg = NULL;
2930 isr_data->mask = 0;
2931
2932 ret = 0;
2933 break;
2934 }
2935
2936 if (ret == 0)
2937 _omap_dispc_set_irqs();
2938
2939 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2940
2941 return ret;
2942 }
2943 EXPORT_SYMBOL(omap_dispc_unregister_isr);
2944
2945 #ifdef DEBUG
2946 static void print_irq_status(u32 status)
2947 {
2948 if ((status & dispc.irq_error_mask) == 0)
2949 return;
2950
2951 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2952
2953 #define PIS(x) \
2954 if (status & DISPC_IRQ_##x) \
2955 printk(#x " ");
2956 PIS(GFX_FIFO_UNDERFLOW);
2957 PIS(OCP_ERR);
2958 PIS(VID1_FIFO_UNDERFLOW);
2959 PIS(VID2_FIFO_UNDERFLOW);
2960 if (dss_feat_get_num_ovls() > 3)
2961 PIS(VID3_FIFO_UNDERFLOW);
2962 PIS(SYNC_LOST);
2963 PIS(SYNC_LOST_DIGIT);
2964 if (dss_has_feature(FEAT_MGR_LCD2))
2965 PIS(SYNC_LOST2);
2966 #undef PIS
2967
2968 printk("\n");
2969 }
2970 #endif
2971
2972 /* Called from dss.c. Note that we don't touch clocks here,
2973 * but we presume they are on because we got an IRQ. However,
2974 * an irq handler may turn the clocks off, so we may not have
2975 * clock later in the function. */
2976 static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
2977 {
2978 int i;
2979 u32 irqstatus, irqenable;
2980 u32 handledirqs = 0;
2981 u32 unhandled_errors;
2982 struct omap_dispc_isr_data *isr_data;
2983 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2984
2985 spin_lock(&dispc.irq_lock);
2986
2987 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2988 irqenable = dispc_read_reg(DISPC_IRQENABLE);
2989
2990 /* IRQ is not for us */
2991 if (!(irqstatus & irqenable)) {
2992 spin_unlock(&dispc.irq_lock);
2993 return IRQ_NONE;
2994 }
2995
2996 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2997 spin_lock(&dispc.irq_stats_lock);
2998 dispc.irq_stats.irq_count++;
2999 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3000 spin_unlock(&dispc.irq_stats_lock);
3001 #endif
3002
3003 #ifdef DEBUG
3004 if (dss_debug)
3005 print_irq_status(irqstatus);
3006 #endif
3007 /* Ack the interrupt. Do it here before clocks are possibly turned
3008 * off */
3009 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3010 /* flush posted write */
3011 dispc_read_reg(DISPC_IRQSTATUS);
3012
3013 /* make a copy and unlock, so that isrs can unregister
3014 * themselves */
3015 memcpy(registered_isr, dispc.registered_isr,
3016 sizeof(registered_isr));
3017
3018 spin_unlock(&dispc.irq_lock);
3019
3020 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3021 isr_data = &registered_isr[i];
3022
3023 if (!isr_data->isr)
3024 continue;
3025
3026 if (isr_data->mask & irqstatus) {
3027 isr_data->isr(isr_data->arg, irqstatus);
3028 handledirqs |= isr_data->mask;
3029 }
3030 }
3031
3032 spin_lock(&dispc.irq_lock);
3033
3034 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3035
3036 if (unhandled_errors) {
3037 dispc.error_irqs |= unhandled_errors;
3038
3039 dispc.irq_error_mask &= ~unhandled_errors;
3040 _omap_dispc_set_irqs();
3041
3042 schedule_work(&dispc.error_work);
3043 }
3044
3045 spin_unlock(&dispc.irq_lock);
3046
3047 return IRQ_HANDLED;
3048 }
3049
3050 static void dispc_error_worker(struct work_struct *work)
3051 {
3052 int i;
3053 u32 errors;
3054 unsigned long flags;
3055 static const unsigned fifo_underflow_bits[] = {
3056 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3057 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3058 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
3059 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
3060 };
3061
3062 static const unsigned sync_lost_bits[] = {
3063 DISPC_IRQ_SYNC_LOST,
3064 DISPC_IRQ_SYNC_LOST_DIGIT,
3065 DISPC_IRQ_SYNC_LOST2,
3066 };
3067
3068 spin_lock_irqsave(&dispc.irq_lock, flags);
3069 errors = dispc.error_irqs;
3070 dispc.error_irqs = 0;
3071 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3072
3073 dispc_runtime_get();
3074
3075 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3076 struct omap_overlay *ovl;
3077 unsigned bit;
3078
3079 ovl = omap_dss_get_overlay(i);
3080 bit = fifo_underflow_bits[i];
3081
3082 if (bit & errors) {
3083 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3084 ovl->name);
3085 dispc_ovl_enable(ovl->id, false);
3086 dispc_mgr_go(ovl->manager->id);
3087 mdelay(50);
3088 }
3089 }
3090
3091 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3092 struct omap_overlay_manager *mgr;
3093 unsigned bit;
3094
3095 mgr = omap_dss_get_overlay_manager(i);
3096 bit = sync_lost_bits[i];
3097
3098 if (bit & errors) {
3099 struct omap_dss_device *dssdev = mgr->device;
3100 bool enable;
3101
3102 DSSERR("SYNC_LOST on channel %s, restarting the output "
3103 "with video overlays disabled\n",
3104 mgr->name);
3105
3106 enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3107 dssdev->driver->disable(dssdev);
3108
3109 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3110 struct omap_overlay *ovl;
3111 ovl = omap_dss_get_overlay(i);
3112
3113 if (ovl->id != OMAP_DSS_GFX &&
3114 ovl->manager == mgr)
3115 dispc_ovl_enable(ovl->id, false);
3116 }
3117
3118 dispc_mgr_go(mgr->id);
3119 mdelay(50);
3120
3121 if (enable)
3122 dssdev->driver->enable(dssdev);
3123 }
3124 }
3125
3126 if (errors & DISPC_IRQ_OCP_ERR) {
3127 DSSERR("OCP_ERR\n");
3128 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3129 struct omap_overlay_manager *mgr;
3130 mgr = omap_dss_get_overlay_manager(i);
3131 if (mgr->device && mgr->device->driver)
3132 mgr->device->driver->disable(mgr->device);
3133 }
3134 }
3135
3136 spin_lock_irqsave(&dispc.irq_lock, flags);
3137 dispc.irq_error_mask |= errors;
3138 _omap_dispc_set_irqs();
3139 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3140
3141 dispc_runtime_put();
3142 }
3143
3144 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3145 {
3146 void dispc_irq_wait_handler(void *data, u32 mask)
3147 {
3148 complete((struct completion *)data);
3149 }
3150
3151 int r;
3152 DECLARE_COMPLETION_ONSTACK(completion);
3153
3154 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3155 irqmask);
3156
3157 if (r)
3158 return r;
3159
3160 timeout = wait_for_completion_timeout(&completion, timeout);
3161
3162 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3163
3164 if (timeout == 0)
3165 return -ETIMEDOUT;
3166
3167 if (timeout == -ERESTARTSYS)
3168 return -ERESTARTSYS;
3169
3170 return 0;
3171 }
3172
3173 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3174 unsigned long timeout)
3175 {
3176 void dispc_irq_wait_handler(void *data, u32 mask)
3177 {
3178 complete((struct completion *)data);
3179 }
3180
3181 int r;
3182 DECLARE_COMPLETION_ONSTACK(completion);
3183
3184 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3185 irqmask);
3186
3187 if (r)
3188 return r;
3189
3190 timeout = wait_for_completion_interruptible_timeout(&completion,
3191 timeout);
3192
3193 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3194
3195 if (timeout == 0)
3196 return -ETIMEDOUT;
3197
3198 if (timeout == -ERESTARTSYS)
3199 return -ERESTARTSYS;
3200
3201 return 0;
3202 }
3203
3204 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3205 void dispc_fake_vsync_irq(void)
3206 {
3207 u32 irqstatus = DISPC_IRQ_VSYNC;
3208 int i;
3209
3210 WARN_ON(!in_interrupt());
3211
3212 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3213 struct omap_dispc_isr_data *isr_data;
3214 isr_data = &dispc.registered_isr[i];
3215
3216 if (!isr_data->isr)
3217 continue;
3218
3219 if (isr_data->mask & irqstatus)
3220 isr_data->isr(isr_data->arg, irqstatus);
3221 }
3222 }
3223 #endif
3224
3225 static void _omap_dispc_initialize_irq(void)
3226 {
3227 unsigned long flags;
3228
3229 spin_lock_irqsave(&dispc.irq_lock, flags);
3230
3231 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3232
3233 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3234 if (dss_has_feature(FEAT_MGR_LCD2))
3235 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
3236 if (dss_feat_get_num_ovls() > 3)
3237 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
3238
3239 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3240 * so clear it */
3241 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3242
3243 _omap_dispc_set_irqs();
3244
3245 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3246 }
3247
3248 void dispc_enable_sidle(void)
3249 {
3250 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3251 }
3252
3253 void dispc_disable_sidle(void)
3254 {
3255 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3256 }
3257
3258 static void _omap_dispc_initial_config(void)
3259 {
3260 u32 l;
3261
3262 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3263 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3264 l = dispc_read_reg(DISPC_DIVISOR);
3265 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3266 l = FLD_MOD(l, 1, 0, 0);
3267 l = FLD_MOD(l, 1, 23, 16);
3268 dispc_write_reg(DISPC_DIVISOR, l);
3269 }
3270
3271 /* FUNCGATED */
3272 if (dss_has_feature(FEAT_FUNCGATED))
3273 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3274
3275 /* L3 firewall setting: enable access to OCM RAM */
3276 /* XXX this should be somewhere in plat-omap */
3277 if (cpu_is_omap24xx())
3278 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3279
3280 _dispc_setup_color_conv_coef();
3281
3282 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3283
3284 dispc_read_plane_fifo_sizes();
3285
3286 dispc_configure_burst_sizes();
3287
3288 dispc_ovl_enable_zorder_planes();
3289 }
3290
3291 /* DISPC HW IP initialisation */
3292 static int omap_dispchw_probe(struct platform_device *pdev)
3293 {
3294 u32 rev;
3295 int r = 0;
3296 struct resource *dispc_mem;
3297 struct clk *clk;
3298
3299 dispc.pdev = pdev;
3300
3301 clk = clk_get(&pdev->dev, "fck");
3302 if (IS_ERR(clk)) {
3303 DSSERR("can't get fck\n");
3304 r = PTR_ERR(clk);
3305 goto err_get_clk;
3306 }
3307
3308 dispc.dss_clk = clk;
3309
3310 spin_lock_init(&dispc.irq_lock);
3311
3312 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3313 spin_lock_init(&dispc.irq_stats_lock);
3314 dispc.irq_stats.last_reset = jiffies;
3315 #endif
3316
3317 INIT_WORK(&dispc.error_work, dispc_error_worker);
3318
3319 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3320 if (!dispc_mem) {
3321 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3322 r = -EINVAL;
3323 goto err_ioremap;
3324 }
3325 dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
3326 if (!dispc.base) {
3327 DSSERR("can't ioremap DISPC\n");
3328 r = -ENOMEM;
3329 goto err_ioremap;
3330 }
3331 dispc.irq = platform_get_irq(dispc.pdev, 0);
3332 if (dispc.irq < 0) {
3333 DSSERR("platform_get_irq failed\n");
3334 r = -ENODEV;
3335 goto err_irq;
3336 }
3337
3338 r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3339 "OMAP DISPC", dispc.pdev);
3340 if (r < 0) {
3341 DSSERR("request_irq failed\n");
3342 goto err_irq;
3343 }
3344
3345 pm_runtime_enable(&pdev->dev);
3346
3347 r = dispc_runtime_get();
3348 if (r)
3349 goto err_runtime_get;
3350
3351 _omap_dispc_initial_config();
3352
3353 _omap_dispc_initialize_irq();
3354
3355 rev = dispc_read_reg(DISPC_REVISION);
3356 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3357 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3358
3359 dispc_runtime_put();
3360
3361 return 0;
3362
3363 err_runtime_get:
3364 pm_runtime_disable(&pdev->dev);
3365 free_irq(dispc.irq, dispc.pdev);
3366 err_irq:
3367 iounmap(dispc.base);
3368 err_ioremap:
3369 clk_put(dispc.dss_clk);
3370 err_get_clk:
3371 return r;
3372 }
3373
3374 static int omap_dispchw_remove(struct platform_device *pdev)
3375 {
3376 pm_runtime_disable(&pdev->dev);
3377
3378 clk_put(dispc.dss_clk);
3379
3380 free_irq(dispc.irq, dispc.pdev);
3381 iounmap(dispc.base);
3382 return 0;
3383 }
3384
3385 static int dispc_runtime_suspend(struct device *dev)
3386 {
3387 dispc_save_context();
3388 dss_runtime_put();
3389
3390 return 0;
3391 }
3392
3393 static int dispc_runtime_resume(struct device *dev)
3394 {
3395 int r;
3396
3397 r = dss_runtime_get();
3398 if (r < 0)
3399 return r;
3400
3401 dispc_restore_context();
3402
3403 return 0;
3404 }
3405
3406 static const struct dev_pm_ops dispc_pm_ops = {
3407 .runtime_suspend = dispc_runtime_suspend,
3408 .runtime_resume = dispc_runtime_resume,
3409 };
3410
3411 static struct platform_driver omap_dispchw_driver = {
3412 .probe = omap_dispchw_probe,
3413 .remove = omap_dispchw_remove,
3414 .driver = {
3415 .name = "omapdss_dispc",
3416 .owner = THIS_MODULE,
3417 .pm = &dispc_pm_ops,
3418 },
3419 };
3420
3421 int dispc_init_platform_driver(void)
3422 {
3423 return platform_driver_register(&omap_dispchw_driver);
3424 }
3425
3426 void dispc_uninit_platform_driver(void)
3427 {
3428 return platform_driver_unregister(&omap_dispchw_driver);
3429 }