drivers/video/omap2/dss/dispc.h

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.h
   3  *
   4  * Copyright (C) 2011 Texas Instruments
   5  * Author: Archit Taneja <archit@ti.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License version 2 as published by
  10  * the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef __OMAP2_DISPC_REG_H
  22 #define __OMAP2_DISPC_REG_H
  23
  24 /* DISPC common registers */
  25 #define DISPC_REVISION                  0x0000
  26 #define DISPC_SYSCONFIG                 0x0010
  27 #define DISPC_SYSSTATUS                 0x0014
  28 #define DISPC_IRQSTATUS                 0x0018
  29 #define DISPC_IRQENABLE                 0x001C
  30 #define DISPC_CONTROL                   0x0040
  31 #define DISPC_CONFIG                    0x0044
  32 #define DISPC_CAPABLE                   0x0048
  33 #define DISPC_LINE_STATUS               0x005C
  34 #define DISPC_LINE_NUMBER               0x0060
  35 #define DISPC_GLOBAL_ALPHA              0x0074
  36 #define DISPC_CONTROL2                  0x0238
  37 #define DISPC_CONFIG2                   0x0620
  38 #define DISPC_DIVISOR                   0x0804
  39
  40 /* DISPC overlay registers */
  41 #define DISPC_OVL_BA0(n)                (DISPC_OVL_BASE(n) + \
  42                                         DISPC_BA0_OFFSET(n))
  43 #define DISPC_OVL_BA1(n)                (DISPC_OVL_BASE(n) + \
  44                                         DISPC_BA1_OFFSET(n))
  45 #define DISPC_OVL_BA0_UV(n)             (DISPC_OVL_BASE(n) + \
  46                                         DISPC_BA0_UV_OFFSET(n))
  47 #define DISPC_OVL_BA1_UV(n)             (DISPC_OVL_BASE(n) + \
  48                                         DISPC_BA1_UV_OFFSET(n))
  49 #define DISPC_OVL_POSITION(n)           (DISPC_OVL_BASE(n) + \
  50                                         DISPC_POS_OFFSET(n))
  51 #define DISPC_OVL_SIZE(n)               (DISPC_OVL_BASE(n) + \
  52                                         DISPC_SIZE_OFFSET(n))
  53 #define DISPC_OVL_ATTRIBUTES(n)         (DISPC_OVL_BASE(n) + \
  54                                         DISPC_ATTR_OFFSET(n))
  55 #define DISPC_OVL_ATTRIBUTES2(n)        (DISPC_OVL_BASE(n) + \
  56                                         DISPC_ATTR2_OFFSET(n))
  57 #define DISPC_OVL_FIFO_THRESHOLD(n)     (DISPC_OVL_BASE(n) + \
  58                                         DISPC_FIFO_THRESH_OFFSET(n))
  59 #define DISPC_OVL_FIFO_SIZE_STATUS(n)   (DISPC_OVL_BASE(n) + \
  60                                         DISPC_FIFO_SIZE_STATUS_OFFSET(n))
  61 #define DISPC_OVL_ROW_INC(n)            (DISPC_OVL_BASE(n) + \
  62                                         DISPC_ROW_INC_OFFSET(n))
  63 #define DISPC_OVL_PIXEL_INC(n)          (DISPC_OVL_BASE(n) + \
  64                                         DISPC_PIX_INC_OFFSET(n))
  65 #define DISPC_OVL_WINDOW_SKIP(n)        (DISPC_OVL_BASE(n) + \
  66                                         DISPC_WINDOW_SKIP_OFFSET(n))
  67 #define DISPC_OVL_TABLE_BA(n)           (DISPC_OVL_BASE(n) + \
  68                                         DISPC_TABLE_BA_OFFSET(n))
  69 #define DISPC_OVL_FIR(n)                (DISPC_OVL_BASE(n) + \
  70                                         DISPC_FIR_OFFSET(n))
  71 #define DISPC_OVL_FIR2(n)               (DISPC_OVL_BASE(n) + \
  72                                         DISPC_FIR2_OFFSET(n))
  73 #define DISPC_OVL_PICTURE_SIZE(n)       (DISPC_OVL_BASE(n) + \
  74                                         DISPC_PIC_SIZE_OFFSET(n))
  75 #define DISPC_OVL_ACCU0(n)              (DISPC_OVL_BASE(n) + \
  76                                         DISPC_ACCU0_OFFSET(n))
  77 #define DISPC_OVL_ACCU1(n)              (DISPC_OVL_BASE(n) + \
  78                                         DISPC_ACCU1_OFFSET(n))
  79 #define DISPC_OVL_ACCU2_0(n)            (DISPC_OVL_BASE(n) + \
  80                                         DISPC_ACCU2_0_OFFSET(n))
  81 #define DISPC_OVL_ACCU2_1(n)            (DISPC_OVL_BASE(n) + \
  82                                         DISPC_ACCU2_1_OFFSET(n))
  83 #define DISPC_OVL_FIR_COEF_H(n, i)      (DISPC_OVL_BASE(n) + \
  84                                         DISPC_FIR_COEF_H_OFFSET(n, i))
  85 #define DISPC_OVL_FIR_COEF_HV(n, i)     (DISPC_OVL_BASE(n) + \
  86                                         DISPC_FIR_COEF_HV_OFFSET(n, i))
  87 #define DISPC_OVL_FIR_COEF_H2(n, i)     (DISPC_OVL_BASE(n) + \
  88                                         DISPC_FIR_COEF_H2_OFFSET(n, i))
  89 #define DISPC_OVL_FIR_COEF_HV2(n, i)    (DISPC_OVL_BASE(n) + \
  90                                         DISPC_FIR_COEF_HV2_OFFSET(n, i))
  91 #define DISPC_OVL_CONV_COEF(n, i)       (DISPC_OVL_BASE(n) + \
  92                                         DISPC_CONV_COEF_OFFSET(n, i))
  93 #define DISPC_OVL_FIR_COEF_V(n, i)      (DISPC_OVL_BASE(n) + \
  94                                         DISPC_FIR_COEF_V_OFFSET(n, i))
  95 #define DISPC_OVL_FIR_COEF_V2(n, i)     (DISPC_OVL_BASE(n) + \
  96                                         DISPC_FIR_COEF_V2_OFFSET(n, i))
  97 #define DISPC_OVL_PRELOAD(n)            (DISPC_OVL_BASE(n) + \
  98                                         DISPC_PRELOAD_OFFSET(n))
  99
 100 /* DISPC up/downsampling FIR filter coefficient structure */
 101 struct dispc_coef {
 102         s8 hc4_vc22;
 103         s8 hc3_vc2;
 104         u8 hc2_vc1;
 105         s8 hc1_vc0;
 106         s8 hc0_vc00;
 107 };
 108
 109 const struct dispc_coef *dispc_ovl_get_scale_coef(int inc, int five_taps);
 110
 111 /* DISPC manager/channel specific registers */
 112 static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
 113 {
 114         switch (channel) {
 115         case OMAP_DSS_CHANNEL_LCD:
 116                 return 0x004C;
 117         case OMAP_DSS_CHANNEL_DIGIT:
 118                 return 0x0050;
 119         case OMAP_DSS_CHANNEL_LCD2:
 120                 return 0x03AC;
 121         default:
 122                 BUG();
 123         }
 124 }
 125
 126 static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
 127 {
 128         switch (channel) {
 129         case OMAP_DSS_CHANNEL_LCD:
 130                 return 0x0054;
 131         case OMAP_DSS_CHANNEL_DIGIT:
 132                 return 0x0058;
 133         case OMAP_DSS_CHANNEL_LCD2:
 134                 return 0x03B0;
 135         default:
 136                 BUG();
 137         }
 138 }
 139
 140 static inline u16 DISPC_TIMING_H(enum omap_channel channel)
 141 {
 142         switch (channel) {
 143         case OMAP_DSS_CHANNEL_LCD:
 144                 return 0x0064;
 145         case OMAP_DSS_CHANNEL_DIGIT:
 146                 BUG();
 147         case OMAP_DSS_CHANNEL_LCD2:
 148                 return 0x0400;
 149         default:
 150                 BUG();
 151         }
 152 }
 153
 154 static inline u16 DISPC_TIMING_V(enum omap_channel channel)
 155 {
 156         switch (channel) {
 157         case OMAP_DSS_CHANNEL_LCD:
 158                 return 0x0068;
 159         case OMAP_DSS_CHANNEL_DIGIT:
 160                 BUG();
 161         case OMAP_DSS_CHANNEL_LCD2:
 162                 return 0x0404;
 163         default:
 164                 BUG();
 165         }
 166 }
 167
 168 static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
 169 {
 170         switch (channel) {
 171         case OMAP_DSS_CHANNEL_LCD:
 172                 return 0x006C;
 173         case OMAP_DSS_CHANNEL_DIGIT:
 174                 BUG();
 175         case OMAP_DSS_CHANNEL_LCD2:
 176                 return 0x0408;
 177         default:
 178                 BUG();
 179         }
 180 }
 181
 182 static inline u16 DISPC_DIVISORo(enum omap_channel channel)
 183 {
 184         switch (channel) {
 185         case OMAP_DSS_CHANNEL_LCD:
 186                 return 0x0070;
 187         case OMAP_DSS_CHANNEL_DIGIT:
 188                 BUG();
 189         case OMAP_DSS_CHANNEL_LCD2:
 190                 return 0x040C;
 191         default:
 192                 BUG();
 193         }
 194 }
 195
 196 /* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
 197 static inline u16 DISPC_SIZE_MGR(enum omap_channel channel)
 198 {
 199         switch (channel) {
 200         case OMAP_DSS_CHANNEL_LCD:
 201                 return 0x007C;
 202         case OMAP_DSS_CHANNEL_DIGIT:
 203                 return 0x0078;
 204         case OMAP_DSS_CHANNEL_LCD2:
 205                 return 0x03CC;
 206         default:
 207                 BUG();
 208         }
 209 }
 210
 211 static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel)
 212 {
 213         switch (channel) {
 214         case OMAP_DSS_CHANNEL_LCD:
 215                 return 0x01D4;
 216         case OMAP_DSS_CHANNEL_DIGIT:
 217                 BUG();
 218         case OMAP_DSS_CHANNEL_LCD2:
 219                 return 0x03C0;
 220         default:
 221                 BUG();
 222         }
 223 }
 224
 225 static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel)
 226 {
 227         switch (channel) {
 228         case OMAP_DSS_CHANNEL_LCD:
 229                 return 0x01D8;
 230         case OMAP_DSS_CHANNEL_DIGIT:
 231                 BUG();
 232         case OMAP_DSS_CHANNEL_LCD2:
 233                 return 0x03C4;
 234         default:
 235                 BUG();
 236         }
 237 }
 238
 239 static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel)
 240 {
 241         switch (channel) {
 242         case OMAP_DSS_CHANNEL_LCD:
 243                 return 0x01DC;
 244         case OMAP_DSS_CHANNEL_DIGIT:
 245                 BUG();
 246         case OMAP_DSS_CHANNEL_LCD2:
 247                 return 0x03C8;
 248         default:
 249                 BUG();
 250         }
 251 }
 252
 253 static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel)
 254 {
 255         switch (channel) {
 256         case OMAP_DSS_CHANNEL_LCD:
 257                 return 0x0220;
 258         case OMAP_DSS_CHANNEL_DIGIT:
 259                 BUG();
 260         case OMAP_DSS_CHANNEL_LCD2:
 261                 return 0x03BC;
 262         default:
 263                 BUG();
 264         }
 265 }
 266
 267 static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel)
 268 {
 269         switch (channel) {
 270         case OMAP_DSS_CHANNEL_LCD:
 271                 return 0x0224;
 272         case OMAP_DSS_CHANNEL_DIGIT:
 273                 BUG();
 274         case OMAP_DSS_CHANNEL_LCD2:
 275                 return 0x03B8;
 276         default:
 277                 BUG();
 278         }
 279 }
 280
 281 static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
 282 {
 283         switch (channel) {
 284         case OMAP_DSS_CHANNEL_LCD:
 285                 return 0x0228;
 286         case OMAP_DSS_CHANNEL_DIGIT:
 287                 BUG();
 288         case OMAP_DSS_CHANNEL_LCD2:
 289                 return 0x03B4;
 290         default:
 291                 BUG();
 292         }
 293 }
 294
 295 /* DISPC overlay register base addresses */
 296 static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
 297 {
 298         switch (plane) {
 299         case OMAP_DSS_GFX:
 300                 return 0x0080;
 301         case OMAP_DSS_VIDEO1:
 302                 return 0x00BC;
 303         case OMAP_DSS_VIDEO2:
 304                 return 0x014C;
 305         case OMAP_DSS_VIDEO3:
 306                 return 0x0300;
 307         default:
 308                 BUG();
 309         }
 310 }
 311
 312 /* DISPC overlay register offsets */
 313 static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane)
 314 {
 315         switch (plane) {
 316         case OMAP_DSS_GFX:
 317         case OMAP_DSS_VIDEO1:
 318         case OMAP_DSS_VIDEO2:
 319                 return 0x0000;
 320         case OMAP_DSS_VIDEO3:
 321                 return 0x0008;
 322         default:
 323                 BUG();
 324         }
 325 }
 326
 327 static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
 328 {
 329         switch (plane) {
 330         case OMAP_DSS_GFX:
 331         case OMAP_DSS_VIDEO1:
 332         case OMAP_DSS_VIDEO2:
 333                 return 0x0004;
 334         case OMAP_DSS_VIDEO3:
 335                 return 0x000C;
 336         default:
 337                 BUG();
 338         }
 339 }
 340
 341 static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane)
 342 {
 343         switch (plane) {
 344         case OMAP_DSS_GFX:
 345                 BUG();
 346         case OMAP_DSS_VIDEO1:
 347                 return 0x0544;
 348         case OMAP_DSS_VIDEO2:
 349                 return 0x04BC;
 350         case OMAP_DSS_VIDEO3:
 351                 return 0x0310;
 352         default:
 353                 BUG();
 354         }
 355 }
 356
 357 static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane)
 358 {
 359         switch (plane) {
 360         case OMAP_DSS_GFX:
 361                 BUG();
 362         case OMAP_DSS_VIDEO1:
 363                 return 0x0548;
 364         case OMAP_DSS_VIDEO2:
 365                 return 0x04C0;
 366         case OMAP_DSS_VIDEO3:
 367                 return 0x0314;
 368         default:
 369                 BUG();
 370         }
 371 }
 372
 373 static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
 374 {
 375         switch (plane) {
 376         case OMAP_DSS_GFX:
 377         case OMAP_DSS_VIDEO1:
 378         case OMAP_DSS_VIDEO2:
 379                 return 0x0008;
 380         case OMAP_DSS_VIDEO3:
 381                 return 0x009C;
 382         default:
 383                 BUG();
 384         }
 385 }
 386
 387 static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane)
 388 {
 389         switch (plane) {
 390         case OMAP_DSS_GFX:
 391         case OMAP_DSS_VIDEO1:
 392         case OMAP_DSS_VIDEO2:
 393                 return 0x000C;
 394         case OMAP_DSS_VIDEO3:
 395                 return 0x00A8;
 396         default:
 397                 BUG();
 398         }
 399 }
 400
 401 static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
 402 {
 403         switch (plane) {
 404         case OMAP_DSS_GFX:
 405                 return 0x0020;
 406         case OMAP_DSS_VIDEO1:
 407         case OMAP_DSS_VIDEO2:
 408                 return 0x0010;
 409         case OMAP_DSS_VIDEO3:
 410                 return 0x0070;
 411         default:
 412                 BUG();
 413         }
 414 }
 415
 416 static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane)
 417 {
 418         switch (plane) {
 419         case OMAP_DSS_GFX:
 420                 BUG();
 421         case OMAP_DSS_VIDEO1:
 422                 return 0x0568;
 423         case OMAP_DSS_VIDEO2:
 424                 return 0x04DC;
 425         case OMAP_DSS_VIDEO3:
 426                 return 0x032C;
 427         default:
 428                 BUG();
 429         }
 430 }
 431
 432 static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
 433 {
 434         switch (plane) {
 435         case OMAP_DSS_GFX:
 436                 return 0x0024;
 437         case OMAP_DSS_VIDEO1:
 438         case OMAP_DSS_VIDEO2:
 439                 return 0x0014;
 440         case OMAP_DSS_VIDEO3:
 441                 return 0x008C;
 442         default:
 443                 BUG();
 444         }
 445 }
 446
 447 static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)
 448 {
 449         switch (plane) {
 450         case OMAP_DSS_GFX:
 451                 return 0x0028;
 452         case OMAP_DSS_VIDEO1:
 453         case OMAP_DSS_VIDEO2:
 454                 return 0x0018;
 455         case OMAP_DSS_VIDEO3:
 456                 return 0x0088;
 457         default:
 458                 BUG();
 459         }
 460 }
 461
 462 static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane)
 463 {
 464         switch (plane) {
 465         case OMAP_DSS_GFX:
 466                 return 0x002C;
 467         case OMAP_DSS_VIDEO1:
 468         case OMAP_DSS_VIDEO2:
 469                 return 0x001C;
 470         case OMAP_DSS_VIDEO3:
 471                 return 0x00A4;
 472         default:
 473                 BUG();
 474         }
 475 }
 476
 477 static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane)
 478 {
 479         switch (plane) {
 480         case OMAP_DSS_GFX:
 481                 return 0x0030;
 482         case OMAP_DSS_VIDEO1:
 483         case OMAP_DSS_VIDEO2:
 484                 return 0x0020;
 485         case OMAP_DSS_VIDEO3:
 486                 return 0x0098;
 487         default:
 488                 BUG();
 489         }
 490 }
 491
 492 static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)
 493 {
 494         switch (plane) {
 495         case OMAP_DSS_GFX:
 496                 return 0x0034;
 497         case OMAP_DSS_VIDEO1:
 498         case OMAP_DSS_VIDEO2:
 499         case OMAP_DSS_VIDEO3:
 500                 BUG();
 501         default:
 502                 BUG();
 503         }
 504 }
 505
 506 static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane)
 507 {
 508         switch (plane) {
 509         case OMAP_DSS_GFX:
 510                 return 0x0038;
 511         case OMAP_DSS_VIDEO1:
 512         case OMAP_DSS_VIDEO2:
 513         case OMAP_DSS_VIDEO3:
 514                 BUG();
 515         default:
 516                 BUG();
 517         }
 518 }
 519
 520 static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
 521 {
 522         switch (plane) {
 523         case OMAP_DSS_GFX:
 524                 BUG();
 525         case OMAP_DSS_VIDEO1:
 526         case OMAP_DSS_VIDEO2:
 527                 return 0x0024;
 528         case OMAP_DSS_VIDEO3:
 529                 return 0x0090;
 530         default:
 531                 BUG();
 532         }
 533 }
 534
 535 static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane)
 536 {
 537         switch (plane) {
 538         case OMAP_DSS_GFX:
 539                 BUG();
 540         case OMAP_DSS_VIDEO1:
 541                 return 0x0580;
 542         case OMAP_DSS_VIDEO2:
 543                 return 0x055C;
 544         case OMAP_DSS_VIDEO3:
 545                 return 0x0424;
 546         default:
 547                 BUG();
 548         }
 549 }
 550
 551 static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
 552 {
 553         switch (plane) {
 554         case OMAP_DSS_GFX:
 555                 BUG();
 556         case OMAP_DSS_VIDEO1:
 557         case OMAP_DSS_VIDEO2:
 558                 return 0x0028;
 559         case OMAP_DSS_VIDEO3:
 560                 return 0x0094;
 561         default:
 562                 BUG();
 563         }
 564 }
 565
 566
 567 static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
 568 {
 569         switch (plane) {
 570         case OMAP_DSS_GFX:
 571                 BUG();
 572         case OMAP_DSS_VIDEO1:
 573         case OMAP_DSS_VIDEO2:
 574                 return 0x002C;
 575         case OMAP_DSS_VIDEO3:
 576                 return 0x0000;
 577         default:
 578                 BUG();
 579         }
 580 }
 581
 582 static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane)
 583 {
 584         switch (plane) {
 585         case OMAP_DSS_GFX:
 586                 BUG();
 587         case OMAP_DSS_VIDEO1:
 588                 return 0x0584;
 589         case OMAP_DSS_VIDEO2:
 590                 return 0x0560;
 591         case OMAP_DSS_VIDEO3:
 592                 return 0x0428;
 593         default:
 594                 BUG();
 595         }
 596 }
 597
 598 static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
 599 {
 600         switch (plane) {
 601         case OMAP_DSS_GFX:
 602                 BUG();
 603         case OMAP_DSS_VIDEO1:
 604         case OMAP_DSS_VIDEO2:
 605                 return 0x0030;
 606         case OMAP_DSS_VIDEO3:
 607                 return 0x0004;
 608         default:
 609                 BUG();
 610         }
 611 }
 612
 613 static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane)
 614 {
 615         switch (plane) {
 616         case OMAP_DSS_GFX:
 617                 BUG();
 618         case OMAP_DSS_VIDEO1:
 619                 return 0x0588;
 620         case OMAP_DSS_VIDEO2:
 621                 return 0x0564;
 622         case OMAP_DSS_VIDEO3:
 623                 return 0x042C;
 624         default:
 625                 BUG();
 626         }
 627 }
 628
 629 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 630 static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
 631 {
 632         switch (plane) {
 633         case OMAP_DSS_GFX:
 634                 BUG();
 635         case OMAP_DSS_VIDEO1:
 636         case OMAP_DSS_VIDEO2:
 637                 return 0x0034 + i * 0x8;
 638         case OMAP_DSS_VIDEO3:
 639                 return 0x0010 + i * 0x8;
 640         default:
 641                 BUG();
 642         }
 643 }
 644
 645 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 646 static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i)
 647 {
 648         switch (plane) {
 649         case OMAP_DSS_GFX:
 650                 BUG();
 651         case OMAP_DSS_VIDEO1:
 652                 return 0x058C + i * 0x8;
 653         case OMAP_DSS_VIDEO2:
 654                 return 0x0568 + i * 0x8;
 655         case OMAP_DSS_VIDEO3:
 656                 return 0x0430 + i * 0x8;
 657         default:
 658                 BUG();
 659         }
 660 }
 661
 662 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 663 static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
 664 {
 665         switch (plane) {
 666         case OMAP_DSS_GFX:
 667                 BUG();
 668         case OMAP_DSS_VIDEO1:
 669         case OMAP_DSS_VIDEO2:
 670                 return 0x0038 + i * 0x8;
 671         case OMAP_DSS_VIDEO3:
 672                 return 0x0014 + i * 0x8;
 673         default:
 674                 BUG();
 675         }
 676 }
 677
 678 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 679 static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i)
 680 {
 681         switch (plane) {
 682         case OMAP_DSS_GFX:
 683                 BUG();
 684         case OMAP_DSS_VIDEO1:
 685                 return 0x0590 + i * 8;
 686         case OMAP_DSS_VIDEO2:
 687                 return 0x056C + i * 0x8;
 688         case OMAP_DSS_VIDEO3:
 689                 return 0x0434 + i * 0x8;
 690         default:
 691                 BUG();
 692         }
 693 }
 694
 695 /* coef index i = {0, 1, 2, 3, 4,} */
 696 static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
 697 {
 698         switch (plane) {
 699         case OMAP_DSS_GFX:
 700                 BUG();
 701         case OMAP_DSS_VIDEO1:
 702         case OMAP_DSS_VIDEO2:
 703         case OMAP_DSS_VIDEO3:
 704                 return 0x0074 + i * 0x4;
 705         default:
 706                 BUG();
 707         }
 708 }
 709
 710 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 711 static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
 712 {
 713         switch (plane) {
 714         case OMAP_DSS_GFX:
 715                 BUG();
 716         case OMAP_DSS_VIDEO1:
 717                 return 0x0124 + i * 0x4;
 718         case OMAP_DSS_VIDEO2:
 719                 return 0x00B4 + i * 0x4;
 720         case OMAP_DSS_VIDEO3:
 721                 return 0x0050 + i * 0x4;
 722         default:
 723                 BUG();
 724         }
 725 }
 726
 727 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 728 static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i)
 729 {
 730         switch (plane) {
 731         case OMAP_DSS_GFX:
 732                 BUG();
 733         case OMAP_DSS_VIDEO1:
 734                 return 0x05CC + i * 0x4;
 735         case OMAP_DSS_VIDEO2:
 736                 return 0x05A8 + i * 0x4;
 737         case OMAP_DSS_VIDEO3:
 738                 return 0x0470 + i * 0x4;
 739         default:
 740                 BUG();
 741         }
 742 }
 743
 744 static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
 745 {
 746         switch (plane) {
 747         case OMAP_DSS_GFX:
 748                 return 0x01AC;
 749         case OMAP_DSS_VIDEO1:
 750                 return 0x0174;
 751         case OMAP_DSS_VIDEO2:
 752                 return 0x00E8;
 753         case OMAP_DSS_VIDEO3:
 754                 return 0x00A0;
 755         default:
 756                 BUG();
 757         }
 758 }
 759 #endif