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Avoid beyond bounds copy while caching ACL
[zen-stable.git] / drivers / video / omap2 / dss / ti_hdmi_4xxx_ip.c
blob6847a478b4598d76138b9a331e92d5d0f0239d5c
1 /*
2 * ti_hdmi_4xxx_ip.c
3 *
4 * HDMI TI81xx, TI38xx, TI OMAP4 etc IP driver Library
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/err.h>
25 #include <linux/io.h>
26 #include <linux/interrupt.h>
27 #include <linux/mutex.h>
28 #include <linux/delay.h>
29 #include <linux/string.h>
30 #include <linux/seq_file.h>
31 #include <linux/gpio.h>
32
33 #include "ti_hdmi_4xxx_ip.h"
34 #include "dss.h"
35
36 static inline void hdmi_write_reg(void __iomem *base_addr,
37 const u16 idx, u32 val)
38 {
39 __raw_writel(val, base_addr + idx);
40 }
41
42 static inline u32 hdmi_read_reg(void __iomem *base_addr,
43 const u16 idx)
44 {
45 return __raw_readl(base_addr + idx);
46 }
47
48 static inline void __iomem *hdmi_wp_base(struct hdmi_ip_data *ip_data)
49 {
50 return ip_data->base_wp;
51 }
52
53 static inline void __iomem *hdmi_phy_base(struct hdmi_ip_data *ip_data)
54 {
55 return ip_data->base_wp + ip_data->phy_offset;
56 }
57
58 static inline void __iomem *hdmi_pll_base(struct hdmi_ip_data *ip_data)
59 {
60 return ip_data->base_wp + ip_data->pll_offset;
61 }
62
63 static inline void __iomem *hdmi_av_base(struct hdmi_ip_data *ip_data)
64 {
65 return ip_data->base_wp + ip_data->core_av_offset;
66 }
67
68 static inline void __iomem *hdmi_core_sys_base(struct hdmi_ip_data *ip_data)
69 {
70 return ip_data->base_wp + ip_data->core_sys_offset;
71 }
72
73 static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
74 const u16 idx,
75 int b2, int b1, u32 val)
76 {
77 u32 t = 0;
78 while (val != REG_GET(base_addr, idx, b2, b1)) {
79 udelay(1);
80 if (t++ > 10000)
81 return !val;
82 }
83 return val;
84 }
85
86 static int hdmi_pll_init(struct hdmi_ip_data *ip_data)
87 {
88 u32 r;
89 void __iomem *pll_base = hdmi_pll_base(ip_data);
90 struct hdmi_pll_info *fmt = &ip_data->pll_data;
91
92 /* PLL start always use manual mode */
93 REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
94
95 r = hdmi_read_reg(pll_base, PLLCTRL_CFG1);
96 r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
97 r = FLD_MOD(r, fmt->regn - 1, 8, 1); /* CFG1_PLL_REGN */
98
99 hdmi_write_reg(pll_base, PLLCTRL_CFG1, r);
100
101 r = hdmi_read_reg(pll_base, PLLCTRL_CFG2);
102
103 r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
104 r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
105 r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
106 r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */
107
108 if (fmt->dcofreq) {
109 /* divider programming for frequency beyond 1000Mhz */
110 REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
111 r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
112 } else {
113 r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
114 }
115
116 hdmi_write_reg(pll_base, PLLCTRL_CFG2, r);
117
118 r = hdmi_read_reg(pll_base, PLLCTRL_CFG4);
119 r = FLD_MOD(r, fmt->regm2, 24, 18);
120 r = FLD_MOD(r, fmt->regmf, 17, 0);
121
122 hdmi_write_reg(pll_base, PLLCTRL_CFG4, r);
123
124 /* go now */
125 REG_FLD_MOD(pll_base, PLLCTRL_PLL_GO, 0x1, 0, 0);
126
127 /* wait for bit change */
128 if (hdmi_wait_for_bit_change(pll_base, PLLCTRL_PLL_GO,
129 0, 0, 1) != 1) {
130 pr_err("PLL GO bit not set\n");
131 return -ETIMEDOUT;
132 }
133
134 /* Wait till the lock bit is set in PLL status */
135 if (hdmi_wait_for_bit_change(pll_base,
136 PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) {
137 pr_err("cannot lock PLL\n");
138 pr_err("CFG1 0x%x\n",
139 hdmi_read_reg(pll_base, PLLCTRL_CFG1));
140 pr_err("CFG2 0x%x\n",
141 hdmi_read_reg(pll_base, PLLCTRL_CFG2));
142 pr_err("CFG4 0x%x\n",
143 hdmi_read_reg(pll_base, PLLCTRL_CFG4));
144 return -ETIMEDOUT;
145 }
146
147 pr_debug("PLL locked!\n");
148
149 return 0;
150 }
151
152 /* PHY_PWR_CMD */
153 static int hdmi_set_phy_pwr(struct hdmi_ip_data *ip_data, enum hdmi_phy_pwr val)
154 {
155 /* Command for power control of HDMI PHY */
156 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 7, 6);
157
158 /* Status of the power control of HDMI PHY */
159 if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data),
160 HDMI_WP_PWR_CTRL, 5, 4, val) != val) {
161 pr_err("Failed to set PHY power mode to %d\n", val);
162 return -ETIMEDOUT;
163 }
164
165 return 0;
166 }
167
168 /* PLL_PWR_CMD */
169 static int hdmi_set_pll_pwr(struct hdmi_ip_data *ip_data, enum hdmi_pll_pwr val)
170 {
171 /* Command for power control of HDMI PLL */
172 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 3, 2);
173
174 /* wait till PHY_PWR_STATUS is set */
175 if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL,
176 1, 0, val) != val) {
177 pr_err("Failed to set PLL_PWR_STATUS\n");
178 return -ETIMEDOUT;
179 }
180
181 return 0;
182 }
183
184 static int hdmi_pll_reset(struct hdmi_ip_data *ip_data)
185 {
186 /* SYSRESET controlled by power FSM */
187 REG_FLD_MOD(hdmi_pll_base(ip_data), PLLCTRL_PLL_CONTROL, 0x0, 3, 3);
188
189 /* READ 0x0 reset is in progress */
190 if (hdmi_wait_for_bit_change(hdmi_pll_base(ip_data),
191 PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) {
192 pr_err("Failed to sysreset PLL\n");
193 return -ETIMEDOUT;
194 }
195
196 return 0;
197 }
198
199 int ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data *ip_data)
200 {
201 u16 r = 0;
202
203 r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
204 if (r)
205 return r;
206
207 r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
208 if (r)
209 return r;
210
211 r = hdmi_pll_reset(ip_data);
212 if (r)
213 return r;
214
215 r = hdmi_pll_init(ip_data);
216 if (r)
217 return r;
218
219 return 0;
220 }
221
222 void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data)
223 {
224 hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
225 }
226
227 static int hdmi_check_hpd_state(struct hdmi_ip_data *ip_data)
228 {
229 unsigned long flags;
230 bool hpd;
231 int r;
232 /* this should be in ti_hdmi_4xxx_ip private data */
233 static DEFINE_SPINLOCK(phy_tx_lock);
234
235 spin_lock_irqsave(&phy_tx_lock, flags);
236
237 hpd = gpio_get_value(ip_data->hpd_gpio);
238
239 if (hpd == ip_data->phy_tx_enabled) {
240 spin_unlock_irqrestore(&phy_tx_lock, flags);
241 return 0;
242 }
243
244 if (hpd)
245 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_TXON);
246 else
247 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON);
248
249 if (r) {
250 DSSERR("Failed to %s PHY TX power\n",
251 hpd ? "enable" : "disable");
252 goto err;
253 }
254
255 ip_data->phy_tx_enabled = hpd;
256 err:
257 spin_unlock_irqrestore(&phy_tx_lock, flags);
258 return r;
259 }
260
261 static irqreturn_t hpd_irq_handler(int irq, void *data)
262 {
263 struct hdmi_ip_data *ip_data = data;
264
265 hdmi_check_hpd_state(ip_data);
266
267 return IRQ_HANDLED;
268 }
269
270 int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data)
271 {
272 u16 r = 0;
273 void __iomem *phy_base = hdmi_phy_base(ip_data);
274
275 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON);
276 if (r)
277 return r;
278
279 /*
280 * Read address 0 in order to get the SCP reset done completed
281 * Dummy access performed to make sure reset is done
282 */
283 hdmi_read_reg(phy_base, HDMI_TXPHY_TX_CTRL);
284
285 /*
286 * Write to phy address 0 to configure the clock
287 * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field
288 */
289 REG_FLD_MOD(phy_base, HDMI_TXPHY_TX_CTRL, 0x1, 31, 30);
290
291 /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
292 hdmi_write_reg(phy_base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000);
293
294 /* Setup max LDO voltage */
295 REG_FLD_MOD(phy_base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
296
297 /* Write to phy address 3 to change the polarity control */
298 REG_FLD_MOD(phy_base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27);
299
300 r = request_threaded_irq(gpio_to_irq(ip_data->hpd_gpio),
301 NULL, hpd_irq_handler,
302 IRQF_DISABLED | IRQF_TRIGGER_RISING |
303 IRQF_TRIGGER_FALLING, "hpd", ip_data);
304 if (r) {
305 DSSERR("HPD IRQ request failed\n");
306 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
307 return r;
308 }
309
310 r = hdmi_check_hpd_state(ip_data);
311 if (r) {
312 free_irq(gpio_to_irq(ip_data->hpd_gpio), ip_data);
313 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
314 return r;
315 }
316
317 return 0;
318 }
319
320 void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data)
321 {
322 free_irq(gpio_to_irq(ip_data->hpd_gpio), ip_data);
323
324 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
325 ip_data->phy_tx_enabled = false;
326 }
327
328 static int hdmi_core_ddc_init(struct hdmi_ip_data *ip_data)
329 {
330 void __iomem *base = hdmi_core_sys_base(ip_data);
331
332 /* Turn on CLK for DDC */
333 REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0);
334
335 /* IN_PROG */
336 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) {
337 /* Abort transaction */
338 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0);
339 /* IN_PROG */
340 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
341 4, 4, 0) != 0) {
342 DSSERR("Timeout aborting DDC transaction\n");
343 return -ETIMEDOUT;
344 }
345 }
346
347 /* Clk SCL Devices */
348 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0);
349
350 /* HDMI_CORE_DDC_STATUS_IN_PROG */
351 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
352 4, 4, 0) != 0) {
353 DSSERR("Timeout starting SCL clock\n");
354 return -ETIMEDOUT;
355 }
356
357 /* Clear FIFO */
358 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0);
359
360 /* HDMI_CORE_DDC_STATUS_IN_PROG */
361 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
362 4, 4, 0) != 0) {
363 DSSERR("Timeout clearing DDC fifo\n");
364 return -ETIMEDOUT;
365 }
366
367 return 0;
368 }
369
370 static int hdmi_core_ddc_edid(struct hdmi_ip_data *ip_data,
371 u8 *pedid, int ext)
372 {
373 void __iomem *base = hdmi_core_sys_base(ip_data);
374 u32 i;
375 char checksum;
376 u32 offset = 0;
377
378 /* HDMI_CORE_DDC_STATUS_IN_PROG */
379 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
380 4, 4, 0) != 0) {
381 DSSERR("Timeout waiting DDC to be ready\n");
382 return -ETIMEDOUT;
383 }
384
385 if (ext % 2 != 0)
386 offset = 0x80;
387
388 /* Load Segment Address Register */
389 REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0);
390
391 /* Load Slave Address Register */
392 REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
393
394 /* Load Offset Address Register */
395 REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0);
396
397 /* Load Byte Count */
398 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0);
399 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0);
400
401 /* Set DDC_CMD */
402 if (ext)
403 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0);
404 else
405 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x2, 3, 0);
406
407 /* HDMI_CORE_DDC_STATUS_BUS_LOW */
408 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) {
409 pr_err("I2C Bus Low?\n");
410 return -EIO;
411 }
412 /* HDMI_CORE_DDC_STATUS_NO_ACK */
413 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) {
414 pr_err("I2C No Ack\n");
415 return -EIO;
416 }
417
418 for (i = 0; i < 0x80; ++i) {
419 int t;
420
421 /* IN_PROG */
422 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) {
423 DSSERR("operation stopped when reading edid\n");
424 return -EIO;
425 }
426
427 t = 0;
428 /* FIFO_EMPTY */
429 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) {
430 if (t++ > 10000) {
431 DSSERR("timeout reading edid\n");
432 return -ETIMEDOUT;
433 }
434 udelay(1);
435 }
436
437 pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0);
438 }
439
440 checksum = 0;
441 for (i = 0; i < 0x80; ++i)
442 checksum += pedid[i];
443
444 if (checksum != 0) {
445 pr_err("E-EDID checksum failed!!\n");
446 return -EIO;
447 }
448
449 return 0;
450 }
451
452 int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data,
453 u8 *edid, int len)
454 {
455 int r, l;
456
457 if (len < 128)
458 return -EINVAL;
459
460 r = hdmi_core_ddc_init(ip_data);
461 if (r)
462 return r;
463
464 r = hdmi_core_ddc_edid(ip_data, edid, 0);
465 if (r)
466 return r;
467
468 l = 128;
469
470 if (len >= 128 * 2 && edid[0x7e] > 0) {
471 r = hdmi_core_ddc_edid(ip_data, edid + 0x80, 1);
472 if (r)
473 return r;
474 l += 128;
475 }
476
477 return l;
478 }
479
480 bool ti_hdmi_4xxx_detect(struct hdmi_ip_data *ip_data)
481 {
482 return gpio_get_value(ip_data->hpd_gpio);
483 }
484
485 static void hdmi_core_init(struct hdmi_core_video_config *video_cfg,
486 struct hdmi_core_infoframe_avi *avi_cfg,
487 struct hdmi_core_packet_enable_repeat *repeat_cfg)
488 {
489 pr_debug("Enter hdmi_core_init\n");
490
491 /* video core */
492 video_cfg->ip_bus_width = HDMI_INPUT_8BIT;
493 video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT;
494 video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE;
495 video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE;
496 video_cfg->hdmi_dvi = HDMI_DVI;
497 video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK;
498
499 /* info frame */
500 avi_cfg->db1_format = 0;
501 avi_cfg->db1_active_info = 0;
502 avi_cfg->db1_bar_info_dv = 0;
503 avi_cfg->db1_scan_info = 0;
504 avi_cfg->db2_colorimetry = 0;
505 avi_cfg->db2_aspect_ratio = 0;
506 avi_cfg->db2_active_fmt_ar = 0;
507 avi_cfg->db3_itc = 0;
508 avi_cfg->db3_ec = 0;
509 avi_cfg->db3_q_range = 0;
510 avi_cfg->db3_nup_scaling = 0;
511 avi_cfg->db4_videocode = 0;
512 avi_cfg->db5_pixel_repeat = 0;
513 avi_cfg->db6_7_line_eoftop = 0 ;
514 avi_cfg->db8_9_line_sofbottom = 0;
515 avi_cfg->db10_11_pixel_eofleft = 0;
516 avi_cfg->db12_13_pixel_sofright = 0;
517
518 /* packet enable and repeat */
519 repeat_cfg->audio_pkt = 0;
520 repeat_cfg->audio_pkt_repeat = 0;
521 repeat_cfg->avi_infoframe = 0;
522 repeat_cfg->avi_infoframe_repeat = 0;
523 repeat_cfg->gen_cntrl_pkt = 0;
524 repeat_cfg->gen_cntrl_pkt_repeat = 0;
525 repeat_cfg->generic_pkt = 0;
526 repeat_cfg->generic_pkt_repeat = 0;
527 }
528
529 static void hdmi_core_powerdown_disable(struct hdmi_ip_data *ip_data)
530 {
531 pr_debug("Enter hdmi_core_powerdown_disable\n");
532 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_CTRL1, 0x0, 0, 0);
533 }
534
535 static void hdmi_core_swreset_release(struct hdmi_ip_data *ip_data)
536 {
537 pr_debug("Enter hdmi_core_swreset_release\n");
538 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x0, 0, 0);
539 }
540
541 static void hdmi_core_swreset_assert(struct hdmi_ip_data *ip_data)
542 {
543 pr_debug("Enter hdmi_core_swreset_assert\n");
544 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x1, 0, 0);
545 }
546
547 /* HDMI_CORE_VIDEO_CONFIG */
548 static void hdmi_core_video_config(struct hdmi_ip_data *ip_data,
549 struct hdmi_core_video_config *cfg)
550 {
551 u32 r = 0;
552 void __iomem *core_sys_base = hdmi_core_sys_base(ip_data);
553
554 /* sys_ctrl1 default configuration not tunable */
555 r = hdmi_read_reg(core_sys_base, HDMI_CORE_CTRL1);
556 r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5);
557 r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4);
558 r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2);
559 r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1);
560 hdmi_write_reg(core_sys_base, HDMI_CORE_CTRL1, r);
561
562 REG_FLD_MOD(core_sys_base,
563 HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6);
564
565 /* Vid_Mode */
566 r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE);
567
568 /* dither truncation configuration */
569 if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) {
570 r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6);
571 r = FLD_MOD(r, 1, 5, 5);
572 } else {
573 r = FLD_MOD(r, cfg->op_dither_truc, 7, 6);
574 r = FLD_MOD(r, 0, 5, 5);
575 }
576 hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r);
577
578 /* HDMI_Ctrl */
579 r = hdmi_read_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL);
580 r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6);
581 r = FLD_MOD(r, cfg->pkt_mode, 5, 3);
582 r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0);
583 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL, r);
584
585 /* TMDS_CTRL */
586 REG_FLD_MOD(core_sys_base,
587 HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5);
588 }
589
590 static void hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data *ip_data,
591 struct hdmi_core_infoframe_avi info_avi)
592 {
593 u32 val;
594 char sum = 0, checksum = 0;
595 void __iomem *av_base = hdmi_av_base(ip_data);
596
597 sum += 0x82 + 0x002 + 0x00D;
598 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082);
599 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_VERS, 0x002);
600 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_LEN, 0x00D);
601
602 val = (info_avi.db1_format << 5) |
603 (info_avi.db1_active_info << 4) |
604 (info_avi.db1_bar_info_dv << 2) |
605 (info_avi.db1_scan_info);
606 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(0), val);
607 sum += val;
608
609 val = (info_avi.db2_colorimetry << 6) |
610 (info_avi.db2_aspect_ratio << 4) |
611 (info_avi.db2_active_fmt_ar);
612 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(1), val);
613 sum += val;
614
615 val = (info_avi.db3_itc << 7) |
616 (info_avi.db3_ec << 4) |
617 (info_avi.db3_q_range << 2) |
618 (info_avi.db3_nup_scaling);
619 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(2), val);
620 sum += val;
621
622 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(3),
623 info_avi.db4_videocode);
624 sum += info_avi.db4_videocode;
625
626 val = info_avi.db5_pixel_repeat;
627 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(4), val);
628 sum += val;
629
630 val = info_avi.db6_7_line_eoftop & 0x00FF;
631 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(5), val);
632 sum += val;
633
634 val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF);
635 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(6), val);
636 sum += val;
637
638 val = info_avi.db8_9_line_sofbottom & 0x00FF;
639 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(7), val);
640 sum += val;
641
642 val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF);
643 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(8), val);
644 sum += val;
645
646 val = info_avi.db10_11_pixel_eofleft & 0x00FF;
647 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(9), val);
648 sum += val;
649
650 val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF);
651 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(10), val);
652 sum += val;
653
654 val = info_avi.db12_13_pixel_sofright & 0x00FF;
655 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(11), val);
656 sum += val;
657
658 val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF);
659 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(12), val);
660 sum += val;
661
662 checksum = 0x100 - sum;
663 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum);
664 }
665
666 static void hdmi_core_av_packet_config(struct hdmi_ip_data *ip_data,
667 struct hdmi_core_packet_enable_repeat repeat_cfg)
668 {
669 /* enable/repeat the infoframe */
670 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL1,
671 (repeat_cfg.audio_pkt << 5) |
672 (repeat_cfg.audio_pkt_repeat << 4) |
673 (repeat_cfg.avi_infoframe << 1) |
674 (repeat_cfg.avi_infoframe_repeat));
675
676 /* enable/repeat the packet */
677 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL2,
678 (repeat_cfg.gen_cntrl_pkt << 3) |
679 (repeat_cfg.gen_cntrl_pkt_repeat << 2) |
680 (repeat_cfg.generic_pkt << 1) |
681 (repeat_cfg.generic_pkt_repeat));
682 }
683
684 static void hdmi_wp_init(struct omap_video_timings *timings,
685 struct hdmi_video_format *video_fmt,
686 struct hdmi_video_interface *video_int)
687 {
688 pr_debug("Enter hdmi_wp_init\n");
689
690 timings->hbp = 0;
691 timings->hfp = 0;
692 timings->hsw = 0;
693 timings->vbp = 0;
694 timings->vfp = 0;
695 timings->vsw = 0;
696
697 video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
698 video_fmt->y_res = 0;
699 video_fmt->x_res = 0;
700
701 video_int->vsp = 0;
702 video_int->hsp = 0;
703
704 video_int->interlacing = 0;
705 video_int->tm = 0; /* HDMI_TIMING_SLAVE */
706
707 }
708
709 void ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data *ip_data, bool start)
710 {
711 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, start, 31, 31);
712 }
713
714 static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt,
715 struct omap_video_timings *timings, struct hdmi_config *param)
716 {
717 pr_debug("Enter hdmi_wp_video_init_format\n");
718
719 video_fmt->y_res = param->timings.timings.y_res;
720 video_fmt->x_res = param->timings.timings.x_res;
721
722 timings->hbp = param->timings.timings.hbp;
723 timings->hfp = param->timings.timings.hfp;
724 timings->hsw = param->timings.timings.hsw;
725 timings->vbp = param->timings.timings.vbp;
726 timings->vfp = param->timings.timings.vfp;
727 timings->vsw = param->timings.timings.vsw;
728 }
729
730 static void hdmi_wp_video_config_format(struct hdmi_ip_data *ip_data,
731 struct hdmi_video_format *video_fmt)
732 {
733 u32 l = 0;
734
735 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG,
736 video_fmt->packing_mode, 10, 8);
737
738 l |= FLD_VAL(video_fmt->y_res, 31, 16);
739 l |= FLD_VAL(video_fmt->x_res, 15, 0);
740 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_SIZE, l);
741 }
742
743 static void hdmi_wp_video_config_interface(struct hdmi_ip_data *ip_data,
744 struct hdmi_video_interface *video_int)
745 {
746 u32 r;
747 pr_debug("Enter hdmi_wp_video_config_interface\n");
748
749 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG);
750 r = FLD_MOD(r, video_int->vsp, 7, 7);
751 r = FLD_MOD(r, video_int->hsp, 6, 6);
752 r = FLD_MOD(r, video_int->interlacing, 3, 3);
753 r = FLD_MOD(r, video_int->tm, 1, 0);
754 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r);
755 }
756
757 static void hdmi_wp_video_config_timing(struct hdmi_ip_data *ip_data,
758 struct omap_video_timings *timings)
759 {
760 u32 timing_h = 0;
761 u32 timing_v = 0;
762
763 pr_debug("Enter hdmi_wp_video_config_timing\n");
764
765 timing_h |= FLD_VAL(timings->hbp, 31, 20);
766 timing_h |= FLD_VAL(timings->hfp, 19, 8);
767 timing_h |= FLD_VAL(timings->hsw, 7, 0);
768 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_H, timing_h);
769
770 timing_v |= FLD_VAL(timings->vbp, 31, 20);
771 timing_v |= FLD_VAL(timings->vfp, 19, 8);
772 timing_v |= FLD_VAL(timings->vsw, 7, 0);
773 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v);
774 }
775
776 void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data)
777 {
778 /* HDMI */
779 struct omap_video_timings video_timing;
780 struct hdmi_video_format video_format;
781 struct hdmi_video_interface video_interface;
782 /* HDMI core */
783 struct hdmi_core_infoframe_avi avi_cfg;
784 struct hdmi_core_video_config v_core_cfg;
785 struct hdmi_core_packet_enable_repeat repeat_cfg;
786 struct hdmi_config *cfg = &ip_data->cfg;
787
788 hdmi_wp_init(&video_timing, &video_format,
789 &video_interface);
790
791 hdmi_core_init(&v_core_cfg,
792 &avi_cfg,
793 &repeat_cfg);
794
795 hdmi_wp_video_init_format(&video_format, &video_timing, cfg);
796
797 hdmi_wp_video_config_timing(ip_data, &video_timing);
798
799 /* video config */
800 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
801
802 hdmi_wp_video_config_format(ip_data, &video_format);
803
804 video_interface.vsp = cfg->timings.vsync_pol;
805 video_interface.hsp = cfg->timings.hsync_pol;
806 video_interface.interlacing = cfg->interlace;
807 video_interface.tm = 1 ; /* HDMI_TIMING_MASTER_24BIT */
808
809 hdmi_wp_video_config_interface(ip_data, &video_interface);
810
811 /*
812 * configure core video part
813 * set software reset in the core
814 */
815 hdmi_core_swreset_assert(ip_data);
816
817 /* power down off */
818 hdmi_core_powerdown_disable(ip_data);
819
820 v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL;
821 v_core_cfg.hdmi_dvi = cfg->cm.mode;
822
823 hdmi_core_video_config(ip_data, &v_core_cfg);
824
825 /* release software reset in the core */
826 hdmi_core_swreset_release(ip_data);
827
828 /*
829 * configure packet
830 * info frame video see doc CEA861-D page 65
831 */
832 avi_cfg.db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB;
833 avi_cfg.db1_active_info =
834 HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF;
835 avi_cfg.db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO;
836 avi_cfg.db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0;
837 avi_cfg.db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO;
838 avi_cfg.db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO;
839 avi_cfg.db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME;
840 avi_cfg.db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO;
841 avi_cfg.db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601;
842 avi_cfg.db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT;
843 avi_cfg.db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO;
844 avi_cfg.db4_videocode = cfg->cm.code;
845 avi_cfg.db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO;
846 avi_cfg.db6_7_line_eoftop = 0;
847 avi_cfg.db8_9_line_sofbottom = 0;
848 avi_cfg.db10_11_pixel_eofleft = 0;
849 avi_cfg.db12_13_pixel_sofright = 0;
850
851 hdmi_core_aux_infoframe_avi_config(ip_data, avi_cfg);
852
853 /* enable/repeat the infoframe */
854 repeat_cfg.avi_infoframe = HDMI_PACKETENABLE;
855 repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON;
856 /* wakeup */
857 repeat_cfg.audio_pkt = HDMI_PACKETENABLE;
858 repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON;
859 hdmi_core_av_packet_config(ip_data, repeat_cfg);
860 }
861
862 void ti_hdmi_4xxx_wp_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
863 {
864 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r,\
865 hdmi_read_reg(hdmi_wp_base(ip_data), r))
866
867 DUMPREG(HDMI_WP_REVISION);
868 DUMPREG(HDMI_WP_SYSCONFIG);
869 DUMPREG(HDMI_WP_IRQSTATUS_RAW);
870 DUMPREG(HDMI_WP_IRQSTATUS);
871 DUMPREG(HDMI_WP_PWR_CTRL);
872 DUMPREG(HDMI_WP_IRQENABLE_SET);
873 DUMPREG(HDMI_WP_VIDEO_CFG);
874 DUMPREG(HDMI_WP_VIDEO_SIZE);
875 DUMPREG(HDMI_WP_VIDEO_TIMING_H);
876 DUMPREG(HDMI_WP_VIDEO_TIMING_V);
877 DUMPREG(HDMI_WP_WP_CLK);
878 DUMPREG(HDMI_WP_AUDIO_CFG);
879 DUMPREG(HDMI_WP_AUDIO_CFG2);
880 DUMPREG(HDMI_WP_AUDIO_CTRL);
881 DUMPREG(HDMI_WP_AUDIO_DATA);
882 }
883
884 void ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
885 {
886 #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\
887 hdmi_read_reg(hdmi_pll_base(ip_data), r))
888
889 DUMPPLL(PLLCTRL_PLL_CONTROL);
890 DUMPPLL(PLLCTRL_PLL_STATUS);
891 DUMPPLL(PLLCTRL_PLL_GO);
892 DUMPPLL(PLLCTRL_CFG1);
893 DUMPPLL(PLLCTRL_CFG2);
894 DUMPPLL(PLLCTRL_CFG3);
895 DUMPPLL(PLLCTRL_CFG4);
896 }
897
898 void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
899 {
900 int i;
901
902 #define CORE_REG(i, name) name(i)
903 #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
904 hdmi_read_reg(hdmi_pll_base(ip_data), r))
905 #define DUMPCOREAV(i, r) seq_printf(s, "%s[%d]%*s %08x\n", #r, i, \
906 (i < 10) ? 32 - strlen(#r) : 31 - strlen(#r), " ", \
907 hdmi_read_reg(hdmi_pll_base(ip_data), CORE_REG(i, r)))
908
909 DUMPCORE(HDMI_CORE_SYS_VND_IDL);
910 DUMPCORE(HDMI_CORE_SYS_DEV_IDL);
911 DUMPCORE(HDMI_CORE_SYS_DEV_IDH);
912 DUMPCORE(HDMI_CORE_SYS_DEV_REV);
913 DUMPCORE(HDMI_CORE_SYS_SRST);
914 DUMPCORE(HDMI_CORE_CTRL1);
915 DUMPCORE(HDMI_CORE_SYS_SYS_STAT);
916 DUMPCORE(HDMI_CORE_SYS_VID_ACEN);
917 DUMPCORE(HDMI_CORE_SYS_VID_MODE);
918 DUMPCORE(HDMI_CORE_SYS_INTR_STATE);
919 DUMPCORE(HDMI_CORE_SYS_INTR1);
920 DUMPCORE(HDMI_CORE_SYS_INTR2);
921 DUMPCORE(HDMI_CORE_SYS_INTR3);
922 DUMPCORE(HDMI_CORE_SYS_INTR4);
923 DUMPCORE(HDMI_CORE_SYS_UMASK1);
924 DUMPCORE(HDMI_CORE_SYS_TMDS_CTRL);
925 DUMPCORE(HDMI_CORE_SYS_DE_DLY);
926 DUMPCORE(HDMI_CORE_SYS_DE_CTRL);
927 DUMPCORE(HDMI_CORE_SYS_DE_TOP);
928 DUMPCORE(HDMI_CORE_SYS_DE_CNTL);
929 DUMPCORE(HDMI_CORE_SYS_DE_CNTH);
930 DUMPCORE(HDMI_CORE_SYS_DE_LINL);
931 DUMPCORE(HDMI_CORE_SYS_DE_LINH_1);
932
933 DUMPCORE(HDMI_CORE_DDC_CMD);
934 DUMPCORE(HDMI_CORE_DDC_STATUS);
935 DUMPCORE(HDMI_CORE_DDC_ADDR);
936 DUMPCORE(HDMI_CORE_DDC_OFFSET);
937 DUMPCORE(HDMI_CORE_DDC_COUNT1);
938 DUMPCORE(HDMI_CORE_DDC_COUNT2);
939 DUMPCORE(HDMI_CORE_DDC_DATA);
940 DUMPCORE(HDMI_CORE_DDC_SEGM);
941
942 DUMPCORE(HDMI_CORE_AV_HDMI_CTRL);
943 DUMPCORE(HDMI_CORE_AV_DPD);
944 DUMPCORE(HDMI_CORE_AV_PB_CTRL1);
945 DUMPCORE(HDMI_CORE_AV_PB_CTRL2);
946 DUMPCORE(HDMI_CORE_AV_AVI_TYPE);
947 DUMPCORE(HDMI_CORE_AV_AVI_VERS);
948 DUMPCORE(HDMI_CORE_AV_AVI_LEN);
949 DUMPCORE(HDMI_CORE_AV_AVI_CHSUM);
950
951 for (i = 0; i < HDMI_CORE_AV_AVI_DBYTE_NELEMS; i++)
952 DUMPCOREAV(i, HDMI_CORE_AV_AVI_DBYTE);
953
954 for (i = 0; i < HDMI_CORE_AV_SPD_DBYTE_NELEMS; i++)
955 DUMPCOREAV(i, HDMI_CORE_AV_SPD_DBYTE);
956
957 for (i = 0; i < HDMI_CORE_AV_AUD_DBYTE_NELEMS; i++)
958 DUMPCOREAV(i, HDMI_CORE_AV_AUD_DBYTE);
959
960 for (i = 0; i < HDMI_CORE_AV_MPEG_DBYTE_NELEMS; i++)
961 DUMPCOREAV(i, HDMI_CORE_AV_MPEG_DBYTE);
962
963 for (i = 0; i < HDMI_CORE_AV_GEN_DBYTE_NELEMS; i++)
964 DUMPCOREAV(i, HDMI_CORE_AV_GEN_DBYTE);
965
966 for (i = 0; i < HDMI_CORE_AV_GEN2_DBYTE_NELEMS; i++)
967 DUMPCOREAV(i, HDMI_CORE_AV_GEN2_DBYTE);
968
969 DUMPCORE(HDMI_CORE_AV_ACR_CTRL);
970 DUMPCORE(HDMI_CORE_AV_FREQ_SVAL);
971 DUMPCORE(HDMI_CORE_AV_N_SVAL1);
972 DUMPCORE(HDMI_CORE_AV_N_SVAL2);
973 DUMPCORE(HDMI_CORE_AV_N_SVAL3);
974 DUMPCORE(HDMI_CORE_AV_CTS_SVAL1);
975 DUMPCORE(HDMI_CORE_AV_CTS_SVAL2);
976 DUMPCORE(HDMI_CORE_AV_CTS_SVAL3);
977 DUMPCORE(HDMI_CORE_AV_CTS_HVAL1);
978 DUMPCORE(HDMI_CORE_AV_CTS_HVAL2);
979 DUMPCORE(HDMI_CORE_AV_CTS_HVAL3);
980 DUMPCORE(HDMI_CORE_AV_AUD_MODE);
981 DUMPCORE(HDMI_CORE_AV_SPDIF_CTRL);
982 DUMPCORE(HDMI_CORE_AV_HW_SPDIF_FS);
983 DUMPCORE(HDMI_CORE_AV_SWAP_I2S);
984 DUMPCORE(HDMI_CORE_AV_SPDIF_ERTH);
985 DUMPCORE(HDMI_CORE_AV_I2S_IN_MAP);
986 DUMPCORE(HDMI_CORE_AV_I2S_IN_CTRL);
987 DUMPCORE(HDMI_CORE_AV_I2S_CHST0);
988 DUMPCORE(HDMI_CORE_AV_I2S_CHST1);
989 DUMPCORE(HDMI_CORE_AV_I2S_CHST2);
990 DUMPCORE(HDMI_CORE_AV_I2S_CHST4);
991 DUMPCORE(HDMI_CORE_AV_I2S_CHST5);
992 DUMPCORE(HDMI_CORE_AV_ASRC);
993 DUMPCORE(HDMI_CORE_AV_I2S_IN_LEN);
994 DUMPCORE(HDMI_CORE_AV_HDMI_CTRL);
995 DUMPCORE(HDMI_CORE_AV_AUDO_TXSTAT);
996 DUMPCORE(HDMI_CORE_AV_AUD_PAR_BUSCLK_1);
997 DUMPCORE(HDMI_CORE_AV_AUD_PAR_BUSCLK_2);
998 DUMPCORE(HDMI_CORE_AV_AUD_PAR_BUSCLK_3);
999 DUMPCORE(HDMI_CORE_AV_TEST_TXCTRL);
1000 DUMPCORE(HDMI_CORE_AV_DPD);
1001 DUMPCORE(HDMI_CORE_AV_PB_CTRL1);
1002 DUMPCORE(HDMI_CORE_AV_PB_CTRL2);
1003 DUMPCORE(HDMI_CORE_AV_AVI_TYPE);
1004 DUMPCORE(HDMI_CORE_AV_AVI_VERS);
1005 DUMPCORE(HDMI_CORE_AV_AVI_LEN);
1006 DUMPCORE(HDMI_CORE_AV_AVI_CHSUM);
1007 DUMPCORE(HDMI_CORE_AV_SPD_TYPE);
1008 DUMPCORE(HDMI_CORE_AV_SPD_VERS);
1009 DUMPCORE(HDMI_CORE_AV_SPD_LEN);
1010 DUMPCORE(HDMI_CORE_AV_SPD_CHSUM);
1011 DUMPCORE(HDMI_CORE_AV_AUDIO_TYPE);
1012 DUMPCORE(HDMI_CORE_AV_AUDIO_VERS);
1013 DUMPCORE(HDMI_CORE_AV_AUDIO_LEN);
1014 DUMPCORE(HDMI_CORE_AV_AUDIO_CHSUM);
1015 DUMPCORE(HDMI_CORE_AV_MPEG_TYPE);
1016 DUMPCORE(HDMI_CORE_AV_MPEG_VERS);
1017 DUMPCORE(HDMI_CORE_AV_MPEG_LEN);
1018 DUMPCORE(HDMI_CORE_AV_MPEG_CHSUM);
1019 DUMPCORE(HDMI_CORE_AV_CP_BYTE1);
1020 DUMPCORE(HDMI_CORE_AV_CEC_ADDR_ID);
1021 }
1022
1023 void ti_hdmi_4xxx_phy_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
1024 {
1025 #define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\
1026 hdmi_read_reg(hdmi_phy_base(ip_data), r))
1027
1028 DUMPPHY(HDMI_TXPHY_TX_CTRL);
1029 DUMPPHY(HDMI_TXPHY_DIGITAL_CTRL);
1030 DUMPPHY(HDMI_TXPHY_POWER_CTRL);
1031 DUMPPHY(HDMI_TXPHY_PAD_CFG_CTRL);
1032 }
1033
1034 #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
1035 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
1036 void hdmi_wp_audio_config_format(struct hdmi_ip_data *ip_data,
1037 struct hdmi_audio_format *aud_fmt)
1038 {
1039 u32 r;
1040
1041 DSSDBG("Enter hdmi_wp_audio_config_format\n");
1042
1043 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG);
1044 r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24);
1045 r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16);
1046 r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5);
1047 r = FLD_MOD(r, aud_fmt->type, 4, 4);
1048 r = FLD_MOD(r, aud_fmt->justification, 3, 3);
1049 r = FLD_MOD(r, aud_fmt->sample_order, 2, 2);
1050 r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1);
1051 r = FLD_MOD(r, aud_fmt->sample_size, 0, 0);
1052 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG, r);
1053 }
1054
1055 void hdmi_wp_audio_config_dma(struct hdmi_ip_data *ip_data,
1056 struct hdmi_audio_dma *aud_dma)
1057 {
1058 u32 r;
1059
1060 DSSDBG("Enter hdmi_wp_audio_config_dma\n");
1061
1062 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2);
1063 r = FLD_MOD(r, aud_dma->transfer_size, 15, 8);
1064 r = FLD_MOD(r, aud_dma->block_size, 7, 0);
1065 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2, r);
1066
1067 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL);
1068 r = FLD_MOD(r, aud_dma->mode, 9, 9);
1069 r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0);
1070 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL, r);
1071 }
1072
1073 void hdmi_core_audio_config(struct hdmi_ip_data *ip_data,
1074 struct hdmi_core_audio_config *cfg)
1075 {
1076 u32 r;
1077 void __iomem *av_base = hdmi_av_base(ip_data);
1078
1079 /* audio clock recovery parameters */
1080 r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL);
1081 r = FLD_MOD(r, cfg->use_mclk, 2, 2);
1082 r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1);
1083 r = FLD_MOD(r, cfg->cts_mode, 0, 0);
1084 hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r);
1085
1086 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0);
1087 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0);
1088 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0);
1089
1090 if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) {
1091 REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0);
1092 REG_FLD_MOD(av_base,
1093 HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0);
1094 REG_FLD_MOD(av_base,
1095 HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0);
1096 } else {
1097 /*
1098 * HDMI IP uses this configuration to divide the MCLK to
1099 * update CTS value.
1100 */
1101 REG_FLD_MOD(av_base,
1102 HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0);
1103
1104 /* Configure clock for audio packets */
1105 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1,
1106 cfg->aud_par_busclk, 7, 0);
1107 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2,
1108 (cfg->aud_par_busclk >> 8), 7, 0);
1109 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_3,
1110 (cfg->aud_par_busclk >> 16), 7, 0);
1111 }
1112
1113 /* Override of SPDIF sample frequency with value in I2S_CHST4 */
1114 REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL,
1115 cfg->fs_override, 1, 1);
1116
1117 /* I2S parameters */
1118 REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_CHST4,
1119 cfg->freq_sample, 3, 0);
1120
1121 r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL);
1122 r = FLD_MOD(r, cfg->i2s_cfg.en_high_bitrate_aud, 7, 7);
1123 r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6);
1124 r = FLD_MOD(r, cfg->i2s_cfg.cbit_order, 5, 5);
1125 r = FLD_MOD(r, cfg->i2s_cfg.vbit, 4, 4);
1126 r = FLD_MOD(r, cfg->i2s_cfg.ws_polarity, 3, 3);
1127 r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2);
1128 r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1);
1129 r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0);
1130 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL, r);
1131
1132 r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_CHST5);
1133 r = FLD_MOD(r, cfg->freq_sample, 7, 4);
1134 r = FLD_MOD(r, cfg->i2s_cfg.word_length, 3, 1);
1135 r = FLD_MOD(r, cfg->i2s_cfg.word_max_length, 0, 0);
1136 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST5, r);
1137
1138 REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_IN_LEN,
1139 cfg->i2s_cfg.in_length_bits, 3, 0);
1140
1141 /* Audio channels and mode parameters */
1142 REG_FLD_MOD(av_base, HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1);
1143 r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE);
1144 r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4);
1145 r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3);
1146 r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2);
1147 r = FLD_MOD(r, cfg->en_spdif, 1, 1);
1148 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_MODE, r);
1149 }
1150
1151 void hdmi_core_audio_infoframe_config(struct hdmi_ip_data *ip_data,
1152 struct hdmi_core_infoframe_audio *info_aud)
1153 {
1154 u8 val;
1155 u8 sum = 0, checksum = 0;
1156 void __iomem *av_base = hdmi_av_base(ip_data);
1157
1158 /*
1159 * Set audio info frame type, version and length as
1160 * described in HDMI 1.4a Section 8.2.2 specification.
1161 * Checksum calculation is defined in Section 5.3.5.
1162 */
1163 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_TYPE, 0x84);
1164 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_VERS, 0x01);
1165 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_LEN, 0x0a);
1166 sum += 0x84 + 0x001 + 0x00a;
1167
1168 val = (info_aud->db1_coding_type << 4)
1169 | (info_aud->db1_channel_count - 1);
1170 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(0), val);
1171 sum += val;
1172
1173 val = (info_aud->db2_sample_freq << 2) | info_aud->db2_sample_size;
1174 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(1), val);
1175 sum += val;
1176
1177 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(2), 0x00);
1178
1179 val = info_aud->db4_channel_alloc;
1180 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(3), val);
1181 sum += val;
1182
1183 val = (info_aud->db5_downmix_inh << 7) | (info_aud->db5_lsv << 3);
1184 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(4), val);
1185 sum += val;
1186
1187 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(5), 0x00);
1188 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(6), 0x00);
1189 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(7), 0x00);
1190 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(8), 0x00);
1191 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(9), 0x00);
1192
1193 checksum = 0x100 - sum;
1194 hdmi_write_reg(av_base,
1195 HDMI_CORE_AV_AUDIO_CHSUM, checksum);
1196
1197 /*
1198 * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing
1199 * is available.
1200 */
1201 }
1202
1203 int hdmi_config_audio_acr(struct hdmi_ip_data *ip_data,
1204 u32 sample_freq, u32 *n, u32 *cts)
1205 {
1206 u32 r;
1207 u32 deep_color = 0;
1208 u32 pclk = ip_data->cfg.timings.timings.pixel_clock;
1209
1210 if (n == NULL || cts == NULL)
1211 return -EINVAL;
1212 /*
1213 * Obtain current deep color configuration. This needed
1214 * to calculate the TMDS clock based on the pixel clock.
1215 */
1216 r = REG_GET(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, 1, 0);
1217 switch (r) {
1218 case 1: /* No deep color selected */
1219 deep_color = 100;
1220 break;
1221 case 2: /* 10-bit deep color selected */
1222 deep_color = 125;
1223 break;
1224 case 3: /* 12-bit deep color selected */
1225 deep_color = 150;
1226 break;
1227 default:
1228 return -EINVAL;
1229 }
1230
1231 switch (sample_freq) {
1232 case 32000:
1233 if ((deep_color == 125) && ((pclk == 54054)
1234 || (pclk == 74250)))
1235 *n = 8192;
1236 else
1237 *n = 4096;
1238 break;
1239 case 44100:
1240 *n = 6272;
1241 break;
1242 case 48000:
1243 if ((deep_color == 125) && ((pclk == 54054)
1244 || (pclk == 74250)))
1245 *n = 8192;
1246 else
1247 *n = 6144;
1248 break;
1249 default:
1250 *n = 0;
1251 return -EINVAL;
1252 }
1253
1254 /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */
1255 *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10);
1256
1257 return 0;
1258 }
1259
1260 void ti_hdmi_4xxx_wp_audio_enable(struct hdmi_ip_data *ip_data, bool enable)
1261 {
1262 REG_FLD_MOD(hdmi_av_base(ip_data),
1263 HDMI_CORE_AV_AUD_MODE, enable, 0, 0);
1264 REG_FLD_MOD(hdmi_wp_base(ip_data),
1265 HDMI_WP_AUDIO_CTRL, enable, 31, 31);
1266 REG_FLD_MOD(hdmi_wp_base(ip_data),
1267 HDMI_WP_AUDIO_CTRL, enable, 30, 30);
1268 }
1269 #endif