drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h

   1 /*
   2  * ti_hdmi_4xxx_ip.h
   3  *
   4  * HDMI header definition for DM81xx, DM38xx, TI OMAP4 etc processors.
   5  *
   6  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License version 2 as published by
  10  * the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef _HDMI_TI_4xxx_H_
  22 #define _HDMI_TI_4xxx_H_
  23
  24 #include <linux/string.h>
  25 #include <video/omapdss.h>
  26 #include "ti_hdmi.h"
  27 #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
  28         defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
  29 #include <sound/soc.h>
  30 #include <sound/pcm_params.h>
  31 #endif
  32
  33 /* HDMI Wrapper */
  34
  35 #define HDMI_WP_REVISION                        0x0
  36 #define HDMI_WP_SYSCONFIG                       0x10
  37 #define HDMI_WP_IRQSTATUS_RAW                   0x24
  38 #define HDMI_WP_IRQSTATUS                       0x28
  39 #define HDMI_WP_PWR_CTRL                        0x40
  40 #define HDMI_WP_IRQENABLE_SET                   0x2C
  41 #define HDMI_WP_VIDEO_CFG                       0x50
  42 #define HDMI_WP_VIDEO_SIZE                      0x60
  43 #define HDMI_WP_VIDEO_TIMING_H                  0x68
  44 #define HDMI_WP_VIDEO_TIMING_V                  0x6C
  45 #define HDMI_WP_WP_CLK                          0x70
  46 #define HDMI_WP_AUDIO_CFG                       0x80
  47 #define HDMI_WP_AUDIO_CFG2                      0x84
  48 #define HDMI_WP_AUDIO_CTRL                      0x88
  49 #define HDMI_WP_AUDIO_DATA                      0x8C
  50
  51 /* HDMI IP Core System */
  52
  53 #define HDMI_CORE_SYS_VND_IDL                   0x0
  54 #define HDMI_CORE_SYS_DEV_IDL                   0x8
  55 #define HDMI_CORE_SYS_DEV_IDH                   0xC
  56 #define HDMI_CORE_SYS_DEV_REV                   0x10
  57 #define HDMI_CORE_SYS_SRST                      0x14
  58 #define HDMI_CORE_CTRL1                         0x20
  59 #define HDMI_CORE_SYS_SYS_STAT                  0x24
  60 #define HDMI_CORE_SYS_VID_ACEN                  0x124
  61 #define HDMI_CORE_SYS_VID_MODE                  0x128
  62 #define HDMI_CORE_SYS_INTR_STATE                0x1C0
  63 #define HDMI_CORE_SYS_INTR1                     0x1C4
  64 #define HDMI_CORE_SYS_INTR2                     0x1C8
  65 #define HDMI_CORE_SYS_INTR3                     0x1CC
  66 #define HDMI_CORE_SYS_INTR4                     0x1D0
  67 #define HDMI_CORE_SYS_UMASK1                    0x1D4
  68 #define HDMI_CORE_SYS_TMDS_CTRL                 0x208
  69 #define HDMI_CORE_SYS_DE_DLY                    0xC8
  70 #define HDMI_CORE_SYS_DE_CTRL                   0xCC
  71 #define HDMI_CORE_SYS_DE_TOP                    0xD0
  72 #define HDMI_CORE_SYS_DE_CNTL                   0xD8
  73 #define HDMI_CORE_SYS_DE_CNTH                   0xDC
  74 #define HDMI_CORE_SYS_DE_LINL                   0xE0
  75 #define HDMI_CORE_SYS_DE_LINH_1                 0xE4
  76 #define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC 0x1
  77 #define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC 0x1
  78 #define HDMI_CORE_CTRL1_BSEL_24BITBUS           0x1
  79 #define HDMI_CORE_CTRL1_EDGE_RISINGEDGE 0x1
  80
  81 /* HDMI DDC E-DID */
  82 #define HDMI_CORE_DDC_CMD                       0x3CC
  83 #define HDMI_CORE_DDC_STATUS                    0x3C8
  84 #define HDMI_CORE_DDC_ADDR                      0x3B4
  85 #define HDMI_CORE_DDC_OFFSET                    0x3BC
  86 #define HDMI_CORE_DDC_COUNT1                    0x3C0
  87 #define HDMI_CORE_DDC_COUNT2                    0x3C4
  88 #define HDMI_CORE_DDC_DATA                      0x3D0
  89 #define HDMI_CORE_DDC_SEGM                      0x3B8
  90
  91 /* HDMI IP Core Audio Video */
  92
  93 #define HDMI_CORE_AV_HDMI_CTRL                  0xBC
  94 #define HDMI_CORE_AV_DPD                        0xF4
  95 #define HDMI_CORE_AV_PB_CTRL1                   0xF8
  96 #define HDMI_CORE_AV_PB_CTRL2                   0xFC
  97 #define HDMI_CORE_AV_AVI_TYPE                   0x100
  98 #define HDMI_CORE_AV_AVI_VERS                   0x104
  99 #define HDMI_CORE_AV_AVI_LEN                    0x108
 100 #define HDMI_CORE_AV_AVI_CHSUM                  0x10C
 101 #define HDMI_CORE_AV_AVI_DBYTE(n)               (n * 4 + 0x110)
 102 #define HDMI_CORE_AV_AVI_DBYTE_NELEMS           15
 103 #define HDMI_CORE_AV_SPD_DBYTE(n)               (n * 4 + 0x190)
 104 #define HDMI_CORE_AV_SPD_DBYTE_NELEMS           27
 105 #define HDMI_CORE_AV_AUD_DBYTE(n)               (n * 4 + 0x210)
 106 #define HDMI_CORE_AV_AUD_DBYTE_NELEMS           10
 107 #define HDMI_CORE_AV_MPEG_DBYTE(n)              (n * 4 + 0x290)
 108 #define HDMI_CORE_AV_MPEG_DBYTE_NELEMS          27
 109 #define HDMI_CORE_AV_GEN_DBYTE(n)               (n * 4 + 0x300)
 110 #define HDMI_CORE_AV_GEN_DBYTE_NELEMS           31
 111 #define HDMI_CORE_AV_GEN2_DBYTE(n)              (n * 4 + 0x380)
 112 #define HDMI_CORE_AV_GEN2_DBYTE_NELEMS          31
 113 #define HDMI_CORE_AV_ACR_CTRL                   0x4
 114 #define HDMI_CORE_AV_FREQ_SVAL                  0x8
 115 #define HDMI_CORE_AV_N_SVAL1                    0xC
 116 #define HDMI_CORE_AV_N_SVAL2                    0x10
 117 #define HDMI_CORE_AV_N_SVAL3                    0x14
 118 #define HDMI_CORE_AV_CTS_SVAL1                  0x18
 119 #define HDMI_CORE_AV_CTS_SVAL2                  0x1C
 120 #define HDMI_CORE_AV_CTS_SVAL3                  0x20
 121 #define HDMI_CORE_AV_CTS_HVAL1                  0x24
 122 #define HDMI_CORE_AV_CTS_HVAL2                  0x28
 123 #define HDMI_CORE_AV_CTS_HVAL3                  0x2C
 124 #define HDMI_CORE_AV_AUD_MODE                   0x50
 125 #define HDMI_CORE_AV_SPDIF_CTRL                 0x54
 126 #define HDMI_CORE_AV_HW_SPDIF_FS                0x60
 127 #define HDMI_CORE_AV_SWAP_I2S                   0x64
 128 #define HDMI_CORE_AV_SPDIF_ERTH                 0x6C
 129 #define HDMI_CORE_AV_I2S_IN_MAP                 0x70
 130 #define HDMI_CORE_AV_I2S_IN_CTRL                0x74
 131 #define HDMI_CORE_AV_I2S_CHST0                  0x78
 132 #define HDMI_CORE_AV_I2S_CHST1                  0x7C
 133 #define HDMI_CORE_AV_I2S_CHST2                  0x80
 134 #define HDMI_CORE_AV_I2S_CHST4                  0x84
 135 #define HDMI_CORE_AV_I2S_CHST5                  0x88
 136 #define HDMI_CORE_AV_ASRC                       0x8C
 137 #define HDMI_CORE_AV_I2S_IN_LEN                 0x90
 138 #define HDMI_CORE_AV_HDMI_CTRL                  0xBC
 139 #define HDMI_CORE_AV_AUDO_TXSTAT                0xC0
 140 #define HDMI_CORE_AV_AUD_PAR_BUSCLK_1           0xCC
 141 #define HDMI_CORE_AV_AUD_PAR_BUSCLK_2           0xD0
 142 #define HDMI_CORE_AV_AUD_PAR_BUSCLK_3           0xD4
 143 #define HDMI_CORE_AV_TEST_TXCTRL                0xF0
 144 #define HDMI_CORE_AV_DPD                        0xF4
 145 #define HDMI_CORE_AV_PB_CTRL1                   0xF8
 146 #define HDMI_CORE_AV_PB_CTRL2                   0xFC
 147 #define HDMI_CORE_AV_AVI_TYPE                   0x100
 148 #define HDMI_CORE_AV_AVI_VERS                   0x104
 149 #define HDMI_CORE_AV_AVI_LEN                    0x108
 150 #define HDMI_CORE_AV_AVI_CHSUM                  0x10C
 151 #define HDMI_CORE_AV_SPD_TYPE                   0x180
 152 #define HDMI_CORE_AV_SPD_VERS                   0x184
 153 #define HDMI_CORE_AV_SPD_LEN                    0x188
 154 #define HDMI_CORE_AV_SPD_CHSUM                  0x18C
 155 #define HDMI_CORE_AV_AUDIO_TYPE                 0x200
 156 #define HDMI_CORE_AV_AUDIO_VERS                 0x204
 157 #define HDMI_CORE_AV_AUDIO_LEN                  0x208
 158 #define HDMI_CORE_AV_AUDIO_CHSUM                0x20C
 159 #define HDMI_CORE_AV_MPEG_TYPE                  0x280
 160 #define HDMI_CORE_AV_MPEG_VERS                  0x284
 161 #define HDMI_CORE_AV_MPEG_LEN                   0x288
 162 #define HDMI_CORE_AV_MPEG_CHSUM                 0x28C
 163 #define HDMI_CORE_AV_CP_BYTE1                   0x37C
 164 #define HDMI_CORE_AV_CEC_ADDR_ID                0x3FC
 165 #define HDMI_CORE_AV_SPD_DBYTE_ELSIZE           0x4
 166 #define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE          0x4
 167 #define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE          0x4
 168 #define HDMI_CORE_AV_GEN_DBYTE_ELSIZE           0x4
 169
 170 /* PLL */
 171
 172 #define PLLCTRL_PLL_CONTROL                     0x0
 173 #define PLLCTRL_PLL_STATUS                      0x4
 174 #define PLLCTRL_PLL_GO                          0x8
 175 #define PLLCTRL_CFG1                            0xC
 176 #define PLLCTRL_CFG2                            0x10
 177 #define PLLCTRL_CFG3                            0x14
 178 #define PLLCTRL_CFG4                            0x20
 179
 180 /* HDMI PHY */
 181
 182 #define HDMI_TXPHY_TX_CTRL                      0x0
 183 #define HDMI_TXPHY_DIGITAL_CTRL                 0x4
 184 #define HDMI_TXPHY_POWER_CTRL                   0x8
 185 #define HDMI_TXPHY_PAD_CFG_CTRL                 0xC
 186
 187 #define REG_FLD_MOD(base, idx, val, start, end) \
 188         hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
 189                                                         val, start, end))
 190 #define REG_GET(base, idx, start, end) \
 191         FLD_GET(hdmi_read_reg(base, idx), start, end)
 192
 193 enum hdmi_phy_pwr {
 194         HDMI_PHYPWRCMD_OFF = 0,
 195         HDMI_PHYPWRCMD_LDOON = 1,
 196         HDMI_PHYPWRCMD_TXON = 2
 197 };
 198
 199 enum hdmi_core_inputbus_width {
 200         HDMI_INPUT_8BIT = 0,
 201         HDMI_INPUT_10BIT = 1,
 202         HDMI_INPUT_12BIT = 2
 203 };
 204
 205 enum hdmi_core_dither_trunc {
 206         HDMI_OUTPUTTRUNCATION_8BIT = 0,
 207         HDMI_OUTPUTTRUNCATION_10BIT = 1,
 208         HDMI_OUTPUTTRUNCATION_12BIT = 2,
 209         HDMI_OUTPUTDITHER_8BIT = 3,
 210         HDMI_OUTPUTDITHER_10BIT = 4,
 211         HDMI_OUTPUTDITHER_12BIT = 5
 212 };
 213
 214 enum hdmi_core_deepcolor_ed {
 215         HDMI_DEEPCOLORPACKECTDISABLE = 0,
 216         HDMI_DEEPCOLORPACKECTENABLE = 1
 217 };
 218
 219 enum hdmi_core_packet_mode {
 220         HDMI_PACKETMODERESERVEDVALUE = 0,
 221         HDMI_PACKETMODE24BITPERPIXEL = 4,
 222         HDMI_PACKETMODE30BITPERPIXEL = 5,
 223         HDMI_PACKETMODE36BITPERPIXEL = 6,
 224         HDMI_PACKETMODE48BITPERPIXEL = 7
 225 };
 226
 227 enum hdmi_core_tclkselclkmult {
 228         HDMI_FPLL05IDCK = 0,
 229         HDMI_FPLL10IDCK = 1,
 230         HDMI_FPLL20IDCK = 2,
 231         HDMI_FPLL40IDCK = 3
 232 };
 233
 234 enum hdmi_core_packet_ctrl {
 235         HDMI_PACKETENABLE = 1,
 236         HDMI_PACKETDISABLE = 0,
 237         HDMI_PACKETREPEATON = 1,
 238         HDMI_PACKETREPEATOFF = 0
 239 };
 240
 241 /* INFOFRAME_AVI_ and INFOFRAME_AUDIO_ definitions */
 242 enum hdmi_core_infoframe {
 243         HDMI_INFOFRAME_AVI_DB1Y_RGB = 0,
 244         HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1,
 245         HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2,
 246         HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0,
 247         HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON =  1,
 248         HDMI_INFOFRAME_AVI_DB1B_NO = 0,
 249         HDMI_INFOFRAME_AVI_DB1B_VERT = 1,
 250         HDMI_INFOFRAME_AVI_DB1B_HORI = 2,
 251         HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3,
 252         HDMI_INFOFRAME_AVI_DB1S_0 = 0,
 253         HDMI_INFOFRAME_AVI_DB1S_1 = 1,
 254         HDMI_INFOFRAME_AVI_DB1S_2 = 2,
 255         HDMI_INFOFRAME_AVI_DB2C_NO = 0,
 256         HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1,
 257         HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2,
 258         HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3,
 259         HDMI_INFOFRAME_AVI_DB2M_NO = 0,
 260         HDMI_INFOFRAME_AVI_DB2M_43 = 1,
 261         HDMI_INFOFRAME_AVI_DB2M_169 = 2,
 262         HDMI_INFOFRAME_AVI_DB2R_SAME = 8,
 263         HDMI_INFOFRAME_AVI_DB2R_43 = 9,
 264         HDMI_INFOFRAME_AVI_DB2R_169 = 10,
 265         HDMI_INFOFRAME_AVI_DB2R_149 = 11,
 266         HDMI_INFOFRAME_AVI_DB3ITC_NO = 0,
 267         HDMI_INFOFRAME_AVI_DB3ITC_YES = 1,
 268         HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0,
 269         HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1,
 270         HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0,
 271         HDMI_INFOFRAME_AVI_DB3Q_LR = 1,
 272         HDMI_INFOFRAME_AVI_DB3Q_FR = 2,
 273         HDMI_INFOFRAME_AVI_DB3SC_NO = 0,
 274         HDMI_INFOFRAME_AVI_DB3SC_HORI = 1,
 275         HDMI_INFOFRAME_AVI_DB3SC_VERT = 2,
 276         HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3,
 277         HDMI_INFOFRAME_AVI_DB5PR_NO = 0,
 278         HDMI_INFOFRAME_AVI_DB5PR_2 = 1,
 279         HDMI_INFOFRAME_AVI_DB5PR_3 = 2,
 280         HDMI_INFOFRAME_AVI_DB5PR_4 = 3,
 281         HDMI_INFOFRAME_AVI_DB5PR_5 = 4,
 282         HDMI_INFOFRAME_AVI_DB5PR_6 = 5,
 283         HDMI_INFOFRAME_AVI_DB5PR_7 = 6,
 284         HDMI_INFOFRAME_AVI_DB5PR_8 = 7,
 285         HDMI_INFOFRAME_AVI_DB5PR_9 = 8,
 286         HDMI_INFOFRAME_AVI_DB5PR_10 = 9,
 287         HDMI_INFOFRAME_AUDIO_DB1CT_FROM_STREAM = 0,
 288         HDMI_INFOFRAME_AUDIO_DB1CT_IEC60958 = 1,
 289         HDMI_INFOFRAME_AUDIO_DB1CT_AC3 = 2,
 290         HDMI_INFOFRAME_AUDIO_DB1CT_MPEG1 = 3,
 291         HDMI_INFOFRAME_AUDIO_DB1CT_MP3 = 4,
 292         HDMI_INFOFRAME_AUDIO_DB1CT_MPEG2_MULTICH = 5,
 293         HDMI_INFOFRAME_AUDIO_DB1CT_AAC = 6,
 294         HDMI_INFOFRAME_AUDIO_DB1CT_DTS = 7,
 295         HDMI_INFOFRAME_AUDIO_DB1CT_ATRAC = 8,
 296         HDMI_INFOFRAME_AUDIO_DB1CT_ONEBIT = 9,
 297         HDMI_INFOFRAME_AUDIO_DB1CT_DOLBY_DIGITAL_PLUS = 10,
 298         HDMI_INFOFRAME_AUDIO_DB1CT_DTS_HD = 11,
 299         HDMI_INFOFRAME_AUDIO_DB1CT_MAT = 12,
 300         HDMI_INFOFRAME_AUDIO_DB1CT_DST = 13,
 301         HDMI_INFOFRAME_AUDIO_DB1CT_WMA_PRO = 14,
 302         HDMI_INFOFRAME_AUDIO_DB2SF_FROM_STREAM = 0,
 303         HDMI_INFOFRAME_AUDIO_DB2SF_32000 = 1,
 304         HDMI_INFOFRAME_AUDIO_DB2SF_44100 = 2,
 305         HDMI_INFOFRAME_AUDIO_DB2SF_48000 = 3,
 306         HDMI_INFOFRAME_AUDIO_DB2SF_88200 = 4,
 307         HDMI_INFOFRAME_AUDIO_DB2SF_96000 = 5,
 308         HDMI_INFOFRAME_AUDIO_DB2SF_176400 = 6,
 309         HDMI_INFOFRAME_AUDIO_DB2SF_192000 = 7,
 310         HDMI_INFOFRAME_AUDIO_DB2SS_FROM_STREAM = 0,
 311         HDMI_INFOFRAME_AUDIO_DB2SS_16BIT = 1,
 312         HDMI_INFOFRAME_AUDIO_DB2SS_20BIT = 2,
 313         HDMI_INFOFRAME_AUDIO_DB2SS_24BIT = 3,
 314         HDMI_INFOFRAME_AUDIO_DB5_DM_INH_PERMITTED = 0,
 315         HDMI_INFOFRAME_AUDIO_DB5_DM_INH_PROHIBITED = 1
 316 };
 317
 318 enum hdmi_packing_mode {
 319         HDMI_PACK_10b_RGB_YUV444 = 0,
 320         HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
 321         HDMI_PACK_20b_YUV422 = 2,
 322         HDMI_PACK_ALREADYPACKED = 7
 323 };
 324
 325 enum hdmi_core_audio_sample_freq {
 326         HDMI_AUDIO_FS_32000 = 0x3,
 327         HDMI_AUDIO_FS_44100 = 0x0,
 328         HDMI_AUDIO_FS_48000 = 0x2,
 329         HDMI_AUDIO_FS_88200 = 0x8,
 330         HDMI_AUDIO_FS_96000 = 0xA,
 331         HDMI_AUDIO_FS_176400 = 0xC,
 332         HDMI_AUDIO_FS_192000 = 0xE,
 333         HDMI_AUDIO_FS_NOT_INDICATED = 0x1
 334 };
 335
 336 enum hdmi_core_audio_layout {
 337         HDMI_AUDIO_LAYOUT_2CH = 0,
 338         HDMI_AUDIO_LAYOUT_8CH = 1
 339 };
 340
 341 enum hdmi_core_cts_mode {
 342         HDMI_AUDIO_CTS_MODE_HW = 0,
 343         HDMI_AUDIO_CTS_MODE_SW = 1
 344 };
 345
 346 enum hdmi_stereo_channels {
 347         HDMI_AUDIO_STEREO_NOCHANNELS = 0,
 348         HDMI_AUDIO_STEREO_ONECHANNEL = 1,
 349         HDMI_AUDIO_STEREO_TWOCHANNELS = 2,
 350         HDMI_AUDIO_STEREO_THREECHANNELS = 3,
 351         HDMI_AUDIO_STEREO_FOURCHANNELS = 4
 352 };
 353
 354 enum hdmi_audio_type {
 355         HDMI_AUDIO_TYPE_LPCM = 0,
 356         HDMI_AUDIO_TYPE_IEC = 1
 357 };
 358
 359 enum hdmi_audio_justify {
 360         HDMI_AUDIO_JUSTIFY_LEFT = 0,
 361         HDMI_AUDIO_JUSTIFY_RIGHT = 1
 362 };
 363
 364 enum hdmi_audio_sample_order {
 365         HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,
 366         HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1
 367 };
 368
 369 enum hdmi_audio_samples_perword {
 370         HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,
 371         HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1
 372 };
 373
 374 enum hdmi_audio_sample_size {
 375         HDMI_AUDIO_SAMPLE_16BITS = 0,
 376         HDMI_AUDIO_SAMPLE_24BITS = 1
 377 };
 378
 379 enum hdmi_audio_transf_mode {
 380         HDMI_AUDIO_TRANSF_DMA = 0,
 381         HDMI_AUDIO_TRANSF_IRQ = 1
 382 };
 383
 384 enum hdmi_audio_blk_strt_end_sig {
 385         HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,
 386         HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1
 387 };
 388
 389 enum hdmi_audio_i2s_config {
 390         HDMI_AUDIO_I2S_WS_POLARITY_LOW_IS_LEFT = 0,
 391         HDMI_AUDIO_I2S_WS_POLARIT_YLOW_IS_RIGHT = 1,
 392         HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST = 0,
 393         HDMI_AUDIO_I2S_LSB_SHIFTED_FIRST = 1,
 394         HDMI_AUDIO_I2S_MAX_WORD_20BITS = 0,
 395         HDMI_AUDIO_I2S_MAX_WORD_24BITS = 1,
 396         HDMI_AUDIO_I2S_CHST_WORD_NOT_SPECIFIED = 0,
 397         HDMI_AUDIO_I2S_CHST_WORD_16_BITS = 1,
 398         HDMI_AUDIO_I2S_CHST_WORD_17_BITS = 6,
 399         HDMI_AUDIO_I2S_CHST_WORD_18_BITS = 2,
 400         HDMI_AUDIO_I2S_CHST_WORD_19_BITS = 4,
 401         HDMI_AUDIO_I2S_CHST_WORD_20_BITS_20MAX = 5,
 402         HDMI_AUDIO_I2S_CHST_WORD_20_BITS_24MAX = 1,
 403         HDMI_AUDIO_I2S_CHST_WORD_21_BITS = 6,
 404         HDMI_AUDIO_I2S_CHST_WORD_22_BITS = 2,
 405         HDMI_AUDIO_I2S_CHST_WORD_23_BITS = 4,
 406         HDMI_AUDIO_I2S_CHST_WORD_24_BITS = 5,
 407         HDMI_AUDIO_I2S_SCK_EDGE_FALLING = 0,
 408         HDMI_AUDIO_I2S_SCK_EDGE_RISING = 1,
 409         HDMI_AUDIO_I2S_VBIT_FOR_PCM = 0,
 410         HDMI_AUDIO_I2S_VBIT_FOR_COMPRESSED = 1,
 411         HDMI_AUDIO_I2S_INPUT_LENGTH_NA = 0,
 412         HDMI_AUDIO_I2S_INPUT_LENGTH_16 = 2,
 413         HDMI_AUDIO_I2S_INPUT_LENGTH_17 = 12,
 414         HDMI_AUDIO_I2S_INPUT_LENGTH_18 = 4,
 415         HDMI_AUDIO_I2S_INPUT_LENGTH_19 = 8,
 416         HDMI_AUDIO_I2S_INPUT_LENGTH_20 = 10,
 417         HDMI_AUDIO_I2S_INPUT_LENGTH_21 = 13,
 418         HDMI_AUDIO_I2S_INPUT_LENGTH_22 = 5,
 419         HDMI_AUDIO_I2S_INPUT_LENGTH_23 = 9,
 420         HDMI_AUDIO_I2S_INPUT_LENGTH_24 = 11,
 421         HDMI_AUDIO_I2S_FIRST_BIT_SHIFT = 0,
 422         HDMI_AUDIO_I2S_FIRST_BIT_NO_SHIFT = 1,
 423         HDMI_AUDIO_I2S_SD0_EN = 1,
 424         HDMI_AUDIO_I2S_SD1_EN = 1 << 1,
 425         HDMI_AUDIO_I2S_SD2_EN = 1 << 2,
 426         HDMI_AUDIO_I2S_SD3_EN = 1 << 3,
 427 };
 428
 429 enum hdmi_audio_mclk_mode {
 430         HDMI_AUDIO_MCLK_128FS = 0,
 431         HDMI_AUDIO_MCLK_256FS = 1,
 432         HDMI_AUDIO_MCLK_384FS = 2,
 433         HDMI_AUDIO_MCLK_512FS = 3,
 434         HDMI_AUDIO_MCLK_768FS = 4,
 435         HDMI_AUDIO_MCLK_1024FS = 5,
 436         HDMI_AUDIO_MCLK_1152FS = 6,
 437         HDMI_AUDIO_MCLK_192FS = 7
 438 };
 439
 440 struct hdmi_core_video_config {
 441         enum hdmi_core_inputbus_width   ip_bus_width;
 442         enum hdmi_core_dither_trunc     op_dither_truc;
 443         enum hdmi_core_deepcolor_ed     deep_color_pkt;
 444         enum hdmi_core_packet_mode      pkt_mode;
 445         enum hdmi_core_hdmi_dvi         hdmi_dvi;
 446         enum hdmi_core_tclkselclkmult   tclk_sel_clkmult;
 447 };
 448
 449 /*
 450  * Refer to section 8.2 in HDMI 1.3 specification for
 451  * details about infoframe databytes
 452  */
 453 struct hdmi_core_infoframe_avi {
 454         /* Y0, Y1 rgb,yCbCr */
 455         u8      db1_format;
 456         /* A0  Active information Present */
 457         u8      db1_active_info;
 458         /* B0, B1 Bar info data valid */
 459         u8      db1_bar_info_dv;
 460         /* S0, S1 scan information */
 461         u8      db1_scan_info;
 462         /* C0, C1 colorimetry */
 463         u8      db2_colorimetry;
 464         /* M0, M1 Aspect ratio (4:3, 16:9) */
 465         u8      db2_aspect_ratio;
 466         /* R0...R3 Active format aspect ratio */
 467         u8      db2_active_fmt_ar;
 468         /* ITC IT content. */
 469         u8      db3_itc;
 470         /* EC0, EC1, EC2 Extended colorimetry */
 471         u8      db3_ec;
 472         /* Q1, Q0 Quantization range */
 473         u8      db3_q_range;
 474         /* SC1, SC0 Non-uniform picture scaling */
 475         u8      db3_nup_scaling;
 476         /* VIC0..6 Video format identification */
 477         u8      db4_videocode;
 478         /* PR0..PR3 Pixel repetition factor */
 479         u8      db5_pixel_repeat;
 480         /* Line number end of top bar */
 481         u16     db6_7_line_eoftop;
 482         /* Line number start of bottom bar */
 483         u16     db8_9_line_sofbottom;
 484         /* Pixel number end of left bar */
 485         u16     db10_11_pixel_eofleft;
 486         /* Pixel number start of right bar */
 487         u16     db12_13_pixel_sofright;
 488 };
 489 /*
 490  * Refer to section 8.2 in HDMI 1.3 specification for
 491  * details about infoframe databytes
 492  */
 493 struct hdmi_core_infoframe_audio {
 494         u8 db1_coding_type;
 495         u8 db1_channel_count;
 496         u8 db2_sample_freq;
 497         u8 db2_sample_size;
 498         u8 db4_channel_alloc;
 499         bool db5_downmix_inh;
 500         u8 db5_lsv;     /* Level shift values for downmix */
 501 };
 502
 503 struct hdmi_core_packet_enable_repeat {
 504         u32     audio_pkt;
 505         u32     audio_pkt_repeat;
 506         u32     avi_infoframe;
 507         u32     avi_infoframe_repeat;
 508         u32     gen_cntrl_pkt;
 509         u32     gen_cntrl_pkt_repeat;
 510         u32     generic_pkt;
 511         u32     generic_pkt_repeat;
 512 };
 513
 514 struct hdmi_video_format {
 515         enum hdmi_packing_mode  packing_mode;
 516         u32                     y_res;  /* Line per panel */
 517         u32                     x_res;  /* pixel per line */
 518 };
 519
 520 struct hdmi_video_interface {
 521         int     vsp;    /* Vsync polarity */
 522         int     hsp;    /* Hsync polarity */
 523         int     interlacing;
 524         int     tm;     /* Timing mode */
 525 };
 526
 527 struct hdmi_audio_format {
 528         enum hdmi_stereo_channels               stereo_channels;
 529         u8                                      active_chnnls_msk;
 530         enum hdmi_audio_type                    type;
 531         enum hdmi_audio_justify                 justification;
 532         enum hdmi_audio_sample_order            sample_order;
 533         enum hdmi_audio_samples_perword         samples_per_word;
 534         enum hdmi_audio_sample_size             sample_size;
 535         enum hdmi_audio_blk_strt_end_sig        en_sig_blk_strt_end;
 536 };
 537
 538 struct hdmi_audio_dma {
 539         u8                              transfer_size;
 540         u8                              block_size;
 541         enum hdmi_audio_transf_mode     mode;
 542         u16                             fifo_threshold;
 543 };
 544
 545 struct hdmi_core_audio_i2s_config {
 546         u8 word_max_length;
 547         u8 word_length;
 548         u8 in_length_bits;
 549         u8 justification;
 550         u8 en_high_bitrate_aud;
 551         u8 sck_edge_mode;
 552         u8 cbit_order;
 553         u8 vbit;
 554         u8 ws_polarity;
 555         u8 direction;
 556         u8 shift;
 557         u8 active_sds;
 558 };
 559
 560 struct hdmi_core_audio_config {
 561         struct hdmi_core_audio_i2s_config       i2s_cfg;
 562         enum hdmi_core_audio_sample_freq        freq_sample;
 563         bool                                    fs_override;
 564         u32                                     n;
 565         u32                                     cts;
 566         u32                                     aud_par_busclk;
 567         enum hdmi_core_audio_layout             layout;
 568         enum hdmi_core_cts_mode                 cts_mode;
 569         bool                                    use_mclk;
 570         enum hdmi_audio_mclk_mode               mclk_mode;
 571         bool                                    en_acr_pkt;
 572         bool                                    en_dsd_audio;
 573         bool                                    en_parallel_aud_input;
 574         bool                                    en_spdif;
 575 };
 576
 577 #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
 578         defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
 579 int hdmi_config_audio_acr(struct hdmi_ip_data *ip_data,
 580                                 u32 sample_freq, u32 *n, u32 *cts);
 581 void hdmi_core_audio_infoframe_config(struct hdmi_ip_data *ip_data,
 582                 struct hdmi_core_infoframe_audio *info_aud);
 583 void hdmi_core_audio_config(struct hdmi_ip_data *ip_data,
 584                                         struct hdmi_core_audio_config *cfg);
 585 void hdmi_wp_audio_config_dma(struct hdmi_ip_data *ip_data,
 586                                         struct hdmi_audio_dma *aud_dma);
 587 void hdmi_wp_audio_config_format(struct hdmi_ip_data *ip_data,
 588                                         struct hdmi_audio_format *aud_fmt);
 589 #endif
 590 #endif