| blob | e8d88567680718167cf2fe389dbe4af3e0155887 |
1 /*
2 * linux/arch/arm/kernel/entry-armv.S
3 *
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Low-level vector interface routines
13 *
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
16 */
18 #include <asm/memory.h>
19 #include <asm/glue-df.h>
20 #include <asm/glue-pf.h>
21 #include <asm/vfpmacros.h>
22 #include <mach/entry-macro.S>
23 #include <asm/thread_notify.h>
24 #include <asm/unwind.h>
25 #include <asm/unistd.h>
26 #include <asm/tls.h>
28 #include "entry-header.S"
29 #include <asm/entry-macro-multi.S>
31 /*
32 * Interrupt handling. Preserves r7, r8, r9
33 */
34 .macro irq_handler
35 #ifdef CONFIG_MULTI_IRQ_HANDLER
36 ldr r5, =handle_arch_irq
37 mov r0, sp
38 ldr r5, [r5]
39 adr lr, BSYM(9997f)
40 teq r5, #0
41 movne pc, r5
42 #endif
43 arch_irq_handler_default
44 9997:
45 .endm
47 #ifdef CONFIG_KPROBES
48 .section .kprobes.text,"ax",%progbits
49 #else
50 .text
51 #endif
53 /*
54 * Invalid mode handlers
55 */
56 .macro inv_entry, reason
57 sub sp, sp, #S_FRAME_SIZE
58 ARM( stmib sp, {r1 - lr} )
59 THUMB( stmia sp, {r0 - r12} )
60 THUMB( str sp, [sp, #S_SP] )
61 THUMB( str lr, [sp, #S_LR] )
62 mov r1, #\reason
63 .endm
65 __pabt_invalid:
66 inv_entry BAD_PREFETCH
67 b common_invalid
68 ENDPROC(__pabt_invalid)
70 __dabt_invalid:
71 inv_entry BAD_DATA
72 b common_invalid
73 ENDPROC(__dabt_invalid)
75 __irq_invalid:
76 inv_entry BAD_IRQ
77 b common_invalid
78 ENDPROC(__irq_invalid)
80 __und_invalid:
81 inv_entry BAD_UNDEFINSTR
83 @
84 @ XXX fall through to common_invalid
85 @
87 @
88 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
89 @
90 common_invalid:
91 zero_fp
93 ldmia r0, {r4 - r6}
94 add r0, sp, #S_PC @ here for interlock avoidance
95 mov r7, #-1 @ "" "" "" ""
96 str r4, [sp] @ save preserved r0
97 stmia r0, {r5 - r7} @ lr_<exception>,
98 @ cpsr_<exception>, "old_r0"
100 mov r0, sp
101 b bad_mode
102 ENDPROC(__und_invalid)
104 /*
105 * SVC mode handlers
106 */
108 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
109 #define SPFIX(code...) code
110 #else
111 #define SPFIX(code...)
112 #endif
114 .macro svc_entry, stack_hole=0
115 UNWIND(.fnstart )
116 UNWIND(.save {r0 - pc} )
117 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
118 #ifdef CONFIG_THUMB2_KERNEL
119 SPFIX( str r0, [sp] ) @ temporarily saved
120 SPFIX( mov r0, sp )
121 SPFIX( tst r0, #4 ) @ test original stack alignment
122 SPFIX( ldr r0, [sp] ) @ restored
123 #else
124 SPFIX( tst sp, #4 )
125 #endif
126 SPFIX( subeq sp, sp, #4 )
127 stmia sp, {r1 - r12}
129 ldmia r0, {r1 - r3}
130 add r5, sp, #S_SP - 4 @ here for interlock avoidance
131 mov r4, #-1 @ "" "" "" ""
132 add r0, sp, #(S_FRAME_SIZE + \stack_hole - 4)
133 SPFIX( addeq r0, r0, #4 )
134 str r1, [sp, #-4]! @ save the "real" r0 copied
135 @ from the exception stack
137 mov r1, lr
139 @
140 @ We are now ready to fill in the remaining blanks on the stack:
141 @
142 @ r0 - sp_svc
143 @ r1 - lr_svc
144 @ r2 - lr_<exception>, already fixed up for correct return/restart
145 @ r3 - spsr_<exception>
146 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
147 @
148 stmia r5, {r0 - r4}
149 .endm
151 .align 5
152 __dabt_svc:
153 svc_entry
155 @
156 @ get ready to re-enable interrupts if appropriate
157 @
158 mrs r9, cpsr
159 tst r3, #PSR_I_BIT
160 biceq r9, r9, #PSR_I_BIT
162 @
163 @ Call the processor-specific abort handler:
164 @
165 @ r2 - aborted context pc
166 @ r3 - aborted context cpsr
167 @
168 @ The abort handler must return the aborted address in r0, and
169 @ the fault status register in r1. r9 must be preserved.
170 @
171 #ifdef MULTI_DABORT
172 ldr r4, .LCprocfns
173 mov lr, pc
174 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
175 #else
176 bl CPU_DABORT_HANDLER
177 #endif
179 @
180 @ set desired IRQ state, then call main handler
181 @
182 debug_entry r1
183 msr cpsr_c, r9
184 mov r2, sp
185 bl do_DataAbort
187 @
188 @ IRQs off again before pulling preserved data off the stack
189 @
190 disable_irq_notrace
192 @
193 @ restore SPSR and restart the instruction
194 @
195 ldr r2, [sp, #S_PSR]
196 svc_exit r2 @ return from exception
197 UNWIND(.fnend )
198 ENDPROC(__dabt_svc)
200 .align 5
201 __irq_svc:
202 svc_entry
204 #ifdef CONFIG_TRACE_IRQFLAGS
205 bl trace_hardirqs_off
206 #endif
207 #ifdef CONFIG_PREEMPT
208 get_thread_info tsk
209 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
210 add r7, r8, #1 @ increment it
211 str r7, [tsk, #TI_PREEMPT]
212 #endif
214 irq_handler
215 #ifdef CONFIG_PREEMPT
216 str r8, [tsk, #TI_PREEMPT] @ restore preempt count
217 ldr r0, [tsk, #TI_FLAGS] @ get flags
218 teq r8, #0 @ if preempt count != 0
219 movne r0, #0 @ force flags to 0
220 tst r0, #_TIF_NEED_RESCHED
221 blne svc_preempt
222 #endif
223 ldr r4, [sp, #S_PSR] @ irqs are already disabled
224 #ifdef CONFIG_TRACE_IRQFLAGS
225 tst r4, #PSR_I_BIT
226 bleq trace_hardirqs_on
227 #endif
228 svc_exit r4 @ return from exception
229 UNWIND(.fnend )
230 ENDPROC(__irq_svc)
232 .ltorg
234 #ifdef CONFIG_PREEMPT
235 svc_preempt:
236 mov r8, lr
237 1: bl preempt_schedule_irq @ irq en/disable is done inside
238 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
239 tst r0, #_TIF_NEED_RESCHED
240 moveq pc, r8 @ go again
241 b 1b
242 #endif
244 .align 5
245 __und_svc:
246 #ifdef CONFIG_KPROBES
247 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
248 @ it obviously needs free stack space which then will belong to
249 @ the saved context.
250 svc_entry 64
251 #else
252 svc_entry
253 #endif
255 @
256 @ call emulation code, which returns using r9 if it has emulated
257 @ the instruction, or the more conventional lr if we are to treat
258 @ this as a real undefined instruction
259 @
260 @ r0 - instruction
261 @
262 #ifndef CONFIG_THUMB2_KERNEL
263 ldr r0, [r2, #-4]
264 #else
265 ldrh r0, [r2, #-2] @ Thumb instruction at LR - 2
266 and r9, r0, #0xf800
267 cmp r9, #0xe800 @ 32-bit instruction if xx >= 0
268 ldrhhs r9, [r2] @ bottom 16 bits
269 orrhs r0, r9, r0, lsl #16
270 #endif
271 adr r9, BSYM(1f)
272 bl call_fpe
274 mov r0, sp @ struct pt_regs *regs
275 bl do_undefinstr
277 @
278 @ IRQs off again before pulling preserved data off the stack
279 @
280 1: disable_irq_notrace
282 @
283 @ restore SPSR and restart the instruction
284 @
285 ldr r2, [sp, #S_PSR] @ Get SVC cpsr
286 svc_exit r2 @ return from exception
287 UNWIND(.fnend )
288 ENDPROC(__und_svc)
290 .align 5
291 __pabt_svc:
292 svc_entry
294 @
295 @ re-enable interrupts if appropriate
296 @
297 mrs r9, cpsr
298 tst r3, #PSR_I_BIT
299 biceq r9, r9, #PSR_I_BIT
301 mov r0, r2 @ pass address of aborted instruction.
302 #ifdef MULTI_PABORT
303 ldr r4, .LCprocfns
304 mov lr, pc
305 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
306 #else
307 bl CPU_PABORT_HANDLER
308 #endif
309 debug_entry r1
310 msr cpsr_c, r9 @ Maybe enable interrupts
311 mov r2, sp @ regs
312 bl do_PrefetchAbort @ call abort handler
314 @
315 @ IRQs off again before pulling preserved data off the stack
316 @
317 disable_irq_notrace
319 @
320 @ restore SPSR and restart the instruction
321 @
322 ldr r2, [sp, #S_PSR]
323 svc_exit r2 @ return from exception
324 UNWIND(.fnend )
325 ENDPROC(__pabt_svc)
327 .align 5
328 .LCcralign:
329 .word cr_alignment
330 #ifdef MULTI_DABORT
331 .LCprocfns:
332 .word processor
333 #endif
334 .LCfp:
335 .word fp_enter
337 /*
338 * User mode handlers
339 *
340 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
341 */
343 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
344 #error "sizeof(struct pt_regs) must be a multiple of 8"
345 #endif
347 .macro usr_entry
348 UNWIND(.fnstart )
349 UNWIND(.cantunwind ) @ don't unwind the user space
350 sub sp, sp, #S_FRAME_SIZE
351 ARM( stmib sp, {r1 - r12} )
352 THUMB( stmia sp, {r0 - r12} )
354 ldmia r0, {r1 - r3}
355 add r0, sp, #S_PC @ here for interlock avoidance
356 mov r4, #-1 @ "" "" "" ""
358 str r1, [sp] @ save the "real" r0 copied
359 @ from the exception stack
361 @
362 @ We are now ready to fill in the remaining blanks on the stack:
363 @
364 @ r2 - lr_<exception>, already fixed up for correct return/restart
365 @ r3 - spsr_<exception>
366 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
367 @
368 @ Also, separately save sp_usr and lr_usr
369 @
370 stmia r0, {r2 - r4}
371 ARM( stmdb r0, {sp, lr}^ )
372 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
374 @
375 @ Enable the alignment trap while in kernel mode
376 @
377 alignment_trap r0
379 @
380 @ Clear FP to mark the first stack frame
381 @
382 zero_fp
383 .endm
385 .macro kuser_cmpxchg_check
386 #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
387 #ifndef CONFIG_MMU
388 #warning "NPTL on non MMU needs fixing"
389 #else
390 @ Make sure our user space atomic helper is restarted
391 @ if it was interrupted in a critical region. Here we
392 @ perform a quick test inline since it should be false
393 @ 99.9999% of the time. The rest is done out of line.
394 cmp r2, #TASK_SIZE
395 blhs kuser_cmpxchg_fixup
396 #endif
397 #endif
398 .endm
400 .align 5
401 __dabt_usr:
402 usr_entry
403 kuser_cmpxchg_check
405 @
406 @ Call the processor-specific abort handler:
407 @
408 @ r2 - aborted context pc
409 @ r3 - aborted context cpsr
410 @
411 @ The abort handler must return the aborted address in r0, and
412 @ the fault status register in r1.
413 @
414 #ifdef MULTI_DABORT
415 ldr r4, .LCprocfns
416 mov lr, pc
417 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
418 #else
419 bl CPU_DABORT_HANDLER
420 #endif
422 @
423 @ IRQs on, then call the main handler
424 @
425 debug_entry r1
426 enable_irq
427 mov r2, sp
428 adr lr, BSYM(ret_from_exception)
429 b do_DataAbort
430 UNWIND(.fnend )
431 ENDPROC(__dabt_usr)
433 .align 5
434 __irq_usr:
435 usr_entry
436 kuser_cmpxchg_check
438 get_thread_info tsk
439 #ifdef CONFIG_PREEMPT
440 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
441 add r7, r8, #1 @ increment it
442 str r7, [tsk, #TI_PREEMPT]
443 #endif
445 irq_handler
446 #ifdef CONFIG_PREEMPT
447 ldr r0, [tsk, #TI_PREEMPT]
448 str r8, [tsk, #TI_PREEMPT]
449 teq r0, r7
450 ARM( strne r0, [r0, -r0] )
451 THUMB( movne r0, #0 )
452 THUMB( strne r0, [r0] )
453 #endif
455 mov why, #0
456 b ret_to_user
457 UNWIND(.fnend )
458 ENDPROC(__irq_usr)
460 .ltorg
462 .align 5
463 __und_usr:
464 usr_entry
466 @
467 @ fall through to the emulation code, which returns using r9 if
468 @ it has emulated the instruction, or the more conventional lr
469 @ if we are to treat this as a real undefined instruction
470 @
471 @ r0 - instruction
472 @
473 adr r9, BSYM(ret_from_exception)
474 adr lr, BSYM(__und_usr_unknown)
475 tst r3, #PSR_T_BIT @ Thumb mode?
476 itet eq @ explicit IT needed for the 1f label
477 subeq r4, r2, #4 @ ARM instr at LR - 4
478 subne r4, r2, #2 @ Thumb instr at LR - 2
479 1: ldreqt r0, [r4]
480 #ifdef CONFIG_CPU_ENDIAN_BE8
481 reveq r0, r0 @ little endian instruction
482 #endif
483 beq call_fpe
484 @ Thumb instruction
485 #if __LINUX_ARM_ARCH__ >= 7
486 2:
487 ARM( ldrht r5, [r4], #2 )
488 THUMB( ldrht r5, [r4] )
489 THUMB( add r4, r4, #2 )
490 and r0, r5, #0xf800 @ mask bits 111x x... .... ....
491 cmp r0, #0xe800 @ 32bit instruction if xx != 0
492 blo __und_usr_unknown
493 3: ldrht r0, [r4]
494 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
495 orr r0, r0, r5, lsl #16
496 #else
497 b __und_usr_unknown
498 #endif
499 UNWIND(.fnend )
500 ENDPROC(__und_usr)
502 @
503 @ fallthrough to call_fpe
504 @
506 /*
507 * The out of line fixup for the ldrt above.
508 */
509 .pushsection .fixup, "ax"
510 4: mov pc, r9
511 .popsection
512 .pushsection __ex_table,"a"
513 .long 1b, 4b
514 #if __LINUX_ARM_ARCH__ >= 7
515 .long 2b, 4b
516 .long 3b, 4b
517 #endif
518 .popsection
520 /*
521 * Check whether the instruction is a co-processor instruction.
522 * If yes, we need to call the relevant co-processor handler.
523 *
524 * Note that we don't do a full check here for the co-processor
525 * instructions; all instructions with bit 27 set are well
526 * defined. The only instructions that should fault are the
527 * co-processor instructions. However, we have to watch out
528 * for the ARM6/ARM7 SWI bug.
529 *
530 * NEON is a special case that has to be handled here. Not all
531 * NEON instructions are co-processor instructions, so we have
532 * to make a special case of checking for them. Plus, there's
533 * five groups of them, so we have a table of mask/opcode pairs
534 * to check against, and if any match then we branch off into the
535 * NEON handler code.
536 *
537 * Emulators may wish to make use of the following registers:
538 * r0 = instruction opcode.
539 * r2 = PC+4
540 * r9 = normal "successful" return address
541 * r10 = this threads thread_info structure.
542 * lr = unrecognised instruction return address
543 */
544 @
545 @ Fall-through from Thumb-2 __und_usr
546 @
547 #ifdef CONFIG_NEON
548 adr r6, .LCneon_thumb_opcodes
549 b 2f
550 #endif
551 call_fpe:
552 #ifdef CONFIG_NEON
553 adr r6, .LCneon_arm_opcodes
554 2:
555 ldr r7, [r6], #4 @ mask value
556 cmp r7, #0 @ end mask?
557 beq 1f
558 and r8, r0, r7
559 ldr r7, [r6], #4 @ opcode bits matching in mask
560 cmp r8, r7 @ NEON instruction?
561 bne 2b
562 get_thread_info r10
563 mov r7, #1
564 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
565 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
566 b do_vfp @ let VFP handler handle this
567 1:
568 #endif
569 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
570 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
571 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
572 and r8, r0, #0x0f000000 @ mask out op-code bits
573 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
574 #endif
575 moveq pc, lr
576 get_thread_info r10 @ get current thread
577 and r8, r0, #0x00000f00 @ mask out CP number
578 THUMB( lsr r8, r8, #8 )
579 mov r7, #1
580 add r6, r10, #TI_USED_CP
581 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
582 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
583 #ifdef CONFIG_IWMMXT
584 @ Test if we need to give access to iWMMXt coprocessors
585 ldr r5, [r10, #TI_FLAGS]
586 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
587 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
588 bcs iwmmxt_task_enable
589 #endif
590 ARM( add pc, pc, r8, lsr #6 )
591 THUMB( lsl r8, r8, #2 )
592 THUMB( add pc, r8 )
593 nop
595 movw_pc lr @ CP#0
596 W(b) do_fpe @ CP#1 (FPE)
597 W(b) do_fpe @ CP#2 (FPE)
598 movw_pc lr @ CP#3
599 #ifdef CONFIG_CRUNCH
600 b crunch_task_enable @ CP#4 (MaverickCrunch)
601 b crunch_task_enable @ CP#5 (MaverickCrunch)
602 b crunch_task_enable @ CP#6 (MaverickCrunch)
603 #else
604 movw_pc lr @ CP#4
605 movw_pc lr @ CP#5
606 movw_pc lr @ CP#6
607 #endif
608 movw_pc lr @ CP#7
609 movw_pc lr @ CP#8
610 movw_pc lr @ CP#9
611 #ifdef CONFIG_VFP
612 W(b) do_vfp @ CP#10 (VFP)
613 W(b) do_vfp @ CP#11 (VFP)
614 #else
615 movw_pc lr @ CP#10 (VFP)
616 movw_pc lr @ CP#11 (VFP)
617 #endif
618 movw_pc lr @ CP#12
619 movw_pc lr @ CP#13
620 movw_pc lr @ CP#14 (Debug)
621 movw_pc lr @ CP#15 (Control)
623 #ifdef CONFIG_NEON
624 .align 6
626 .LCneon_arm_opcodes:
627 .word 0xfe000000 @ mask
628 .word 0xf2000000 @ opcode
630 .word 0xff100000 @ mask
631 .word 0xf4000000 @ opcode
633 .word 0x00000000 @ mask
634 .word 0x00000000 @ opcode
636 .LCneon_thumb_opcodes:
637 .word 0xef000000 @ mask
638 .word 0xef000000 @ opcode
640 .word 0xff100000 @ mask
641 .word 0xf9000000 @ opcode
643 .word 0x00000000 @ mask
644 .word 0x00000000 @ opcode
645 #endif
647 do_fpe:
648 enable_irq
649 ldr r4, .LCfp
650 add r10, r10, #TI_FPSTATE @ r10 = workspace
651 ldr pc, [r4] @ Call FP module USR entry point
653 /*
654 * The FP module is called with these registers set:
655 * r0 = instruction
656 * r2 = PC+4
657 * r9 = normal "successful" return address
658 * r10 = FP workspace
659 * lr = unrecognised FP instruction return address
660 */
662 .pushsection .data
663 ENTRY(fp_enter)
664 .word no_fp
665 .popsection
667 ENTRY(no_fp)
668 mov pc, lr
669 ENDPROC(no_fp)
671 __und_usr_unknown:
672 enable_irq
673 mov r0, sp
674 adr lr, BSYM(ret_from_exception)
675 b do_undefinstr
676 ENDPROC(__und_usr_unknown)
678 .align 5
679 __pabt_usr:
680 usr_entry
682 mov r0, r2 @ pass address of aborted instruction.
683 #ifdef MULTI_PABORT
684 ldr r4, .LCprocfns
685 mov lr, pc
686 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
687 #else
688 bl CPU_PABORT_HANDLER
689 #endif
690 debug_entry r1
691 enable_irq @ Enable interrupts
692 mov r2, sp @ regs
693 bl do_PrefetchAbort @ call abort handler
694 UNWIND(.fnend )
695 /* fall through */
696 /*
697 * This is the return code to user mode for abort handlers
698 */
699 ENTRY(ret_from_exception)
700 UNWIND(.fnstart )
701 UNWIND(.cantunwind )
702 get_thread_info tsk
703 mov why, #0
704 b ret_to_user
705 UNWIND(.fnend )
706 ENDPROC(__pabt_usr)
707 ENDPROC(ret_from_exception)
709 /*
710 * Register switch for ARMv3 and ARMv4 processors
711 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
712 * previous and next are guaranteed not to be the same.
713 */
714 ENTRY(__switch_to)
715 UNWIND(.fnstart )
716 UNWIND(.cantunwind )
717 add ip, r1, #TI_CPU_SAVE
718 ldr r3, [r2, #TI_TP_VALUE]
719 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
720 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
721 THUMB( str sp, [ip], #4 )
722 THUMB( str lr, [ip], #4 )
723 #ifdef CONFIG_CPU_USE_DOMAINS
724 ldr r6, [r2, #TI_CPU_DOMAIN]
725 #endif
726 set_tls r3, r4, r5
727 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
728 ldr r7, [r2, #TI_TASK]
729 ldr r8, =__stack_chk_guard
730 ldr r7, [r7, #TSK_STACK_CANARY]
731 #endif
732 #ifdef CONFIG_CPU_USE_DOMAINS
733 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
734 #endif
735 mov r5, r0
736 add r4, r2, #TI_CPU_SAVE
737 ldr r0, =thread_notify_head
738 mov r1, #THREAD_NOTIFY_SWITCH
739 bl atomic_notifier_call_chain
740 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
741 str r7, [r8]
742 #endif
743 THUMB( mov ip, r4 )
744 mov r0, r5
745 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
746 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
747 THUMB( ldr sp, [ip], #4 )
748 THUMB( ldr pc, [ip] )
749 UNWIND(.fnend )
750 ENDPROC(__switch_to)
752 __INIT
754 /*
755 * User helpers.
756 *
757 * These are segment of kernel provided user code reachable from user space
758 * at a fixed address in kernel memory. This is used to provide user space
759 * with some operations which require kernel help because of unimplemented
760 * native feature and/or instructions in many ARM CPUs. The idea is for
761 * this code to be executed directly in user mode for best efficiency but
762 * which is too intimate with the kernel counter part to be left to user
763 * libraries. In fact this code might even differ from one CPU to another
764 * depending on the available instruction set and restrictions like on
765 * SMP systems. In other words, the kernel reserves the right to change
766 * this code as needed without warning. Only the entry points and their
767 * results are guaranteed to be stable.
768 *
769 * Each segment is 32-byte aligned and will be moved to the top of the high
770 * vector page. New segments (if ever needed) must be added in front of
771 * existing ones. This mechanism should be used only for things that are
772 * really small and justified, and not be abused freely.
773 *
774 * User space is expected to implement those things inline when optimizing
775 * for a processor that has the necessary native support, but only if such
776 * resulting binaries are already to be incompatible with earlier ARM
777 * processors due to the use of unsupported instructions other than what
778 * is provided here. In other words don't make binaries unable to run on
779 * earlier processors just for the sake of not using these kernel helpers
780 * if your compiled code is not going to use the new instructions for other
781 * purpose.
782 */
783 THUMB( .arm )
785 .macro usr_ret, reg
786 #ifdef CONFIG_ARM_THUMB
787 bx \reg
788 #else
789 mov pc, \reg
790 #endif
791 .endm
793 .align 5
794 .globl __kuser_helper_start
795 __kuser_helper_start:
797 /*
798 * Reference prototype:
799 *
800 * void __kernel_memory_barrier(void)
801 *
802 * Input:
803 *
804 * lr = return address
805 *
806 * Output:
807 *
808 * none
809 *
810 * Clobbered:
811 *
812 * none
813 *
814 * Definition and user space usage example:
815 *
816 * typedef void (__kernel_dmb_t)(void);
817 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
818 *
819 * Apply any needed memory barrier to preserve consistency with data modified
820 * manually and __kuser_cmpxchg usage.
821 *
822 * This could be used as follows:
823 *
824 * #define __kernel_dmb() \
825 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \
826 * : : : "r0", "lr","cc" )
827 */
829 __kuser_memory_barrier: @ 0xffff0fa0
830 smp_dmb arm
831 usr_ret lr
833 .align 5
835 /*
836 * Reference prototype:
837 *
838 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
839 *
840 * Input:
841 *
842 * r0 = oldval
843 * r1 = newval
844 * r2 = ptr
845 * lr = return address
846 *
847 * Output:
848 *
849 * r0 = returned value (zero or non-zero)
850 * C flag = set if r0 == 0, clear if r0 != 0
851 *
852 * Clobbered:
853 *
854 * r3, ip, flags
855 *
856 * Definition and user space usage example:
857 *
858 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
859 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
860 *
861 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
862 * Return zero if *ptr was changed or non-zero if no exchange happened.
863 * The C flag is also set if *ptr was changed to allow for assembly
864 * optimization in the calling code.
865 *
866 * Notes:
867 *
868 * - This routine already includes memory barriers as needed.
869 *
870 * For example, a user space atomic_add implementation could look like this:
871 *
872 * #define atomic_add(ptr, val) \
873 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
874 * register unsigned int __result asm("r1"); \
875 * asm volatile ( \
876 * "1: @ atomic_add\n\t" \
877 * "ldr r0, [r2]\n\t" \
878 * "mov r3, #0xffff0fff\n\t" \
879 * "add lr, pc, #4\n\t" \
880 * "add r1, r0, %2\n\t" \
881 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
882 * "bcc 1b" \
883 * : "=&r" (__result) \
884 * : "r" (__ptr), "rIL" (val) \
885 * : "r0","r3","ip","lr","cc","memory" ); \
886 * __result; })
887 */
889 __kuser_cmpxchg: @ 0xffff0fc0
891 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
893 /*
894 * Poor you. No fast solution possible...
895 * The kernel itself must perform the operation.
896 * A special ghost syscall is used for that (see traps.c).
897 */
898 stmfd sp!, {r7, lr}
899 ldr r7, 1f @ it's 20 bits
900 swi __ARM_NR_cmpxchg
901 ldmfd sp!, {r7, pc}
902 1: .word __ARM_NR_cmpxchg
904 #elif __LINUX_ARM_ARCH__ < 6
906 #ifdef CONFIG_MMU
908 /*
909 * The only thing that can break atomicity in this cmpxchg
910 * implementation is either an IRQ or a data abort exception
911 * causing another process/thread to be scheduled in the middle
912 * of the critical sequence. To prevent this, code is added to
913 * the IRQ and data abort exception handlers to set the pc back
914 * to the beginning of the critical section if it is found to be
915 * within that critical section (see kuser_cmpxchg_fixup).
916 */
917 1: ldr r3, [r2] @ load current val
918 subs r3, r3, r0 @ compare with oldval
919 2: streq r1, [r2] @ store newval if eq
920 rsbs r0, r3, #0 @ set return val and C flag
921 usr_ret lr
923 .text
924 kuser_cmpxchg_fixup:
925 @ Called from kuser_cmpxchg_check macro.
926 @ r2 = address of interrupted insn (must be preserved).
927 @ sp = saved regs. r7 and r8 are clobbered.
928 @ 1b = first critical insn, 2b = last critical insn.
929 @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b.
930 mov r7, #0xffff0fff
931 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
932 subs r8, r2, r7
933 rsbcss r8, r8, #(2b - 1b)
934 strcs r7, [sp, #S_PC]
935 mov pc, lr
936 .previous
938 #else
939 #warning "NPTL on non MMU needs fixing"
940 mov r0, #-1
941 adds r0, r0, #0
942 usr_ret lr
943 #endif
945 #else
947 smp_dmb arm
948 1: ldrex r3, [r2]
949 subs r3, r3, r0
950 strexeq r3, r1, [r2]
951 teqeq r3, #1
952 beq 1b
953 rsbs r0, r3, #0
954 /* beware -- each __kuser slot must be 8 instructions max */
955 ALT_SMP(b __kuser_memory_barrier)
956 ALT_UP(usr_ret lr)
958 #endif
960 .align 5
962 /*
963 * Reference prototype:
964 *
965 * int __kernel_get_tls(void)
966 *
967 * Input:
968 *
969 * lr = return address
970 *
971 * Output:
972 *
973 * r0 = TLS value
974 *
975 * Clobbered:
976 *
977 * none
978 *
979 * Definition and user space usage example:
980 *
981 * typedef int (__kernel_get_tls_t)(void);
982 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
983 *
984 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
985 *
986 * This could be used as follows:
987 *
988 * #define __kernel_get_tls() \
989 * ({ register unsigned int __val asm("r0"); \
990 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
991 * : "=r" (__val) : : "lr","cc" ); \
992 * __val; })
993 */
995 __kuser_get_tls: @ 0xffff0fe0
996 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
997 usr_ret lr
998 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
999 .rep 4
1000 .word 0 @ 0xffff0ff0 software TLS value, then
1001 .endr @ pad up to __kuser_helper_version
1003 /*
1004 * Reference declaration:
1005 *
1006 * extern unsigned int __kernel_helper_version;
1007 *
1008 * Definition and user space usage example:
1009 *
1010 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
1011 *
1012 * User space may read this to determine the curent number of helpers
1013 * available.
1014 */
1016 __kuser_helper_version: @ 0xffff0ffc
1017 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
1019 .globl __kuser_helper_end
1020 __kuser_helper_end:
1022 THUMB( .thumb )
1024 /*
1025 * Vector stubs.
1026 *
1027 * This code is copied to 0xffff0200 so we can use branches in the
1028 * vectors, rather than ldr's. Note that this code must not
1029 * exceed 0x300 bytes.
1030 *
1031 * Common stub entry macro:
1032 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1033 *
1034 * SP points to a minimal amount of processor-private memory, the address
1035 * of which is copied into r0 for the mode specific abort handler.
1036 */
1037 .macro vector_stub, name, mode, correction=0
1038 .align 5
1040 vector_\name:
1041 .if \correction
1042 sub lr, lr, #\correction
1043 .endif
1045 @
1046 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1047 @ (parent CPSR)
1048 @
1049 stmia sp, {r0, lr} @ save r0, lr
1050 mrs lr, spsr
1051 str lr, [sp, #8] @ save spsr
1053 @
1054 @ Prepare for SVC32 mode. IRQs remain disabled.
1055 @
1056 mrs r0, cpsr
1057 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
1058 msr spsr_cxsf, r0
1060 @
1061 @ the branch table must immediately follow this code
1062 @
1063 and lr, lr, #0x0f
1064 THUMB( adr r0, 1f )
1065 THUMB( ldr lr, [r0, lr, lsl #2] )
1066 mov r0, sp
1067 ARM( ldr lr, [pc, lr, lsl #2] )
1068 movs pc, lr @ branch to handler in SVC mode
1069 ENDPROC(vector_\name)
1071 .align 2
1072 @ handler addresses follow this label
1073 1:
1074 .endm
1076 .globl __stubs_start
1077 __stubs_start:
1078 /*
1079 * Interrupt dispatcher
1080 */
1081 vector_stub irq, IRQ_MODE, 4
1083 .long __irq_usr @ 0 (USR_26 / USR_32)
1084 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1085 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1086 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1087 .long __irq_invalid @ 4
1088 .long __irq_invalid @ 5
1089 .long __irq_invalid @ 6
1090 .long __irq_invalid @ 7
1091 .long __irq_invalid @ 8
1092 .long __irq_invalid @ 9
1093 .long __irq_invalid @ a
1094 .long __irq_invalid @ b
1095 .long __irq_invalid @ c
1096 .long __irq_invalid @ d
1097 .long __irq_invalid @ e
1098 .long __irq_invalid @ f
1100 /*
1101 * Data abort dispatcher
1102 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1103 */
1104 vector_stub dabt, ABT_MODE, 8
1106 .long __dabt_usr @ 0 (USR_26 / USR_32)
1107 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1108 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1109 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1110 .long __dabt_invalid @ 4
1111 .long __dabt_invalid @ 5
1112 .long __dabt_invalid @ 6
1113 .long __dabt_invalid @ 7
1114 .long __dabt_invalid @ 8
1115 .long __dabt_invalid @ 9
1116 .long __dabt_invalid @ a
1117 .long __dabt_invalid @ b
1118 .long __dabt_invalid @ c
1119 .long __dabt_invalid @ d
1120 .long __dabt_invalid @ e
1121 .long __dabt_invalid @ f
1123 /*
1124 * Prefetch abort dispatcher
1125 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1126 */
1127 vector_stub pabt, ABT_MODE, 4
1129 .long __pabt_usr @ 0 (USR_26 / USR_32)
1130 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1131 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1132 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1133 .long __pabt_invalid @ 4
1134 .long __pabt_invalid @ 5
1135 .long __pabt_invalid @ 6
1136 .long __pabt_invalid @ 7
1137 .long __pabt_invalid @ 8
1138 .long __pabt_invalid @ 9
1139 .long __pabt_invalid @ a
1140 .long __pabt_invalid @ b
1141 .long __pabt_invalid @ c
1142 .long __pabt_invalid @ d
1143 .long __pabt_invalid @ e
1144 .long __pabt_invalid @ f
1146 /*
1147 * Undef instr entry dispatcher
1148 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1149 */
1150 vector_stub und, UND_MODE
1152 .long __und_usr @ 0 (USR_26 / USR_32)
1153 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1154 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1155 .long __und_svc @ 3 (SVC_26 / SVC_32)
1156 .long __und_invalid @ 4
1157 .long __und_invalid @ 5
1158 .long __und_invalid @ 6
1159 .long __und_invalid @ 7
1160 .long __und_invalid @ 8
1161 .long __und_invalid @ 9
1162 .long __und_invalid @ a
1163 .long __und_invalid @ b
1164 .long __und_invalid @ c
1165 .long __und_invalid @ d
1166 .long __und_invalid @ e
1167 .long __und_invalid @ f
1169 .align 5
1171 /*=============================================================================
1172 * Undefined FIQs
1173 *-----------------------------------------------------------------------------
1174 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1175 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1176 * Basically to switch modes, we *HAVE* to clobber one register... brain
1177 * damage alert! I don't think that we can execute any code in here in any
1178 * other mode than FIQ... Ok you can switch to another mode, but you can't
1179 * get out of that mode without clobbering one register.
1180 */
1181 vector_fiq:
1182 disable_fiq
1183 subs pc, lr, #4
1185 /*=============================================================================
1186 * Address exception handler
1187 *-----------------------------------------------------------------------------
1188 * These aren't too critical.
1189 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1190 */
1192 vector_addrexcptn:
1193 b vector_addrexcptn
1195 /*
1196 * We group all the following data together to optimise
1197 * for CPUs with separate I & D caches.
1198 */
1199 .align 5
1201 .LCvswi:
1202 .word vector_swi
1204 .globl __stubs_end
1205 __stubs_end:
1207 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
1209 .globl __vectors_start
1210 __vectors_start:
1211 ARM( swi SYS_ERROR0 )
1212 THUMB( svc #0 )
1213 THUMB( nop )
1214 W(b) vector_und + stubs_offset
1215 W(ldr) pc, .LCvswi + stubs_offset
1216 W(b) vector_pabt + stubs_offset
1217 W(b) vector_dabt + stubs_offset
1218 W(b) vector_addrexcptn + stubs_offset
1219 W(b) vector_irq + stubs_offset
1220 W(b) vector_fiq + stubs_offset
1222 .globl __vectors_end
1223 __vectors_end:
1225 .data
1227 .globl cr_alignment
1228 .globl cr_no_alignment
1229 cr_alignment:
1230 .space 4
1231 cr_no_alignment:
1232 .space 4
1234 #ifdef CONFIG_MULTI_IRQ_HANDLER
1235 .globl handle_arch_irq
1236 handle_arch_irq:
1237 .space 4
1238 #endif