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regulator, mc13xxx: Remove pointless test for unsigned less than zero
[zen-stable.git] / arch / arm / mach-omap2 / clock3xxx_data.c
blob403a4a1d3f9c4d0e4362cd768c2781dc32329ec1
1 /*
2 * OMAP3 clock data
3 *
4 * Copyright (C) 2007-2010 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
10 *
11 */
12
13 /*
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/clk.h>
21 #include <linux/list.h>
22
23 #include <plat/clkdev_omap.h>
24
25 #include "clock.h"
26 #include "clock3xxx.h"
27 #include "clock34xx.h"
28 #include "clock36xx.h"
29 #include "clock3517.h"
30
31 #include "cm2xxx_3xxx.h"
32 #include "cm-regbits-34xx.h"
33 #include "prm2xxx_3xxx.h"
34 #include "prm-regbits-34xx.h"
35 #include "control.h"
36
37 /*
38 * clocks
39 */
40
41 #define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
42
43 /* Maximum DPLL multiplier, divider values for OMAP3 */
44 #define OMAP3_MAX_DPLL_MULT 2047
45 #define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
46 #define OMAP3_MAX_DPLL_DIV 128
47
48 /*
49 * DPLL1 supplies clock to the MPU.
50 * DPLL2 supplies clock to the IVA2.
51 * DPLL3 supplies CORE domain clocks.
52 * DPLL4 supplies peripheral clocks.
53 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
54 */
55
56 /* Forward declarations for DPLL bypass clocks */
57 static struct clk dpll1_fck;
58 static struct clk dpll2_fck;
59
60 /* PRM CLOCKS */
61
62 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
63 static struct clk omap_32k_fck = {
64 .name = "omap_32k_fck",
65 .ops = &clkops_null,
66 .rate = 32768,
67 };
68
69 static struct clk secure_32k_fck = {
70 .name = "secure_32k_fck",
71 .ops = &clkops_null,
72 .rate = 32768,
73 };
74
75 /* Virtual source clocks for osc_sys_ck */
76 static struct clk virt_12m_ck = {
77 .name = "virt_12m_ck",
78 .ops = &clkops_null,
79 .rate = 12000000,
80 };
81
82 static struct clk virt_13m_ck = {
83 .name = "virt_13m_ck",
84 .ops = &clkops_null,
85 .rate = 13000000,
86 };
87
88 static struct clk virt_16_8m_ck = {
89 .name = "virt_16_8m_ck",
90 .ops = &clkops_null,
91 .rate = 16800000,
92 };
93
94 static struct clk virt_19_2m_ck = {
95 .name = "virt_19_2m_ck",
96 .ops = &clkops_null,
97 .rate = 19200000,
98 };
99
100 static struct clk virt_26m_ck = {
101 .name = "virt_26m_ck",
102 .ops = &clkops_null,
103 .rate = 26000000,
104 };
105
106 static struct clk virt_38_4m_ck = {
107 .name = "virt_38_4m_ck",
108 .ops = &clkops_null,
109 .rate = 38400000,
110 };
111
112 static const struct clksel_rate osc_sys_12m_rates[] = {
113 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
114 { .div = 0 }
115 };
116
117 static const struct clksel_rate osc_sys_13m_rates[] = {
118 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
119 { .div = 0 }
120 };
121
122 static const struct clksel_rate osc_sys_16_8m_rates[] = {
123 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
124 { .div = 0 }
125 };
126
127 static const struct clksel_rate osc_sys_19_2m_rates[] = {
128 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
129 { .div = 0 }
130 };
131
132 static const struct clksel_rate osc_sys_26m_rates[] = {
133 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
134 { .div = 0 }
135 };
136
137 static const struct clksel_rate osc_sys_38_4m_rates[] = {
138 { .div = 1, .val = 4, .flags = RATE_IN_3XXX },
139 { .div = 0 }
140 };
141
142 static const struct clksel osc_sys_clksel[] = {
143 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
144 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
145 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
146 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
147 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
148 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
149 { .parent = NULL },
150 };
151
152 /* Oscillator clock */
153 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
154 static struct clk osc_sys_ck = {
155 .name = "osc_sys_ck",
156 .ops = &clkops_null,
157 .init = &omap2_init_clksel_parent,
158 .clksel_reg = OMAP3430_PRM_CLKSEL,
159 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
160 .clksel = osc_sys_clksel,
161 /* REVISIT: deal with autoextclkmode? */
162 .recalc = &omap2_clksel_recalc,
163 };
164
165 static const struct clksel_rate div2_rates[] = {
166 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
167 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
168 { .div = 0 }
169 };
170
171 static const struct clksel sys_clksel[] = {
172 { .parent = &osc_sys_ck, .rates = div2_rates },
173 { .parent = NULL }
174 };
175
176 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
177 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
178 static struct clk sys_ck = {
179 .name = "sys_ck",
180 .ops = &clkops_null,
181 .parent = &osc_sys_ck,
182 .init = &omap2_init_clksel_parent,
183 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
184 .clksel_mask = OMAP_SYSCLKDIV_MASK,
185 .clksel = sys_clksel,
186 .recalc = &omap2_clksel_recalc,
187 };
188
189 static struct clk sys_altclk = {
190 .name = "sys_altclk",
191 .ops = &clkops_null,
192 };
193
194 /* Optional external clock input for some McBSPs */
195 static struct clk mcbsp_clks = {
196 .name = "mcbsp_clks",
197 .ops = &clkops_null,
198 };
199
200 /* PRM EXTERNAL CLOCK OUTPUT */
201
202 static struct clk sys_clkout1 = {
203 .name = "sys_clkout1",
204 .ops = &clkops_omap2_dflt,
205 .parent = &osc_sys_ck,
206 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
207 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
208 .recalc = &followparent_recalc,
209 };
210
211 /* DPLLS */
212
213 /* CM CLOCKS */
214
215 static const struct clksel_rate div16_dpll_rates[] = {
216 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
217 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
218 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
219 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
220 { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
221 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
222 { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
223 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
224 { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
225 { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
226 { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
227 { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
228 { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
229 { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
230 { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
231 { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
232 { .div = 0 }
233 };
234
235 static const struct clksel_rate dpll4_rates[] = {
236 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
237 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
238 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
239 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
240 { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
241 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
242 { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
243 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
244 { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
245 { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
246 { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
247 { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
248 { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
249 { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
250 { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
251 { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
252 { .div = 17, .val = 17, .flags = RATE_IN_36XX },
253 { .div = 18, .val = 18, .flags = RATE_IN_36XX },
254 { .div = 19, .val = 19, .flags = RATE_IN_36XX },
255 { .div = 20, .val = 20, .flags = RATE_IN_36XX },
256 { .div = 21, .val = 21, .flags = RATE_IN_36XX },
257 { .div = 22, .val = 22, .flags = RATE_IN_36XX },
258 { .div = 23, .val = 23, .flags = RATE_IN_36XX },
259 { .div = 24, .val = 24, .flags = RATE_IN_36XX },
260 { .div = 25, .val = 25, .flags = RATE_IN_36XX },
261 { .div = 26, .val = 26, .flags = RATE_IN_36XX },
262 { .div = 27, .val = 27, .flags = RATE_IN_36XX },
263 { .div = 28, .val = 28, .flags = RATE_IN_36XX },
264 { .div = 29, .val = 29, .flags = RATE_IN_36XX },
265 { .div = 30, .val = 30, .flags = RATE_IN_36XX },
266 { .div = 31, .val = 31, .flags = RATE_IN_36XX },
267 { .div = 32, .val = 32, .flags = RATE_IN_36XX },
268 { .div = 0 }
269 };
270
271 /* DPLL1 */
272 /* MPU clock source */
273 /* Type: DPLL */
274 static struct dpll_data dpll1_dd = {
275 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
276 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
277 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
278 .clk_bypass = &dpll1_fck,
279 .clk_ref = &sys_ck,
280 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
281 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
282 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
283 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
284 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
285 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
286 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
287 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
288 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
289 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
290 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
291 .max_multiplier = OMAP3_MAX_DPLL_MULT,
292 .min_divider = 1,
293 .max_divider = OMAP3_MAX_DPLL_DIV,
294 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
295 };
296
297 static struct clk dpll1_ck = {
298 .name = "dpll1_ck",
299 .ops = &clkops_null,
300 .parent = &sys_ck,
301 .dpll_data = &dpll1_dd,
302 .round_rate = &omap2_dpll_round_rate,
303 .set_rate = &omap3_noncore_dpll_set_rate,
304 .clkdm_name = "dpll1_clkdm",
305 .recalc = &omap3_dpll_recalc,
306 };
307
308 /*
309 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
310 * DPLL isn't bypassed.
311 */
312 static struct clk dpll1_x2_ck = {
313 .name = "dpll1_x2_ck",
314 .ops = &clkops_null,
315 .parent = &dpll1_ck,
316 .clkdm_name = "dpll1_clkdm",
317 .recalc = &omap3_clkoutx2_recalc,
318 };
319
320 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
321 static const struct clksel div16_dpll1_x2m2_clksel[] = {
322 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
323 { .parent = NULL }
324 };
325
326 /*
327 * Does not exist in the TRM - needed to separate the M2 divider from
328 * bypass selection in mpu_ck
329 */
330 static struct clk dpll1_x2m2_ck = {
331 .name = "dpll1_x2m2_ck",
332 .ops = &clkops_null,
333 .parent = &dpll1_x2_ck,
334 .init = &omap2_init_clksel_parent,
335 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
336 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
337 .clksel = div16_dpll1_x2m2_clksel,
338 .clkdm_name = "dpll1_clkdm",
339 .recalc = &omap2_clksel_recalc,
340 };
341
342 /* DPLL2 */
343 /* IVA2 clock source */
344 /* Type: DPLL */
345
346 static struct dpll_data dpll2_dd = {
347 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
348 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
349 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
350 .clk_bypass = &dpll2_fck,
351 .clk_ref = &sys_ck,
352 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
353 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
354 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
355 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
356 (1 << DPLL_LOW_POWER_BYPASS),
357 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
358 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
359 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
360 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
361 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
362 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
363 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
364 .max_multiplier = OMAP3_MAX_DPLL_MULT,
365 .min_divider = 1,
366 .max_divider = OMAP3_MAX_DPLL_DIV,
367 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
368 };
369
370 static struct clk dpll2_ck = {
371 .name = "dpll2_ck",
372 .ops = &clkops_omap3_noncore_dpll_ops,
373 .parent = &sys_ck,
374 .dpll_data = &dpll2_dd,
375 .round_rate = &omap2_dpll_round_rate,
376 .set_rate = &omap3_noncore_dpll_set_rate,
377 .clkdm_name = "dpll2_clkdm",
378 .recalc = &omap3_dpll_recalc,
379 };
380
381 static const struct clksel div16_dpll2_m2x2_clksel[] = {
382 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
383 { .parent = NULL }
384 };
385
386 /*
387 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
388 * or CLKOUTX2. CLKOUT seems most plausible.
389 */
390 static struct clk dpll2_m2_ck = {
391 .name = "dpll2_m2_ck",
392 .ops = &clkops_null,
393 .parent = &dpll2_ck,
394 .init = &omap2_init_clksel_parent,
395 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
396 OMAP3430_CM_CLKSEL2_PLL),
397 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
398 .clksel = div16_dpll2_m2x2_clksel,
399 .clkdm_name = "dpll2_clkdm",
400 .recalc = &omap2_clksel_recalc,
401 };
402
403 /*
404 * DPLL3
405 * Source clock for all interfaces and for some device fclks
406 * REVISIT: Also supports fast relock bypass - not included below
407 */
408 static struct dpll_data dpll3_dd = {
409 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
410 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
411 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
412 .clk_bypass = &sys_ck,
413 .clk_ref = &sys_ck,
414 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
415 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
416 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
417 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
418 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
419 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
420 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
421 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
422 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
423 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
424 .max_multiplier = OMAP3_MAX_DPLL_MULT,
425 .min_divider = 1,
426 .max_divider = OMAP3_MAX_DPLL_DIV,
427 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
428 };
429
430 static struct clk dpll3_ck = {
431 .name = "dpll3_ck",
432 .ops = &clkops_null,
433 .parent = &sys_ck,
434 .dpll_data = &dpll3_dd,
435 .round_rate = &omap2_dpll_round_rate,
436 .clkdm_name = "dpll3_clkdm",
437 .recalc = &omap3_dpll_recalc,
438 };
439
440 /*
441 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
442 * DPLL isn't bypassed
443 */
444 static struct clk dpll3_x2_ck = {
445 .name = "dpll3_x2_ck",
446 .ops = &clkops_null,
447 .parent = &dpll3_ck,
448 .clkdm_name = "dpll3_clkdm",
449 .recalc = &omap3_clkoutx2_recalc,
450 };
451
452 static const struct clksel_rate div31_dpll3_rates[] = {
453 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
454 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
455 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS_36XX },
456 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS_36XX },
457 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
458 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS_36XX },
459 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS_36XX },
460 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS_36XX },
461 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS_36XX },
462 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS_36XX },
463 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS_36XX },
464 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS_36XX },
465 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS_36XX },
466 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS_36XX },
467 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS_36XX },
468 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS_36XX },
469 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS_36XX },
470 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS_36XX },
471 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS_36XX },
472 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS_36XX },
473 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS_36XX },
474 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS_36XX },
475 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS_36XX },
476 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS_36XX },
477 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS_36XX },
478 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS_36XX },
479 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS_36XX },
480 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS_36XX },
481 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS_36XX },
482 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS_36XX },
483 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS_36XX },
484 { .div = 0 },
485 };
486
487 static const struct clksel div31_dpll3m2_clksel[] = {
488 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
489 { .parent = NULL }
490 };
491
492 /* DPLL3 output M2 - primary control point for CORE speed */
493 static struct clk dpll3_m2_ck = {
494 .name = "dpll3_m2_ck",
495 .ops = &clkops_null,
496 .parent = &dpll3_ck,
497 .init = &omap2_init_clksel_parent,
498 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
499 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
500 .clksel = div31_dpll3m2_clksel,
501 .clkdm_name = "dpll3_clkdm",
502 .round_rate = &omap2_clksel_round_rate,
503 .set_rate = &omap3_core_dpll_m2_set_rate,
504 .recalc = &omap2_clksel_recalc,
505 };
506
507 static struct clk core_ck = {
508 .name = "core_ck",
509 .ops = &clkops_null,
510 .parent = &dpll3_m2_ck,
511 .recalc = &followparent_recalc,
512 };
513
514 static struct clk dpll3_m2x2_ck = {
515 .name = "dpll3_m2x2_ck",
516 .ops = &clkops_null,
517 .parent = &dpll3_m2_ck,
518 .clkdm_name = "dpll3_clkdm",
519 .recalc = &omap3_clkoutx2_recalc,
520 };
521
522 /* The PWRDN bit is apparently only available on 3430ES2 and above */
523 static const struct clksel div16_dpll3_clksel[] = {
524 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
525 { .parent = NULL }
526 };
527
528 /* This virtual clock is the source for dpll3_m3x2_ck */
529 static struct clk dpll3_m3_ck = {
530 .name = "dpll3_m3_ck",
531 .ops = &clkops_null,
532 .parent = &dpll3_ck,
533 .init = &omap2_init_clksel_parent,
534 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
535 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
536 .clksel = div16_dpll3_clksel,
537 .clkdm_name = "dpll3_clkdm",
538 .recalc = &omap2_clksel_recalc,
539 };
540
541 /* The PWRDN bit is apparently only available on 3430ES2 and above */
542 static struct clk dpll3_m3x2_ck = {
543 .name = "dpll3_m3x2_ck",
544 .ops = &clkops_omap2_dflt_wait,
545 .parent = &dpll3_m3_ck,
546 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
547 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
548 .flags = INVERT_ENABLE,
549 .clkdm_name = "dpll3_clkdm",
550 .recalc = &omap3_clkoutx2_recalc,
551 };
552
553 static struct clk emu_core_alwon_ck = {
554 .name = "emu_core_alwon_ck",
555 .ops = &clkops_null,
556 .parent = &dpll3_m3x2_ck,
557 .clkdm_name = "dpll3_clkdm",
558 .recalc = &followparent_recalc,
559 };
560
561 /* DPLL4 */
562 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
563 /* Type: DPLL */
564 static struct dpll_data dpll4_dd;
565
566 static struct dpll_data dpll4_dd_34xx __initdata = {
567 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
568 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
569 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
570 .clk_bypass = &sys_ck,
571 .clk_ref = &sys_ck,
572 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
573 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
574 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
575 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
576 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
577 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
578 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
579 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
580 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
581 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
582 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
583 .max_multiplier = OMAP3_MAX_DPLL_MULT,
584 .min_divider = 1,
585 .max_divider = OMAP3_MAX_DPLL_DIV,
586 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
587 };
588
589 static struct dpll_data dpll4_dd_3630 __initdata = {
590 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
591 .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK,
592 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
593 .clk_bypass = &sys_ck,
594 .clk_ref = &sys_ck,
595 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
596 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
597 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
598 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
599 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
600 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
601 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
602 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
603 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
604 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
605 .dco_mask = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
606 .sddiv_mask = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
607 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
608 .min_divider = 1,
609 .max_divider = OMAP3_MAX_DPLL_DIV,
610 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE,
611 .flags = DPLL_J_TYPE
612 };
613
614 static struct clk dpll4_ck = {
615 .name = "dpll4_ck",
616 .ops = &clkops_omap3_noncore_dpll_ops,
617 .parent = &sys_ck,
618 .dpll_data = &dpll4_dd,
619 .round_rate = &omap2_dpll_round_rate,
620 .set_rate = &omap3_dpll4_set_rate,
621 .clkdm_name = "dpll4_clkdm",
622 .recalc = &omap3_dpll_recalc,
623 };
624
625 /*
626 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
627 * DPLL isn't bypassed --
628 * XXX does this serve any downstream clocks?
629 */
630 static struct clk dpll4_x2_ck = {
631 .name = "dpll4_x2_ck",
632 .ops = &clkops_null,
633 .parent = &dpll4_ck,
634 .clkdm_name = "dpll4_clkdm",
635 .recalc = &omap3_clkoutx2_recalc,
636 };
637
638 static const struct clksel dpll4_clksel[] = {
639 { .parent = &dpll4_ck, .rates = dpll4_rates },
640 { .parent = NULL }
641 };
642
643 /* This virtual clock is the source for dpll4_m2x2_ck */
644 static struct clk dpll4_m2_ck = {
645 .name = "dpll4_m2_ck",
646 .ops = &clkops_null,
647 .parent = &dpll4_ck,
648 .init = &omap2_init_clksel_parent,
649 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
650 .clksel_mask = OMAP3630_DIV_96M_MASK,
651 .clksel = dpll4_clksel,
652 .clkdm_name = "dpll4_clkdm",
653 .recalc = &omap2_clksel_recalc,
654 };
655
656 /* The PWRDN bit is apparently only available on 3430ES2 and above */
657 static struct clk dpll4_m2x2_ck = {
658 .name = "dpll4_m2x2_ck",
659 .ops = &clkops_omap2_dflt_wait,
660 .parent = &dpll4_m2_ck,
661 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
662 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
663 .flags = INVERT_ENABLE,
664 .clkdm_name = "dpll4_clkdm",
665 .recalc = &omap3_clkoutx2_recalc,
666 };
667
668 /*
669 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
670 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
671 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
672 * CM_96K_(F)CLK.
673 */
674
675 /* Adding 192MHz Clock node needed by SGX */
676 static struct clk omap_192m_alwon_fck = {
677 .name = "omap_192m_alwon_fck",
678 .ops = &clkops_null,
679 .parent = &dpll4_m2x2_ck,
680 .recalc = &followparent_recalc,
681 };
682
683 static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
684 { .div = 1, .val = 1, .flags = RATE_IN_36XX },
685 { .div = 2, .val = 2, .flags = RATE_IN_36XX },
686 { .div = 0 }
687 };
688
689 static const struct clksel omap_96m_alwon_fck_clksel[] = {
690 { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
691 { .parent = NULL }
692 };
693
694 static const struct clksel_rate omap_96m_dpll_rates[] = {
695 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
696 { .div = 0 }
697 };
698
699 static const struct clksel_rate omap_96m_sys_rates[] = {
700 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
701 { .div = 0 }
702 };
703
704 static struct clk omap_96m_alwon_fck = {
705 .name = "omap_96m_alwon_fck",
706 .ops = &clkops_null,
707 .parent = &dpll4_m2x2_ck,
708 .recalc = &followparent_recalc,
709 };
710
711 static struct clk omap_96m_alwon_fck_3630 = {
712 .name = "omap_96m_alwon_fck",
713 .parent = &omap_192m_alwon_fck,
714 .init = &omap2_init_clksel_parent,
715 .ops = &clkops_null,
716 .recalc = &omap2_clksel_recalc,
717 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
718 .clksel_mask = OMAP3630_CLKSEL_96M_MASK,
719 .clksel = omap_96m_alwon_fck_clksel
720 };
721
722 static struct clk cm_96m_fck = {
723 .name = "cm_96m_fck",
724 .ops = &clkops_null,
725 .parent = &omap_96m_alwon_fck,
726 .recalc = &followparent_recalc,
727 };
728
729 static const struct clksel omap_96m_fck_clksel[] = {
730 { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
731 { .parent = &sys_ck, .rates = omap_96m_sys_rates },
732 { .parent = NULL }
733 };
734
735 static struct clk omap_96m_fck = {
736 .name = "omap_96m_fck",
737 .ops = &clkops_null,
738 .parent = &sys_ck,
739 .init = &omap2_init_clksel_parent,
740 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
741 .clksel_mask = OMAP3430_SOURCE_96M_MASK,
742 .clksel = omap_96m_fck_clksel,
743 .recalc = &omap2_clksel_recalc,
744 };
745
746 /* This virtual clock is the source for dpll4_m3x2_ck */
747 static struct clk dpll4_m3_ck = {
748 .name = "dpll4_m3_ck",
749 .ops = &clkops_null,
750 .parent = &dpll4_ck,
751 .init = &omap2_init_clksel_parent,
752 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
753 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
754 .clksel = dpll4_clksel,
755 .clkdm_name = "dpll4_clkdm",
756 .recalc = &omap2_clksel_recalc,
757 };
758
759 /* The PWRDN bit is apparently only available on 3430ES2 and above */
760 static struct clk dpll4_m3x2_ck = {
761 .name = "dpll4_m3x2_ck",
762 .ops = &clkops_omap2_dflt_wait,
763 .parent = &dpll4_m3_ck,
764 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
765 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
766 .flags = INVERT_ENABLE,
767 .clkdm_name = "dpll4_clkdm",
768 .recalc = &omap3_clkoutx2_recalc,
769 };
770
771 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
772 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
773 { .div = 0 }
774 };
775
776 static const struct clksel_rate omap_54m_alt_rates[] = {
777 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
778 { .div = 0 }
779 };
780
781 static const struct clksel omap_54m_clksel[] = {
782 { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
783 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
784 { .parent = NULL }
785 };
786
787 static struct clk omap_54m_fck = {
788 .name = "omap_54m_fck",
789 .ops = &clkops_null,
790 .init = &omap2_init_clksel_parent,
791 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
792 .clksel_mask = OMAP3430_SOURCE_54M_MASK,
793 .clksel = omap_54m_clksel,
794 .recalc = &omap2_clksel_recalc,
795 };
796
797 static const struct clksel_rate omap_48m_cm96m_rates[] = {
798 { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
799 { .div = 0 }
800 };
801
802 static const struct clksel_rate omap_48m_alt_rates[] = {
803 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
804 { .div = 0 }
805 };
806
807 static const struct clksel omap_48m_clksel[] = {
808 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
809 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
810 { .parent = NULL }
811 };
812
813 static struct clk omap_48m_fck = {
814 .name = "omap_48m_fck",
815 .ops = &clkops_null,
816 .init = &omap2_init_clksel_parent,
817 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
818 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
819 .clksel = omap_48m_clksel,
820 .recalc = &omap2_clksel_recalc,
821 };
822
823 static struct clk omap_12m_fck = {
824 .name = "omap_12m_fck",
825 .ops = &clkops_null,
826 .parent = &omap_48m_fck,
827 .fixed_div = 4,
828 .recalc = &omap_fixed_divisor_recalc,
829 };
830
831 /* This virtual clock is the source for dpll4_m4x2_ck */
832 static struct clk dpll4_m4_ck = {
833 .name = "dpll4_m4_ck",
834 .ops = &clkops_null,
835 .parent = &dpll4_ck,
836 .init = &omap2_init_clksel_parent,
837 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
838 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
839 .clksel = dpll4_clksel,
840 .clkdm_name = "dpll4_clkdm",
841 .recalc = &omap2_clksel_recalc,
842 .set_rate = &omap2_clksel_set_rate,
843 .round_rate = &omap2_clksel_round_rate,
844 };
845
846 /* The PWRDN bit is apparently only available on 3430ES2 and above */
847 static struct clk dpll4_m4x2_ck = {
848 .name = "dpll4_m4x2_ck",
849 .ops = &clkops_omap2_dflt_wait,
850 .parent = &dpll4_m4_ck,
851 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
852 .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
853 .flags = INVERT_ENABLE,
854 .clkdm_name = "dpll4_clkdm",
855 .recalc = &omap3_clkoutx2_recalc,
856 };
857
858 /* This virtual clock is the source for dpll4_m5x2_ck */
859 static struct clk dpll4_m5_ck = {
860 .name = "dpll4_m5_ck",
861 .ops = &clkops_null,
862 .parent = &dpll4_ck,
863 .init = &omap2_init_clksel_parent,
864 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
865 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
866 .clksel = dpll4_clksel,
867 .clkdm_name = "dpll4_clkdm",
868 .set_rate = &omap2_clksel_set_rate,
869 .round_rate = &omap2_clksel_round_rate,
870 .recalc = &omap2_clksel_recalc,
871 };
872
873 /* The PWRDN bit is apparently only available on 3430ES2 and above */
874 static struct clk dpll4_m5x2_ck = {
875 .name = "dpll4_m5x2_ck",
876 .ops = &clkops_omap2_dflt_wait,
877 .parent = &dpll4_m5_ck,
878 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
879 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
880 .flags = INVERT_ENABLE,
881 .clkdm_name = "dpll4_clkdm",
882 .recalc = &omap3_clkoutx2_recalc,
883 };
884
885 /* This virtual clock is the source for dpll4_m6x2_ck */
886 static struct clk dpll4_m6_ck = {
887 .name = "dpll4_m6_ck",
888 .ops = &clkops_null,
889 .parent = &dpll4_ck,
890 .init = &omap2_init_clksel_parent,
891 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
892 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
893 .clksel = dpll4_clksel,
894 .clkdm_name = "dpll4_clkdm",
895 .recalc = &omap2_clksel_recalc,
896 };
897
898 /* The PWRDN bit is apparently only available on 3430ES2 and above */
899 static struct clk dpll4_m6x2_ck = {
900 .name = "dpll4_m6x2_ck",
901 .ops = &clkops_omap2_dflt_wait,
902 .parent = &dpll4_m6_ck,
903 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
904 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
905 .flags = INVERT_ENABLE,
906 .clkdm_name = "dpll4_clkdm",
907 .recalc = &omap3_clkoutx2_recalc,
908 };
909
910 static struct clk emu_per_alwon_ck = {
911 .name = "emu_per_alwon_ck",
912 .ops = &clkops_null,
913 .parent = &dpll4_m6x2_ck,
914 .clkdm_name = "dpll4_clkdm",
915 .recalc = &followparent_recalc,
916 };
917
918 /* DPLL5 */
919 /* Supplies 120MHz clock, USIM source clock */
920 /* Type: DPLL */
921 /* 3430ES2 only */
922 static struct dpll_data dpll5_dd = {
923 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
924 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
925 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
926 .clk_bypass = &sys_ck,
927 .clk_ref = &sys_ck,
928 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
929 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
930 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
931 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
932 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
933 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
934 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
935 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
936 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
937 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
938 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
939 .max_multiplier = OMAP3_MAX_DPLL_MULT,
940 .min_divider = 1,
941 .max_divider = OMAP3_MAX_DPLL_DIV,
942 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
943 };
944
945 static struct clk dpll5_ck = {
946 .name = "dpll5_ck",
947 .ops = &clkops_omap3_noncore_dpll_ops,
948 .parent = &sys_ck,
949 .dpll_data = &dpll5_dd,
950 .round_rate = &omap2_dpll_round_rate,
951 .set_rate = &omap3_noncore_dpll_set_rate,
952 .clkdm_name = "dpll5_clkdm",
953 .recalc = &omap3_dpll_recalc,
954 };
955
956 static const struct clksel div16_dpll5_clksel[] = {
957 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
958 { .parent = NULL }
959 };
960
961 static struct clk dpll5_m2_ck = {
962 .name = "dpll5_m2_ck",
963 .ops = &clkops_null,
964 .parent = &dpll5_ck,
965 .init = &omap2_init_clksel_parent,
966 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
967 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
968 .clksel = div16_dpll5_clksel,
969 .clkdm_name = "dpll5_clkdm",
970 .recalc = &omap2_clksel_recalc,
971 };
972
973 /* CM EXTERNAL CLOCK OUTPUTS */
974
975 static const struct clksel_rate clkout2_src_core_rates[] = {
976 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
977 { .div = 0 }
978 };
979
980 static const struct clksel_rate clkout2_src_sys_rates[] = {
981 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
982 { .div = 0 }
983 };
984
985 static const struct clksel_rate clkout2_src_96m_rates[] = {
986 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
987 { .div = 0 }
988 };
989
990 static const struct clksel_rate clkout2_src_54m_rates[] = {
991 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
992 { .div = 0 }
993 };
994
995 static const struct clksel clkout2_src_clksel[] = {
996 { .parent = &core_ck, .rates = clkout2_src_core_rates },
997 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
998 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
999 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
1000 { .parent = NULL }
1001 };
1002
1003 static struct clk clkout2_src_ck = {
1004 .name = "clkout2_src_ck",
1005 .ops = &clkops_omap2_dflt,
1006 .init = &omap2_init_clksel_parent,
1007 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
1008 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
1009 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
1010 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
1011 .clksel = clkout2_src_clksel,
1012 .clkdm_name = "core_clkdm",
1013 .recalc = &omap2_clksel_recalc,
1014 };
1015
1016 static const struct clksel_rate sys_clkout2_rates[] = {
1017 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1018 { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1019 { .div = 4, .val = 2, .flags = RATE_IN_3XXX },
1020 { .div = 8, .val = 3, .flags = RATE_IN_3XXX },
1021 { .div = 16, .val = 4, .flags = RATE_IN_3XXX },
1022 { .div = 0 },
1023 };
1024
1025 static const struct clksel sys_clkout2_clksel[] = {
1026 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1027 { .parent = NULL },
1028 };
1029
1030 static struct clk sys_clkout2 = {
1031 .name = "sys_clkout2",
1032 .ops = &clkops_null,
1033 .init = &omap2_init_clksel_parent,
1034 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
1035 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
1036 .clksel = sys_clkout2_clksel,
1037 .recalc = &omap2_clksel_recalc,
1038 .round_rate = &omap2_clksel_round_rate,
1039 .set_rate = &omap2_clksel_set_rate
1040 };
1041
1042 /* CM OUTPUT CLOCKS */
1043
1044 static struct clk corex2_fck = {
1045 .name = "corex2_fck",
1046 .ops = &clkops_null,
1047 .parent = &dpll3_m2x2_ck,
1048 .recalc = &followparent_recalc,
1049 };
1050
1051 /* DPLL power domain clock controls */
1052
1053 static const struct clksel_rate div4_rates[] = {
1054 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1055 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1056 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1057 { .div = 0 }
1058 };
1059
1060 static const struct clksel div4_core_clksel[] = {
1061 { .parent = &core_ck, .rates = div4_rates },
1062 { .parent = NULL }
1063 };
1064
1065 /*
1066 * REVISIT: Are these in DPLL power domain or CM power domain? docs
1067 * may be inconsistent here?
1068 */
1069 static struct clk dpll1_fck = {
1070 .name = "dpll1_fck",
1071 .ops = &clkops_null,
1072 .parent = &core_ck,
1073 .init = &omap2_init_clksel_parent,
1074 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1075 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
1076 .clksel = div4_core_clksel,
1077 .recalc = &omap2_clksel_recalc,
1078 };
1079
1080 static struct clk mpu_ck = {
1081 .name = "mpu_ck",
1082 .ops = &clkops_null,
1083 .parent = &dpll1_x2m2_ck,
1084 .clkdm_name = "mpu_clkdm",
1085 .recalc = &followparent_recalc,
1086 };
1087
1088 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1089 static const struct clksel_rate arm_fck_rates[] = {
1090 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1091 { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1092 { .div = 0 },
1093 };
1094
1095 static const struct clksel arm_fck_clksel[] = {
1096 { .parent = &mpu_ck, .rates = arm_fck_rates },
1097 { .parent = NULL }
1098 };
1099
1100 static struct clk arm_fck = {
1101 .name = "arm_fck",
1102 .ops = &clkops_null,
1103 .parent = &mpu_ck,
1104 .init = &omap2_init_clksel_parent,
1105 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1106 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1107 .clksel = arm_fck_clksel,
1108 .clkdm_name = "mpu_clkdm",
1109 .recalc = &omap2_clksel_recalc,
1110 };
1111
1112 /* XXX What about neon_clkdm ? */
1113
1114 /*
1115 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1116 * although it is referenced - so this is a guess
1117 */
1118 static struct clk emu_mpu_alwon_ck = {
1119 .name = "emu_mpu_alwon_ck",
1120 .ops = &clkops_null,
1121 .parent = &mpu_ck,
1122 .recalc = &followparent_recalc,
1123 };
1124
1125 static struct clk dpll2_fck = {
1126 .name = "dpll2_fck",
1127 .ops = &clkops_null,
1128 .parent = &core_ck,
1129 .init = &omap2_init_clksel_parent,
1130 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1131 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1132 .clksel = div4_core_clksel,
1133 .recalc = &omap2_clksel_recalc,
1134 };
1135
1136 static struct clk iva2_ck = {
1137 .name = "iva2_ck",
1138 .ops = &clkops_omap2_dflt_wait,
1139 .parent = &dpll2_m2_ck,
1140 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1141 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1142 .clkdm_name = "iva2_clkdm",
1143 .recalc = &followparent_recalc,
1144 };
1145
1146 /* Common interface clocks */
1147
1148 static const struct clksel div2_core_clksel[] = {
1149 { .parent = &core_ck, .rates = div2_rates },
1150 { .parent = NULL }
1151 };
1152
1153 static struct clk l3_ick = {
1154 .name = "l3_ick",
1155 .ops = &clkops_null,
1156 .parent = &core_ck,
1157 .init = &omap2_init_clksel_parent,
1158 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1159 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1160 .clksel = div2_core_clksel,
1161 .clkdm_name = "core_l3_clkdm",
1162 .recalc = &omap2_clksel_recalc,
1163 };
1164
1165 static const struct clksel div2_l3_clksel[] = {
1166 { .parent = &l3_ick, .rates = div2_rates },
1167 { .parent = NULL }
1168 };
1169
1170 static struct clk l4_ick = {
1171 .name = "l4_ick",
1172 .ops = &clkops_null,
1173 .parent = &l3_ick,
1174 .init = &omap2_init_clksel_parent,
1175 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1176 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1177 .clksel = div2_l3_clksel,
1178 .clkdm_name = "core_l4_clkdm",
1179 .recalc = &omap2_clksel_recalc,
1180
1181 };
1182
1183 static const struct clksel div2_l4_clksel[] = {
1184 { .parent = &l4_ick, .rates = div2_rates },
1185 { .parent = NULL }
1186 };
1187
1188 static struct clk rm_ick = {
1189 .name = "rm_ick",
1190 .ops = &clkops_null,
1191 .parent = &l4_ick,
1192 .init = &omap2_init_clksel_parent,
1193 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1194 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1195 .clksel = div2_l4_clksel,
1196 .recalc = &omap2_clksel_recalc,
1197 };
1198
1199 /* GFX power domain */
1200
1201 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1202
1203 static const struct clksel gfx_l3_clksel[] = {
1204 { .parent = &l3_ick, .rates = gfx_l3_rates },
1205 { .parent = NULL }
1206 };
1207
1208 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1209 static struct clk gfx_l3_ck = {
1210 .name = "gfx_l3_ck",
1211 .ops = &clkops_omap2_dflt_wait,
1212 .parent = &l3_ick,
1213 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1214 .enable_bit = OMAP_EN_GFX_SHIFT,
1215 .recalc = &followparent_recalc,
1216 };
1217
1218 static struct clk gfx_l3_fck = {
1219 .name = "gfx_l3_fck",
1220 .ops = &clkops_null,
1221 .parent = &gfx_l3_ck,
1222 .init = &omap2_init_clksel_parent,
1223 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1224 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1225 .clksel = gfx_l3_clksel,
1226 .clkdm_name = "gfx_3430es1_clkdm",
1227 .recalc = &omap2_clksel_recalc,
1228 };
1229
1230 static struct clk gfx_l3_ick = {
1231 .name = "gfx_l3_ick",
1232 .ops = &clkops_null,
1233 .parent = &gfx_l3_ck,
1234 .clkdm_name = "gfx_3430es1_clkdm",
1235 .recalc = &followparent_recalc,
1236 };
1237
1238 static struct clk gfx_cg1_ck = {
1239 .name = "gfx_cg1_ck",
1240 .ops = &clkops_omap2_dflt_wait,
1241 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1242 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1243 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1244 .clkdm_name = "gfx_3430es1_clkdm",
1245 .recalc = &followparent_recalc,
1246 };
1247
1248 static struct clk gfx_cg2_ck = {
1249 .name = "gfx_cg2_ck",
1250 .ops = &clkops_omap2_dflt_wait,
1251 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1252 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1253 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1254 .clkdm_name = "gfx_3430es1_clkdm",
1255 .recalc = &followparent_recalc,
1256 };
1257
1258 /* SGX power domain - 3430ES2 only */
1259
1260 static const struct clksel_rate sgx_core_rates[] = {
1261 { .div = 2, .val = 5, .flags = RATE_IN_36XX },
1262 { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
1263 { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
1264 { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
1265 { .div = 0 },
1266 };
1267
1268 static const struct clksel_rate sgx_192m_rates[] = {
1269 { .div = 1, .val = 4, .flags = RATE_IN_36XX },
1270 { .div = 0 },
1271 };
1272
1273 static const struct clksel_rate sgx_corex2_rates[] = {
1274 { .div = 3, .val = 6, .flags = RATE_IN_36XX },
1275 { .div = 5, .val = 7, .flags = RATE_IN_36XX },
1276 { .div = 0 },
1277 };
1278
1279 static const struct clksel_rate sgx_96m_rates[] = {
1280 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
1281 { .div = 0 },
1282 };
1283
1284 static const struct clksel sgx_clksel[] = {
1285 { .parent = &core_ck, .rates = sgx_core_rates },
1286 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1287 { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
1288 { .parent = &corex2_fck, .rates = sgx_corex2_rates },
1289 { .parent = NULL }
1290 };
1291
1292 static struct clk sgx_fck = {
1293 .name = "sgx_fck",
1294 .ops = &clkops_omap2_dflt_wait,
1295 .init = &omap2_init_clksel_parent,
1296 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1297 .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1298 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1299 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1300 .clksel = sgx_clksel,
1301 .clkdm_name = "sgx_clkdm",
1302 .recalc = &omap2_clksel_recalc,
1303 .set_rate = &omap2_clksel_set_rate,
1304 .round_rate = &omap2_clksel_round_rate
1305 };
1306
1307 static struct clk sgx_ick = {
1308 .name = "sgx_ick",
1309 .ops = &clkops_omap2_dflt_wait,
1310 .parent = &l3_ick,
1311 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1312 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1313 .clkdm_name = "sgx_clkdm",
1314 .recalc = &followparent_recalc,
1315 };
1316
1317 /* CORE power domain */
1318
1319 static struct clk d2d_26m_fck = {
1320 .name = "d2d_26m_fck",
1321 .ops = &clkops_omap2_dflt_wait,
1322 .parent = &sys_ck,
1323 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1324 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1325 .clkdm_name = "d2d_clkdm",
1326 .recalc = &followparent_recalc,
1327 };
1328
1329 static struct clk modem_fck = {
1330 .name = "modem_fck",
1331 .ops = &clkops_omap2_dflt_wait,
1332 .parent = &sys_ck,
1333 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1334 .enable_bit = OMAP3430_EN_MODEM_SHIFT,
1335 .clkdm_name = "d2d_clkdm",
1336 .recalc = &followparent_recalc,
1337 };
1338
1339 static struct clk sad2d_ick = {
1340 .name = "sad2d_ick",
1341 .ops = &clkops_omap2_dflt_wait,
1342 .parent = &l3_ick,
1343 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1344 .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
1345 .clkdm_name = "d2d_clkdm",
1346 .recalc = &followparent_recalc,
1347 };
1348
1349 static struct clk mad2d_ick = {
1350 .name = "mad2d_ick",
1351 .ops = &clkops_omap2_dflt_wait,
1352 .parent = &l3_ick,
1353 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1354 .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
1355 .clkdm_name = "d2d_clkdm",
1356 .recalc = &followparent_recalc,
1357 };
1358
1359 static const struct clksel omap343x_gpt_clksel[] = {
1360 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1361 { .parent = &sys_ck, .rates = gpt_sys_rates },
1362 { .parent = NULL}
1363 };
1364
1365 static struct clk gpt10_fck = {
1366 .name = "gpt10_fck",
1367 .ops = &clkops_omap2_dflt_wait,
1368 .parent = &sys_ck,
1369 .init = &omap2_init_clksel_parent,
1370 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1371 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1372 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1373 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1374 .clksel = omap343x_gpt_clksel,
1375 .clkdm_name = "core_l4_clkdm",
1376 .recalc = &omap2_clksel_recalc,
1377 };
1378
1379 static struct clk gpt11_fck = {
1380 .name = "gpt11_fck",
1381 .ops = &clkops_omap2_dflt_wait,
1382 .parent = &sys_ck,
1383 .init = &omap2_init_clksel_parent,
1384 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1385 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1386 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1387 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1388 .clksel = omap343x_gpt_clksel,
1389 .clkdm_name = "core_l4_clkdm",
1390 .recalc = &omap2_clksel_recalc,
1391 };
1392
1393 static struct clk cpefuse_fck = {
1394 .name = "cpefuse_fck",
1395 .ops = &clkops_omap2_dflt,
1396 .parent = &sys_ck,
1397 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1398 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1399 .recalc = &followparent_recalc,
1400 };
1401
1402 static struct clk ts_fck = {
1403 .name = "ts_fck",
1404 .ops = &clkops_omap2_dflt,
1405 .parent = &omap_32k_fck,
1406 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1407 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1408 .recalc = &followparent_recalc,
1409 };
1410
1411 static struct clk usbtll_fck = {
1412 .name = "usbtll_fck",
1413 .ops = &clkops_omap2_dflt_wait,
1414 .parent = &dpll5_m2_ck,
1415 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1416 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1417 .recalc = &followparent_recalc,
1418 };
1419
1420 /* CORE 96M FCLK-derived clocks */
1421
1422 static struct clk core_96m_fck = {
1423 .name = "core_96m_fck",
1424 .ops = &clkops_null,
1425 .parent = &omap_96m_fck,
1426 .clkdm_name = "core_l4_clkdm",
1427 .recalc = &followparent_recalc,
1428 };
1429
1430 static struct clk mmchs3_fck = {
1431 .name = "mmchs3_fck",
1432 .ops = &clkops_omap2_dflt_wait,
1433 .parent = &core_96m_fck,
1434 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1435 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1436 .clkdm_name = "core_l4_clkdm",
1437 .recalc = &followparent_recalc,
1438 };
1439
1440 static struct clk mmchs2_fck = {
1441 .name = "mmchs2_fck",
1442 .ops = &clkops_omap2_dflt_wait,
1443 .parent = &core_96m_fck,
1444 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1445 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1446 .clkdm_name = "core_l4_clkdm",
1447 .recalc = &followparent_recalc,
1448 };
1449
1450 static struct clk mspro_fck = {
1451 .name = "mspro_fck",
1452 .ops = &clkops_omap2_dflt_wait,
1453 .parent = &core_96m_fck,
1454 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1455 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1456 .clkdm_name = "core_l4_clkdm",
1457 .recalc = &followparent_recalc,
1458 };
1459
1460 static struct clk mmchs1_fck = {
1461 .name = "mmchs1_fck",
1462 .ops = &clkops_omap2_dflt_wait,
1463 .parent = &core_96m_fck,
1464 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1465 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1466 .clkdm_name = "core_l4_clkdm",
1467 .recalc = &followparent_recalc,
1468 };
1469
1470 static struct clk i2c3_fck = {
1471 .name = "i2c3_fck",
1472 .ops = &clkops_omap2_dflt_wait,
1473 .parent = &core_96m_fck,
1474 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1475 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1476 .clkdm_name = "core_l4_clkdm",
1477 .recalc = &followparent_recalc,
1478 };
1479
1480 static struct clk i2c2_fck = {
1481 .name = "i2c2_fck",
1482 .ops = &clkops_omap2_dflt_wait,
1483 .parent = &core_96m_fck,
1484 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1485 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1486 .clkdm_name = "core_l4_clkdm",
1487 .recalc = &followparent_recalc,
1488 };
1489
1490 static struct clk i2c1_fck = {
1491 .name = "i2c1_fck",
1492 .ops = &clkops_omap2_dflt_wait,
1493 .parent = &core_96m_fck,
1494 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1495 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1496 .clkdm_name = "core_l4_clkdm",
1497 .recalc = &followparent_recalc,
1498 };
1499
1500 /*
1501 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1502 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1503 */
1504 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1505 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1506 { .div = 0 }
1507 };
1508
1509 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1510 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1511 { .div = 0 }
1512 };
1513
1514 static const struct clksel mcbsp_15_clksel[] = {
1515 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1516 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1517 { .parent = NULL }
1518 };
1519
1520 static struct clk mcbsp5_fck = {
1521 .name = "mcbsp5_fck",
1522 .ops = &clkops_omap2_dflt_wait,
1523 .init = &omap2_init_clksel_parent,
1524 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1525 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1526 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1527 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1528 .clksel = mcbsp_15_clksel,
1529 .clkdm_name = "core_l4_clkdm",
1530 .recalc = &omap2_clksel_recalc,
1531 };
1532
1533 static struct clk mcbsp1_fck = {
1534 .name = "mcbsp1_fck",
1535 .ops = &clkops_omap2_dflt_wait,
1536 .init = &omap2_init_clksel_parent,
1537 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1538 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1539 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1540 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1541 .clksel = mcbsp_15_clksel,
1542 .clkdm_name = "core_l4_clkdm",
1543 .recalc = &omap2_clksel_recalc,
1544 };
1545
1546 /* CORE_48M_FCK-derived clocks */
1547
1548 static struct clk core_48m_fck = {
1549 .name = "core_48m_fck",
1550 .ops = &clkops_null,
1551 .parent = &omap_48m_fck,
1552 .clkdm_name = "core_l4_clkdm",
1553 .recalc = &followparent_recalc,
1554 };
1555
1556 static struct clk mcspi4_fck = {
1557 .name = "mcspi4_fck",
1558 .ops = &clkops_omap2_dflt_wait,
1559 .parent = &core_48m_fck,
1560 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1561 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1562 .recalc = &followparent_recalc,
1563 .clkdm_name = "core_l4_clkdm",
1564 };
1565
1566 static struct clk mcspi3_fck = {
1567 .name = "mcspi3_fck",
1568 .ops = &clkops_omap2_dflt_wait,
1569 .parent = &core_48m_fck,
1570 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1571 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1572 .recalc = &followparent_recalc,
1573 .clkdm_name = "core_l4_clkdm",
1574 };
1575
1576 static struct clk mcspi2_fck = {
1577 .name = "mcspi2_fck",
1578 .ops = &clkops_omap2_dflt_wait,
1579 .parent = &core_48m_fck,
1580 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1581 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1582 .recalc = &followparent_recalc,
1583 .clkdm_name = "core_l4_clkdm",
1584 };
1585
1586 static struct clk mcspi1_fck = {
1587 .name = "mcspi1_fck",
1588 .ops = &clkops_omap2_dflt_wait,
1589 .parent = &core_48m_fck,
1590 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1591 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1592 .recalc = &followparent_recalc,
1593 .clkdm_name = "core_l4_clkdm",
1594 };
1595
1596 static struct clk uart2_fck = {
1597 .name = "uart2_fck",
1598 .ops = &clkops_omap2_dflt_wait,
1599 .parent = &core_48m_fck,
1600 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1601 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1602 .clkdm_name = "core_l4_clkdm",
1603 .recalc = &followparent_recalc,
1604 };
1605
1606 static struct clk uart1_fck = {
1607 .name = "uart1_fck",
1608 .ops = &clkops_omap2_dflt_wait,
1609 .parent = &core_48m_fck,
1610 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1611 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1612 .clkdm_name = "core_l4_clkdm",
1613 .recalc = &followparent_recalc,
1614 };
1615
1616 static struct clk fshostusb_fck = {
1617 .name = "fshostusb_fck",
1618 .ops = &clkops_omap2_dflt_wait,
1619 .parent = &core_48m_fck,
1620 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1621 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1622 .recalc = &followparent_recalc,
1623 };
1624
1625 /* CORE_12M_FCK based clocks */
1626
1627 static struct clk core_12m_fck = {
1628 .name = "core_12m_fck",
1629 .ops = &clkops_null,
1630 .parent = &omap_12m_fck,
1631 .clkdm_name = "core_l4_clkdm",
1632 .recalc = &followparent_recalc,
1633 };
1634
1635 static struct clk hdq_fck = {
1636 .name = "hdq_fck",
1637 .ops = &clkops_omap2_dflt_wait,
1638 .parent = &core_12m_fck,
1639 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1640 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1641 .recalc = &followparent_recalc,
1642 };
1643
1644 /* DPLL3-derived clock */
1645
1646 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1647 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1648 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1649 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
1650 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1651 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
1652 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
1653 { .div = 0 }
1654 };
1655
1656 static const struct clksel ssi_ssr_clksel[] = {
1657 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1658 { .parent = NULL }
1659 };
1660
1661 static struct clk ssi_ssr_fck_3430es1 = {
1662 .name = "ssi_ssr_fck",
1663 .ops = &clkops_omap2_dflt,
1664 .init = &omap2_init_clksel_parent,
1665 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1666 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1667 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1668 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1669 .clksel = ssi_ssr_clksel,
1670 .clkdm_name = "core_l4_clkdm",
1671 .recalc = &omap2_clksel_recalc,
1672 };
1673
1674 static struct clk ssi_ssr_fck_3430es2 = {
1675 .name = "ssi_ssr_fck",
1676 .ops = &clkops_omap3430es2_ssi_wait,
1677 .init = &omap2_init_clksel_parent,
1678 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1679 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1680 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1681 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1682 .clksel = ssi_ssr_clksel,
1683 .clkdm_name = "core_l4_clkdm",
1684 .recalc = &omap2_clksel_recalc,
1685 };
1686
1687 static struct clk ssi_sst_fck_3430es1 = {
1688 .name = "ssi_sst_fck",
1689 .ops = &clkops_null,
1690 .parent = &ssi_ssr_fck_3430es1,
1691 .fixed_div = 2,
1692 .recalc = &omap_fixed_divisor_recalc,
1693 };
1694
1695 static struct clk ssi_sst_fck_3430es2 = {
1696 .name = "ssi_sst_fck",
1697 .ops = &clkops_null,
1698 .parent = &ssi_ssr_fck_3430es2,
1699 .fixed_div = 2,
1700 .recalc = &omap_fixed_divisor_recalc,
1701 };
1702
1703
1704
1705 /* CORE_L3_ICK based clocks */
1706
1707 /*
1708 * XXX must add clk_enable/clk_disable for these if standard code won't
1709 * handle it
1710 */
1711 static struct clk core_l3_ick = {
1712 .name = "core_l3_ick",
1713 .ops = &clkops_null,
1714 .parent = &l3_ick,
1715 .clkdm_name = "core_l3_clkdm",
1716 .recalc = &followparent_recalc,
1717 };
1718
1719 static struct clk hsotgusb_ick_3430es1 = {
1720 .name = "hsotgusb_ick",
1721 .ops = &clkops_omap2_dflt,
1722 .parent = &core_l3_ick,
1723 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1724 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1725 .clkdm_name = "core_l3_clkdm",
1726 .recalc = &followparent_recalc,
1727 };
1728
1729 static struct clk hsotgusb_ick_3430es2 = {
1730 .name = "hsotgusb_ick",
1731 .ops = &clkops_omap3430es2_hsotgusb_wait,
1732 .parent = &core_l3_ick,
1733 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1734 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1735 .clkdm_name = "core_l3_clkdm",
1736 .recalc = &followparent_recalc,
1737 };
1738
1739 static struct clk sdrc_ick = {
1740 .name = "sdrc_ick",
1741 .ops = &clkops_omap2_dflt_wait,
1742 .parent = &core_l3_ick,
1743 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1744 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1745 .flags = ENABLE_ON_INIT,
1746 .clkdm_name = "core_l3_clkdm",
1747 .recalc = &followparent_recalc,
1748 };
1749
1750 static struct clk gpmc_fck = {
1751 .name = "gpmc_fck",
1752 .ops = &clkops_null,
1753 .parent = &core_l3_ick,
1754 .flags = ENABLE_ON_INIT, /* huh? */
1755 .clkdm_name = "core_l3_clkdm",
1756 .recalc = &followparent_recalc,
1757 };
1758
1759 /* SECURITY_L3_ICK based clocks */
1760
1761 static struct clk security_l3_ick = {
1762 .name = "security_l3_ick",
1763 .ops = &clkops_null,
1764 .parent = &l3_ick,
1765 .recalc = &followparent_recalc,
1766 };
1767
1768 static struct clk pka_ick = {
1769 .name = "pka_ick",
1770 .ops = &clkops_omap2_dflt_wait,
1771 .parent = &security_l3_ick,
1772 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1773 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1774 .recalc = &followparent_recalc,
1775 };
1776
1777 /* CORE_L4_ICK based clocks */
1778
1779 static struct clk core_l4_ick = {
1780 .name = "core_l4_ick",
1781 .ops = &clkops_null,
1782 .parent = &l4_ick,
1783 .clkdm_name = "core_l4_clkdm",
1784 .recalc = &followparent_recalc,
1785 };
1786
1787 static struct clk usbtll_ick = {
1788 .name = "usbtll_ick",
1789 .ops = &clkops_omap2_dflt_wait,
1790 .parent = &core_l4_ick,
1791 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1792 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1793 .clkdm_name = "core_l4_clkdm",
1794 .recalc = &followparent_recalc,
1795 };
1796
1797 static struct clk mmchs3_ick = {
1798 .name = "mmchs3_ick",
1799 .ops = &clkops_omap2_dflt_wait,
1800 .parent = &core_l4_ick,
1801 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1802 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1803 .clkdm_name = "core_l4_clkdm",
1804 .recalc = &followparent_recalc,
1805 };
1806
1807 /* Intersystem Communication Registers - chassis mode only */
1808 static struct clk icr_ick = {
1809 .name = "icr_ick",
1810 .ops = &clkops_omap2_dflt_wait,
1811 .parent = &core_l4_ick,
1812 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1813 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1814 .clkdm_name = "core_l4_clkdm",
1815 .recalc = &followparent_recalc,
1816 };
1817
1818 static struct clk aes2_ick = {
1819 .name = "aes2_ick",
1820 .ops = &clkops_omap2_dflt_wait,
1821 .parent = &core_l4_ick,
1822 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1823 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1824 .clkdm_name = "core_l4_clkdm",
1825 .recalc = &followparent_recalc,
1826 };
1827
1828 static struct clk sha12_ick = {
1829 .name = "sha12_ick",
1830 .ops = &clkops_omap2_dflt_wait,
1831 .parent = &core_l4_ick,
1832 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1833 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1834 .clkdm_name = "core_l4_clkdm",
1835 .recalc = &followparent_recalc,
1836 };
1837
1838 static struct clk des2_ick = {
1839 .name = "des2_ick",
1840 .ops = &clkops_omap2_dflt_wait,
1841 .parent = &core_l4_ick,
1842 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1843 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1844 .clkdm_name = "core_l4_clkdm",
1845 .recalc = &followparent_recalc,
1846 };
1847
1848 static struct clk mmchs2_ick = {
1849 .name = "mmchs2_ick",
1850 .ops = &clkops_omap2_dflt_wait,
1851 .parent = &core_l4_ick,
1852 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1853 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1854 .clkdm_name = "core_l4_clkdm",
1855 .recalc = &followparent_recalc,
1856 };
1857
1858 static struct clk mmchs1_ick = {
1859 .name = "mmchs1_ick",
1860 .ops = &clkops_omap2_dflt_wait,
1861 .parent = &core_l4_ick,
1862 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1863 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1864 .clkdm_name = "core_l4_clkdm",
1865 .recalc = &followparent_recalc,
1866 };
1867
1868 static struct clk mspro_ick = {
1869 .name = "mspro_ick",
1870 .ops = &clkops_omap2_dflt_wait,
1871 .parent = &core_l4_ick,
1872 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1873 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1874 .clkdm_name = "core_l4_clkdm",
1875 .recalc = &followparent_recalc,
1876 };
1877
1878 static struct clk hdq_ick = {
1879 .name = "hdq_ick",
1880 .ops = &clkops_omap2_dflt_wait,
1881 .parent = &core_l4_ick,
1882 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1883 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1884 .clkdm_name = "core_l4_clkdm",
1885 .recalc = &followparent_recalc,
1886 };
1887
1888 static struct clk mcspi4_ick = {
1889 .name = "mcspi4_ick",
1890 .ops = &clkops_omap2_dflt_wait,
1891 .parent = &core_l4_ick,
1892 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1893 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1894 .clkdm_name = "core_l4_clkdm",
1895 .recalc = &followparent_recalc,
1896 };
1897
1898 static struct clk mcspi3_ick = {
1899 .name = "mcspi3_ick",
1900 .ops = &clkops_omap2_dflt_wait,
1901 .parent = &core_l4_ick,
1902 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1903 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1904 .clkdm_name = "core_l4_clkdm",
1905 .recalc = &followparent_recalc,
1906 };
1907
1908 static struct clk mcspi2_ick = {
1909 .name = "mcspi2_ick",
1910 .ops = &clkops_omap2_dflt_wait,
1911 .parent = &core_l4_ick,
1912 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1913 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1914 .clkdm_name = "core_l4_clkdm",
1915 .recalc = &followparent_recalc,
1916 };
1917
1918 static struct clk mcspi1_ick = {
1919 .name = "mcspi1_ick",
1920 .ops = &clkops_omap2_dflt_wait,
1921 .parent = &core_l4_ick,
1922 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1923 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1924 .clkdm_name = "core_l4_clkdm",
1925 .recalc = &followparent_recalc,
1926 };
1927
1928 static struct clk i2c3_ick = {
1929 .name = "i2c3_ick",
1930 .ops = &clkops_omap2_dflt_wait,
1931 .parent = &core_l4_ick,
1932 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1933 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1934 .clkdm_name = "core_l4_clkdm",
1935 .recalc = &followparent_recalc,
1936 };
1937
1938 static struct clk i2c2_ick = {
1939 .name = "i2c2_ick",
1940 .ops = &clkops_omap2_dflt_wait,
1941 .parent = &core_l4_ick,
1942 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1943 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1944 .clkdm_name = "core_l4_clkdm",
1945 .recalc = &followparent_recalc,
1946 };
1947
1948 static struct clk i2c1_ick = {
1949 .name = "i2c1_ick",
1950 .ops = &clkops_omap2_dflt_wait,
1951 .parent = &core_l4_ick,
1952 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1953 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1954 .clkdm_name = "core_l4_clkdm",
1955 .recalc = &followparent_recalc,
1956 };
1957
1958 static struct clk uart2_ick = {
1959 .name = "uart2_ick",
1960 .ops = &clkops_omap2_dflt_wait,
1961 .parent = &core_l4_ick,
1962 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1963 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1964 .clkdm_name = "core_l4_clkdm",
1965 .recalc = &followparent_recalc,
1966 };
1967
1968 static struct clk uart1_ick = {
1969 .name = "uart1_ick",
1970 .ops = &clkops_omap2_dflt_wait,
1971 .parent = &core_l4_ick,
1972 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1973 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1974 .clkdm_name = "core_l4_clkdm",
1975 .recalc = &followparent_recalc,
1976 };
1977
1978 static struct clk gpt11_ick = {
1979 .name = "gpt11_ick",
1980 .ops = &clkops_omap2_dflt_wait,
1981 .parent = &core_l4_ick,
1982 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1983 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1984 .clkdm_name = "core_l4_clkdm",
1985 .recalc = &followparent_recalc,
1986 };
1987
1988 static struct clk gpt10_ick = {
1989 .name = "gpt10_ick",
1990 .ops = &clkops_omap2_dflt_wait,
1991 .parent = &core_l4_ick,
1992 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1993 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1994 .clkdm_name = "core_l4_clkdm",
1995 .recalc = &followparent_recalc,
1996 };
1997
1998 static struct clk mcbsp5_ick = {
1999 .name = "mcbsp5_ick",
2000 .ops = &clkops_omap2_dflt_wait,
2001 .parent = &core_l4_ick,
2002 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2003 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
2004 .clkdm_name = "core_l4_clkdm",
2005 .recalc = &followparent_recalc,
2006 };
2007
2008 static struct clk mcbsp1_ick = {
2009 .name = "mcbsp1_ick",
2010 .ops = &clkops_omap2_dflt_wait,
2011 .parent = &core_l4_ick,
2012 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2013 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
2014 .clkdm_name = "core_l4_clkdm",
2015 .recalc = &followparent_recalc,
2016 };
2017
2018 static struct clk fac_ick = {
2019 .name = "fac_ick",
2020 .ops = &clkops_omap2_dflt_wait,
2021 .parent = &core_l4_ick,
2022 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2023 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
2024 .clkdm_name = "core_l4_clkdm",
2025 .recalc = &followparent_recalc,
2026 };
2027
2028 static struct clk mailboxes_ick = {
2029 .name = "mailboxes_ick",
2030 .ops = &clkops_omap2_dflt_wait,
2031 .parent = &core_l4_ick,
2032 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2033 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2034 .clkdm_name = "core_l4_clkdm",
2035 .recalc = &followparent_recalc,
2036 };
2037
2038 static struct clk omapctrl_ick = {
2039 .name = "omapctrl_ick",
2040 .ops = &clkops_omap2_dflt_wait,
2041 .parent = &core_l4_ick,
2042 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2043 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2044 .flags = ENABLE_ON_INIT,
2045 .recalc = &followparent_recalc,
2046 };
2047
2048 /* SSI_L4_ICK based clocks */
2049
2050 static struct clk ssi_l4_ick = {
2051 .name = "ssi_l4_ick",
2052 .ops = &clkops_null,
2053 .parent = &l4_ick,
2054 .clkdm_name = "core_l4_clkdm",
2055 .recalc = &followparent_recalc,
2056 };
2057
2058 static struct clk ssi_ick_3430es1 = {
2059 .name = "ssi_ick",
2060 .ops = &clkops_omap2_dflt,
2061 .parent = &ssi_l4_ick,
2062 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2063 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2064 .clkdm_name = "core_l4_clkdm",
2065 .recalc = &followparent_recalc,
2066 };
2067
2068 static struct clk ssi_ick_3430es2 = {
2069 .name = "ssi_ick",
2070 .ops = &clkops_omap3430es2_ssi_wait,
2071 .parent = &ssi_l4_ick,
2072 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2073 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2074 .clkdm_name = "core_l4_clkdm",
2075 .recalc = &followparent_recalc,
2076 };
2077
2078 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2079 * but l4_ick makes more sense to me */
2080
2081 static const struct clksel usb_l4_clksel[] = {
2082 { .parent = &l4_ick, .rates = div2_rates },
2083 { .parent = NULL },
2084 };
2085
2086 static struct clk usb_l4_ick = {
2087 .name = "usb_l4_ick",
2088 .ops = &clkops_omap2_dflt_wait,
2089 .parent = &l4_ick,
2090 .init = &omap2_init_clksel_parent,
2091 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2092 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2093 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2094 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2095 .clksel = usb_l4_clksel,
2096 .recalc = &omap2_clksel_recalc,
2097 };
2098
2099 /* SECURITY_L4_ICK2 based clocks */
2100
2101 static struct clk security_l4_ick2 = {
2102 .name = "security_l4_ick2",
2103 .ops = &clkops_null,
2104 .parent = &l4_ick,
2105 .recalc = &followparent_recalc,
2106 };
2107
2108 static struct clk aes1_ick = {
2109 .name = "aes1_ick",
2110 .ops = &clkops_omap2_dflt_wait,
2111 .parent = &security_l4_ick2,
2112 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2113 .enable_bit = OMAP3430_EN_AES1_SHIFT,
2114 .recalc = &followparent_recalc,
2115 };
2116
2117 static struct clk rng_ick = {
2118 .name = "rng_ick",
2119 .ops = &clkops_omap2_dflt_wait,
2120 .parent = &security_l4_ick2,
2121 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2122 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2123 .recalc = &followparent_recalc,
2124 };
2125
2126 static struct clk sha11_ick = {
2127 .name = "sha11_ick",
2128 .ops = &clkops_omap2_dflt_wait,
2129 .parent = &security_l4_ick2,
2130 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2131 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2132 .recalc = &followparent_recalc,
2133 };
2134
2135 static struct clk des1_ick = {
2136 .name = "des1_ick",
2137 .ops = &clkops_omap2_dflt_wait,
2138 .parent = &security_l4_ick2,
2139 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2140 .enable_bit = OMAP3430_EN_DES1_SHIFT,
2141 .recalc = &followparent_recalc,
2142 };
2143
2144 /* DSS */
2145 static struct clk dss1_alwon_fck_3430es1 = {
2146 .name = "dss1_alwon_fck",
2147 .ops = &clkops_omap2_dflt,
2148 .parent = &dpll4_m4x2_ck,
2149 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2150 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2151 .clkdm_name = "dss_clkdm",
2152 .recalc = &followparent_recalc,
2153 };
2154
2155 static struct clk dss1_alwon_fck_3430es2 = {
2156 .name = "dss1_alwon_fck",
2157 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2158 .parent = &dpll4_m4x2_ck,
2159 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2160 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2161 .clkdm_name = "dss_clkdm",
2162 .recalc = &followparent_recalc,
2163 };
2164
2165 static struct clk dss_tv_fck = {
2166 .name = "dss_tv_fck",
2167 .ops = &clkops_omap2_dflt,
2168 .parent = &omap_54m_fck,
2169 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2170 .enable_bit = OMAP3430_EN_TV_SHIFT,
2171 .clkdm_name = "dss_clkdm",
2172 .recalc = &followparent_recalc,
2173 };
2174
2175 static struct clk dss_96m_fck = {
2176 .name = "dss_96m_fck",
2177 .ops = &clkops_omap2_dflt,
2178 .parent = &omap_96m_fck,
2179 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2180 .enable_bit = OMAP3430_EN_TV_SHIFT,
2181 .clkdm_name = "dss_clkdm",
2182 .recalc = &followparent_recalc,
2183 };
2184
2185 static struct clk dss2_alwon_fck = {
2186 .name = "dss2_alwon_fck",
2187 .ops = &clkops_omap2_dflt,
2188 .parent = &sys_ck,
2189 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2190 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2191 .clkdm_name = "dss_clkdm",
2192 .recalc = &followparent_recalc,
2193 };
2194
2195 static struct clk dss_ick_3430es1 = {
2196 /* Handles both L3 and L4 clocks */
2197 .name = "dss_ick",
2198 .ops = &clkops_omap2_dflt,
2199 .parent = &l4_ick,
2200 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2201 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2202 .clkdm_name = "dss_clkdm",
2203 .recalc = &followparent_recalc,
2204 };
2205
2206 static struct clk dss_ick_3430es2 = {
2207 /* Handles both L3 and L4 clocks */
2208 .name = "dss_ick",
2209 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2210 .parent = &l4_ick,
2211 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2212 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2213 .clkdm_name = "dss_clkdm",
2214 .recalc = &followparent_recalc,
2215 };
2216
2217 /* CAM */
2218
2219 static struct clk cam_mclk = {
2220 .name = "cam_mclk",
2221 .ops = &clkops_omap2_dflt,
2222 .parent = &dpll4_m5x2_ck,
2223 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2224 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2225 .clkdm_name = "cam_clkdm",
2226 .recalc = &followparent_recalc,
2227 };
2228
2229 static struct clk cam_ick = {
2230 /* Handles both L3 and L4 clocks */
2231 .name = "cam_ick",
2232 .ops = &clkops_omap2_dflt,
2233 .parent = &l4_ick,
2234 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2235 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2236 .clkdm_name = "cam_clkdm",
2237 .recalc = &followparent_recalc,
2238 };
2239
2240 static struct clk csi2_96m_fck = {
2241 .name = "csi2_96m_fck",
2242 .ops = &clkops_omap2_dflt,
2243 .parent = &core_96m_fck,
2244 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2245 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
2246 .clkdm_name = "cam_clkdm",
2247 .recalc = &followparent_recalc,
2248 };
2249
2250 /* USBHOST - 3430ES2 only */
2251
2252 static struct clk usbhost_120m_fck = {
2253 .name = "usbhost_120m_fck",
2254 .ops = &clkops_omap2_dflt,
2255 .parent = &dpll5_m2_ck,
2256 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2257 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2258 .clkdm_name = "usbhost_clkdm",
2259 .recalc = &followparent_recalc,
2260 };
2261
2262 static struct clk usbhost_48m_fck = {
2263 .name = "usbhost_48m_fck",
2264 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2265 .parent = &omap_48m_fck,
2266 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2267 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2268 .clkdm_name = "usbhost_clkdm",
2269 .recalc = &followparent_recalc,
2270 };
2271
2272 static struct clk usbhost_ick = {
2273 /* Handles both L3 and L4 clocks */
2274 .name = "usbhost_ick",
2275 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2276 .parent = &l4_ick,
2277 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2278 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2279 .clkdm_name = "usbhost_clkdm",
2280 .recalc = &followparent_recalc,
2281 };
2282
2283 /* WKUP */
2284
2285 static const struct clksel_rate usim_96m_rates[] = {
2286 { .div = 2, .val = 3, .flags = RATE_IN_3XXX },
2287 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2288 { .div = 8, .val = 5, .flags = RATE_IN_3XXX },
2289 { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
2290 { .div = 0 },
2291 };
2292
2293 static const struct clksel_rate usim_120m_rates[] = {
2294 { .div = 4, .val = 7, .flags = RATE_IN_3XXX },
2295 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
2296 { .div = 16, .val = 9, .flags = RATE_IN_3XXX },
2297 { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
2298 { .div = 0 },
2299 };
2300
2301 static const struct clksel usim_clksel[] = {
2302 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2303 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
2304 { .parent = &sys_ck, .rates = div2_rates },
2305 { .parent = NULL },
2306 };
2307
2308 /* 3430ES2 only */
2309 static struct clk usim_fck = {
2310 .name = "usim_fck",
2311 .ops = &clkops_omap2_dflt_wait,
2312 .init = &omap2_init_clksel_parent,
2313 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2314 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2315 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2316 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2317 .clksel = usim_clksel,
2318 .recalc = &omap2_clksel_recalc,
2319 };
2320
2321 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2322 static struct clk gpt1_fck = {
2323 .name = "gpt1_fck",
2324 .ops = &clkops_omap2_dflt_wait,
2325 .init = &omap2_init_clksel_parent,
2326 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2327 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2328 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2329 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2330 .clksel = omap343x_gpt_clksel,
2331 .clkdm_name = "wkup_clkdm",
2332 .recalc = &omap2_clksel_recalc,
2333 };
2334
2335 static struct clk wkup_32k_fck = {
2336 .name = "wkup_32k_fck",
2337 .ops = &clkops_null,
2338 .parent = &omap_32k_fck,
2339 .clkdm_name = "wkup_clkdm",
2340 .recalc = &followparent_recalc,
2341 };
2342
2343 static struct clk gpio1_dbck = {
2344 .name = "gpio1_dbck",
2345 .ops = &clkops_omap2_dflt,
2346 .parent = &wkup_32k_fck,
2347 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2348 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2349 .clkdm_name = "wkup_clkdm",
2350 .recalc = &followparent_recalc,
2351 };
2352
2353 static struct clk wdt2_fck = {
2354 .name = "wdt2_fck",
2355 .ops = &clkops_omap2_dflt_wait,
2356 .parent = &wkup_32k_fck,
2357 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2358 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2359 .clkdm_name = "wkup_clkdm",
2360 .recalc = &followparent_recalc,
2361 };
2362
2363 static struct clk wkup_l4_ick = {
2364 .name = "wkup_l4_ick",
2365 .ops = &clkops_null,
2366 .parent = &sys_ck,
2367 .clkdm_name = "wkup_clkdm",
2368 .recalc = &followparent_recalc,
2369 };
2370
2371 /* 3430ES2 only */
2372 /* Never specifically named in the TRM, so we have to infer a likely name */
2373 static struct clk usim_ick = {
2374 .name = "usim_ick",
2375 .ops = &clkops_omap2_dflt_wait,
2376 .parent = &wkup_l4_ick,
2377 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2378 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2379 .clkdm_name = "wkup_clkdm",
2380 .recalc = &followparent_recalc,
2381 };
2382
2383 static struct clk wdt2_ick = {
2384 .name = "wdt2_ick",
2385 .ops = &clkops_omap2_dflt_wait,
2386 .parent = &wkup_l4_ick,
2387 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2388 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2389 .clkdm_name = "wkup_clkdm",
2390 .recalc = &followparent_recalc,
2391 };
2392
2393 static struct clk wdt1_ick = {
2394 .name = "wdt1_ick",
2395 .ops = &clkops_omap2_dflt_wait,
2396 .parent = &wkup_l4_ick,
2397 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2398 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2399 .clkdm_name = "wkup_clkdm",
2400 .recalc = &followparent_recalc,
2401 };
2402
2403 static struct clk gpio1_ick = {
2404 .name = "gpio1_ick",
2405 .ops = &clkops_omap2_dflt_wait,
2406 .parent = &wkup_l4_ick,
2407 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2408 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2409 .clkdm_name = "wkup_clkdm",
2410 .recalc = &followparent_recalc,
2411 };
2412
2413 static struct clk omap_32ksync_ick = {
2414 .name = "omap_32ksync_ick",
2415 .ops = &clkops_omap2_dflt_wait,
2416 .parent = &wkup_l4_ick,
2417 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2418 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2419 .clkdm_name = "wkup_clkdm",
2420 .recalc = &followparent_recalc,
2421 };
2422
2423 /* XXX This clock no longer exists in 3430 TRM rev F */
2424 static struct clk gpt12_ick = {
2425 .name = "gpt12_ick",
2426 .ops = &clkops_omap2_dflt_wait,
2427 .parent = &wkup_l4_ick,
2428 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2429 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2430 .clkdm_name = "wkup_clkdm",
2431 .recalc = &followparent_recalc,
2432 };
2433
2434 static struct clk gpt1_ick = {
2435 .name = "gpt1_ick",
2436 .ops = &clkops_omap2_dflt_wait,
2437 .parent = &wkup_l4_ick,
2438 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2439 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2440 .clkdm_name = "wkup_clkdm",
2441 .recalc = &followparent_recalc,
2442 };
2443
2444
2445
2446 /* PER clock domain */
2447
2448 static struct clk per_96m_fck = {
2449 .name = "per_96m_fck",
2450 .ops = &clkops_null,
2451 .parent = &omap_96m_alwon_fck,
2452 .clkdm_name = "per_clkdm",
2453 .recalc = &followparent_recalc,
2454 };
2455
2456 static struct clk per_48m_fck = {
2457 .name = "per_48m_fck",
2458 .ops = &clkops_null,
2459 .parent = &omap_48m_fck,
2460 .clkdm_name = "per_clkdm",
2461 .recalc = &followparent_recalc,
2462 };
2463
2464 static struct clk uart3_fck = {
2465 .name = "uart3_fck",
2466 .ops = &clkops_omap2_dflt_wait,
2467 .parent = &per_48m_fck,
2468 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2469 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2470 .clkdm_name = "per_clkdm",
2471 .recalc = &followparent_recalc,
2472 };
2473
2474 static struct clk uart4_fck = {
2475 .name = "uart4_fck",
2476 .ops = &clkops_omap2_dflt_wait,
2477 .parent = &per_48m_fck,
2478 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2479 .enable_bit = OMAP3630_EN_UART4_SHIFT,
2480 .clkdm_name = "per_clkdm",
2481 .recalc = &followparent_recalc,
2482 };
2483
2484 static struct clk gpt2_fck = {
2485 .name = "gpt2_fck",
2486 .ops = &clkops_omap2_dflt_wait,
2487 .init = &omap2_init_clksel_parent,
2488 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2489 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2490 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2491 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2492 .clksel = omap343x_gpt_clksel,
2493 .clkdm_name = "per_clkdm",
2494 .recalc = &omap2_clksel_recalc,
2495 };
2496
2497 static struct clk gpt3_fck = {
2498 .name = "gpt3_fck",
2499 .ops = &clkops_omap2_dflt_wait,
2500 .init = &omap2_init_clksel_parent,
2501 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2502 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2503 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2504 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2505 .clksel = omap343x_gpt_clksel,
2506 .clkdm_name = "per_clkdm",
2507 .recalc = &omap2_clksel_recalc,
2508 };
2509
2510 static struct clk gpt4_fck = {
2511 .name = "gpt4_fck",
2512 .ops = &clkops_omap2_dflt_wait,
2513 .init = &omap2_init_clksel_parent,
2514 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2515 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2516 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2517 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2518 .clksel = omap343x_gpt_clksel,
2519 .clkdm_name = "per_clkdm",
2520 .recalc = &omap2_clksel_recalc,
2521 };
2522
2523 static struct clk gpt5_fck = {
2524 .name = "gpt5_fck",
2525 .ops = &clkops_omap2_dflt_wait,
2526 .init = &omap2_init_clksel_parent,
2527 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2528 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2529 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2530 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2531 .clksel = omap343x_gpt_clksel,
2532 .clkdm_name = "per_clkdm",
2533 .recalc = &omap2_clksel_recalc,
2534 };
2535
2536 static struct clk gpt6_fck = {
2537 .name = "gpt6_fck",
2538 .ops = &clkops_omap2_dflt_wait,
2539 .init = &omap2_init_clksel_parent,
2540 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2541 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2542 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2543 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2544 .clksel = omap343x_gpt_clksel,
2545 .clkdm_name = "per_clkdm",
2546 .recalc = &omap2_clksel_recalc,
2547 };
2548
2549 static struct clk gpt7_fck = {
2550 .name = "gpt7_fck",
2551 .ops = &clkops_omap2_dflt_wait,
2552 .init = &omap2_init_clksel_parent,
2553 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2554 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2555 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2556 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2557 .clksel = omap343x_gpt_clksel,
2558 .clkdm_name = "per_clkdm",
2559 .recalc = &omap2_clksel_recalc,
2560 };
2561
2562 static struct clk gpt8_fck = {
2563 .name = "gpt8_fck",
2564 .ops = &clkops_omap2_dflt_wait,
2565 .init = &omap2_init_clksel_parent,
2566 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2567 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2568 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2569 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2570 .clksel = omap343x_gpt_clksel,
2571 .clkdm_name = "per_clkdm",
2572 .recalc = &omap2_clksel_recalc,
2573 };
2574
2575 static struct clk gpt9_fck = {
2576 .name = "gpt9_fck",
2577 .ops = &clkops_omap2_dflt_wait,
2578 .init = &omap2_init_clksel_parent,
2579 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2580 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2581 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2582 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2583 .clksel = omap343x_gpt_clksel,
2584 .clkdm_name = "per_clkdm",
2585 .recalc = &omap2_clksel_recalc,
2586 };
2587
2588 static struct clk per_32k_alwon_fck = {
2589 .name = "per_32k_alwon_fck",
2590 .ops = &clkops_null,
2591 .parent = &omap_32k_fck,
2592 .clkdm_name = "per_clkdm",
2593 .recalc = &followparent_recalc,
2594 };
2595
2596 static struct clk gpio6_dbck = {
2597 .name = "gpio6_dbck",
2598 .ops = &clkops_omap2_dflt,
2599 .parent = &per_32k_alwon_fck,
2600 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2601 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2602 .clkdm_name = "per_clkdm",
2603 .recalc = &followparent_recalc,
2604 };
2605
2606 static struct clk gpio5_dbck = {
2607 .name = "gpio5_dbck",
2608 .ops = &clkops_omap2_dflt,
2609 .parent = &per_32k_alwon_fck,
2610 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2611 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2612 .clkdm_name = "per_clkdm",
2613 .recalc = &followparent_recalc,
2614 };
2615
2616 static struct clk gpio4_dbck = {
2617 .name = "gpio4_dbck",
2618 .ops = &clkops_omap2_dflt,
2619 .parent = &per_32k_alwon_fck,
2620 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2621 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2622 .clkdm_name = "per_clkdm",
2623 .recalc = &followparent_recalc,
2624 };
2625
2626 static struct clk gpio3_dbck = {
2627 .name = "gpio3_dbck",
2628 .ops = &clkops_omap2_dflt,
2629 .parent = &per_32k_alwon_fck,
2630 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2631 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2632 .clkdm_name = "per_clkdm",
2633 .recalc = &followparent_recalc,
2634 };
2635
2636 static struct clk gpio2_dbck = {
2637 .name = "gpio2_dbck",
2638 .ops = &clkops_omap2_dflt,
2639 .parent = &per_32k_alwon_fck,
2640 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2641 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2642 .clkdm_name = "per_clkdm",
2643 .recalc = &followparent_recalc,
2644 };
2645
2646 static struct clk wdt3_fck = {
2647 .name = "wdt3_fck",
2648 .ops = &clkops_omap2_dflt_wait,
2649 .parent = &per_32k_alwon_fck,
2650 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2651 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2652 .clkdm_name = "per_clkdm",
2653 .recalc = &followparent_recalc,
2654 };
2655
2656 static struct clk per_l4_ick = {
2657 .name = "per_l4_ick",
2658 .ops = &clkops_null,
2659 .parent = &l4_ick,
2660 .clkdm_name = "per_clkdm",
2661 .recalc = &followparent_recalc,
2662 };
2663
2664 static struct clk gpio6_ick = {
2665 .name = "gpio6_ick",
2666 .ops = &clkops_omap2_dflt_wait,
2667 .parent = &per_l4_ick,
2668 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2669 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2670 .clkdm_name = "per_clkdm",
2671 .recalc = &followparent_recalc,
2672 };
2673
2674 static struct clk gpio5_ick = {
2675 .name = "gpio5_ick",
2676 .ops = &clkops_omap2_dflt_wait,
2677 .parent = &per_l4_ick,
2678 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2679 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2680 .clkdm_name = "per_clkdm",
2681 .recalc = &followparent_recalc,
2682 };
2683
2684 static struct clk gpio4_ick = {
2685 .name = "gpio4_ick",
2686 .ops = &clkops_omap2_dflt_wait,
2687 .parent = &per_l4_ick,
2688 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2689 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2690 .clkdm_name = "per_clkdm",
2691 .recalc = &followparent_recalc,
2692 };
2693
2694 static struct clk gpio3_ick = {
2695 .name = "gpio3_ick",
2696 .ops = &clkops_omap2_dflt_wait,
2697 .parent = &per_l4_ick,
2698 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2699 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2700 .clkdm_name = "per_clkdm",
2701 .recalc = &followparent_recalc,
2702 };
2703
2704 static struct clk gpio2_ick = {
2705 .name = "gpio2_ick",
2706 .ops = &clkops_omap2_dflt_wait,
2707 .parent = &per_l4_ick,
2708 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2709 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2710 .clkdm_name = "per_clkdm",
2711 .recalc = &followparent_recalc,
2712 };
2713
2714 static struct clk wdt3_ick = {
2715 .name = "wdt3_ick",
2716 .ops = &clkops_omap2_dflt_wait,
2717 .parent = &per_l4_ick,
2718 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2719 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2720 .clkdm_name = "per_clkdm",
2721 .recalc = &followparent_recalc,
2722 };
2723
2724 static struct clk uart3_ick = {
2725 .name = "uart3_ick",
2726 .ops = &clkops_omap2_dflt_wait,
2727 .parent = &per_l4_ick,
2728 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2729 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2730 .clkdm_name = "per_clkdm",
2731 .recalc = &followparent_recalc,
2732 };
2733
2734 static struct clk uart4_ick = {
2735 .name = "uart4_ick",
2736 .ops = &clkops_omap2_dflt_wait,
2737 .parent = &per_l4_ick,
2738 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2739 .enable_bit = OMAP3630_EN_UART4_SHIFT,
2740 .clkdm_name = "per_clkdm",
2741 .recalc = &followparent_recalc,
2742 };
2743
2744 static struct clk gpt9_ick = {
2745 .name = "gpt9_ick",
2746 .ops = &clkops_omap2_dflt_wait,
2747 .parent = &per_l4_ick,
2748 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2749 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2750 .clkdm_name = "per_clkdm",
2751 .recalc = &followparent_recalc,
2752 };
2753
2754 static struct clk gpt8_ick = {
2755 .name = "gpt8_ick",
2756 .ops = &clkops_omap2_dflt_wait,
2757 .parent = &per_l4_ick,
2758 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2759 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2760 .clkdm_name = "per_clkdm",
2761 .recalc = &followparent_recalc,
2762 };
2763
2764 static struct clk gpt7_ick = {
2765 .name = "gpt7_ick",
2766 .ops = &clkops_omap2_dflt_wait,
2767 .parent = &per_l4_ick,
2768 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2769 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2770 .clkdm_name = "per_clkdm",
2771 .recalc = &followparent_recalc,
2772 };
2773
2774 static struct clk gpt6_ick = {
2775 .name = "gpt6_ick",
2776 .ops = &clkops_omap2_dflt_wait,
2777 .parent = &per_l4_ick,
2778 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2779 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2780 .clkdm_name = "per_clkdm",
2781 .recalc = &followparent_recalc,
2782 };
2783
2784 static struct clk gpt5_ick = {
2785 .name = "gpt5_ick",
2786 .ops = &clkops_omap2_dflt_wait,
2787 .parent = &per_l4_ick,
2788 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2789 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2790 .clkdm_name = "per_clkdm",
2791 .recalc = &followparent_recalc,
2792 };
2793
2794 static struct clk gpt4_ick = {
2795 .name = "gpt4_ick",
2796 .ops = &clkops_omap2_dflt_wait,
2797 .parent = &per_l4_ick,
2798 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2799 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2800 .clkdm_name = "per_clkdm",
2801 .recalc = &followparent_recalc,
2802 };
2803
2804 static struct clk gpt3_ick = {
2805 .name = "gpt3_ick",
2806 .ops = &clkops_omap2_dflt_wait,
2807 .parent = &per_l4_ick,
2808 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2809 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2810 .clkdm_name = "per_clkdm",
2811 .recalc = &followparent_recalc,
2812 };
2813
2814 static struct clk gpt2_ick = {
2815 .name = "gpt2_ick",
2816 .ops = &clkops_omap2_dflt_wait,
2817 .parent = &per_l4_ick,
2818 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2819 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2820 .clkdm_name = "per_clkdm",
2821 .recalc = &followparent_recalc,
2822 };
2823
2824 static struct clk mcbsp2_ick = {
2825 .name = "mcbsp2_ick",
2826 .ops = &clkops_omap2_dflt_wait,
2827 .parent = &per_l4_ick,
2828 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2829 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2830 .clkdm_name = "per_clkdm",
2831 .recalc = &followparent_recalc,
2832 };
2833
2834 static struct clk mcbsp3_ick = {
2835 .name = "mcbsp3_ick",
2836 .ops = &clkops_omap2_dflt_wait,
2837 .parent = &per_l4_ick,
2838 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2839 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2840 .clkdm_name = "per_clkdm",
2841 .recalc = &followparent_recalc,
2842 };
2843
2844 static struct clk mcbsp4_ick = {
2845 .name = "mcbsp4_ick",
2846 .ops = &clkops_omap2_dflt_wait,
2847 .parent = &per_l4_ick,
2848 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2849 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2850 .clkdm_name = "per_clkdm",
2851 .recalc = &followparent_recalc,
2852 };
2853
2854 static const struct clksel mcbsp_234_clksel[] = {
2855 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2856 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2857 { .parent = NULL }
2858 };
2859
2860 static struct clk mcbsp2_fck = {
2861 .name = "mcbsp2_fck",
2862 .ops = &clkops_omap2_dflt_wait,
2863 .init = &omap2_init_clksel_parent,
2864 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2865 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2866 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2867 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2868 .clksel = mcbsp_234_clksel,
2869 .clkdm_name = "per_clkdm",
2870 .recalc = &omap2_clksel_recalc,
2871 };
2872
2873 static struct clk mcbsp3_fck = {
2874 .name = "mcbsp3_fck",
2875 .ops = &clkops_omap2_dflt_wait,
2876 .init = &omap2_init_clksel_parent,
2877 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2878 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2879 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2880 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2881 .clksel = mcbsp_234_clksel,
2882 .clkdm_name = "per_clkdm",
2883 .recalc = &omap2_clksel_recalc,
2884 };
2885
2886 static struct clk mcbsp4_fck = {
2887 .name = "mcbsp4_fck",
2888 .ops = &clkops_omap2_dflt_wait,
2889 .init = &omap2_init_clksel_parent,
2890 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2891 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2892 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2893 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2894 .clksel = mcbsp_234_clksel,
2895 .clkdm_name = "per_clkdm",
2896 .recalc = &omap2_clksel_recalc,
2897 };
2898
2899 /* EMU clocks */
2900
2901 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2902
2903 static const struct clksel_rate emu_src_sys_rates[] = {
2904 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
2905 { .div = 0 },
2906 };
2907
2908 static const struct clksel_rate emu_src_core_rates[] = {
2909 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2910 { .div = 0 },
2911 };
2912
2913 static const struct clksel_rate emu_src_per_rates[] = {
2914 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
2915 { .div = 0 },
2916 };
2917
2918 static const struct clksel_rate emu_src_mpu_rates[] = {
2919 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
2920 { .div = 0 },
2921 };
2922
2923 static const struct clksel emu_src_clksel[] = {
2924 { .parent = &sys_ck, .rates = emu_src_sys_rates },
2925 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2926 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
2927 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
2928 { .parent = NULL },
2929 };
2930
2931 /*
2932 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2933 * to switch the source of some of the EMU clocks.
2934 * XXX Are there CLKEN bits for these EMU clks?
2935 */
2936 static struct clk emu_src_ck = {
2937 .name = "emu_src_ck",
2938 .ops = &clkops_null,
2939 .init = &omap2_init_clksel_parent,
2940 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2941 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2942 .clksel = emu_src_clksel,
2943 .clkdm_name = "emu_clkdm",
2944 .recalc = &omap2_clksel_recalc,
2945 };
2946
2947 static const struct clksel_rate pclk_emu_rates[] = {
2948 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2949 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2950 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2951 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
2952 { .div = 0 },
2953 };
2954
2955 static const struct clksel pclk_emu_clksel[] = {
2956 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2957 { .parent = NULL },
2958 };
2959
2960 static struct clk pclk_fck = {
2961 .name = "pclk_fck",
2962 .ops = &clkops_null,
2963 .init = &omap2_init_clksel_parent,
2964 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2965 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
2966 .clksel = pclk_emu_clksel,
2967 .clkdm_name = "emu_clkdm",
2968 .recalc = &omap2_clksel_recalc,
2969 };
2970
2971 static const struct clksel_rate pclkx2_emu_rates[] = {
2972 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2973 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2974 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2975 { .div = 0 },
2976 };
2977
2978 static const struct clksel pclkx2_emu_clksel[] = {
2979 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2980 { .parent = NULL },
2981 };
2982
2983 static struct clk pclkx2_fck = {
2984 .name = "pclkx2_fck",
2985 .ops = &clkops_null,
2986 .init = &omap2_init_clksel_parent,
2987 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2988 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
2989 .clksel = pclkx2_emu_clksel,
2990 .clkdm_name = "emu_clkdm",
2991 .recalc = &omap2_clksel_recalc,
2992 };
2993
2994 static const struct clksel atclk_emu_clksel[] = {
2995 { .parent = &emu_src_ck, .rates = div2_rates },
2996 { .parent = NULL },
2997 };
2998
2999 static struct clk atclk_fck = {
3000 .name = "atclk_fck",
3001 .ops = &clkops_null,
3002 .init = &omap2_init_clksel_parent,
3003 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3004 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
3005 .clksel = atclk_emu_clksel,
3006 .clkdm_name = "emu_clkdm",
3007 .recalc = &omap2_clksel_recalc,
3008 };
3009
3010 static struct clk traceclk_src_fck = {
3011 .name = "traceclk_src_fck",
3012 .ops = &clkops_null,
3013 .init = &omap2_init_clksel_parent,
3014 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3015 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
3016 .clksel = emu_src_clksel,
3017 .clkdm_name = "emu_clkdm",
3018 .recalc = &omap2_clksel_recalc,
3019 };
3020
3021 static const struct clksel_rate traceclk_rates[] = {
3022 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
3023 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
3024 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3025 { .div = 0 },
3026 };
3027
3028 static const struct clksel traceclk_clksel[] = {
3029 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3030 { .parent = NULL },
3031 };
3032
3033 static struct clk traceclk_fck = {
3034 .name = "traceclk_fck",
3035 .ops = &clkops_null,
3036 .init = &omap2_init_clksel_parent,
3037 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3038 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
3039 .clksel = traceclk_clksel,
3040 .clkdm_name = "emu_clkdm",
3041 .recalc = &omap2_clksel_recalc,
3042 };
3043
3044 /* SR clocks */
3045
3046 /* SmartReflex fclk (VDD1) */
3047 static struct clk sr1_fck = {
3048 .name = "sr1_fck",
3049 .ops = &clkops_omap2_dflt_wait,
3050 .parent = &sys_ck,
3051 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3052 .enable_bit = OMAP3430_EN_SR1_SHIFT,
3053 .clkdm_name = "wkup_clkdm",
3054 .recalc = &followparent_recalc,
3055 };
3056
3057 /* SmartReflex fclk (VDD2) */
3058 static struct clk sr2_fck = {
3059 .name = "sr2_fck",
3060 .ops = &clkops_omap2_dflt_wait,
3061 .parent = &sys_ck,
3062 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3063 .enable_bit = OMAP3430_EN_SR2_SHIFT,
3064 .clkdm_name = "wkup_clkdm",
3065 .recalc = &followparent_recalc,
3066 };
3067
3068 static struct clk sr_l4_ick = {
3069 .name = "sr_l4_ick",
3070 .ops = &clkops_null, /* RMK: missing? */
3071 .parent = &l4_ick,
3072 .clkdm_name = "core_l4_clkdm",
3073 .recalc = &followparent_recalc,
3074 };
3075
3076 /* SECURE_32K_FCK clocks */
3077
3078 static struct clk gpt12_fck = {
3079 .name = "gpt12_fck",
3080 .ops = &clkops_null,
3081 .parent = &secure_32k_fck,
3082 .recalc = &followparent_recalc,
3083 };
3084
3085 static struct clk wdt1_fck = {
3086 .name = "wdt1_fck",
3087 .ops = &clkops_null,
3088 .parent = &secure_32k_fck,
3089 .recalc = &followparent_recalc,
3090 };
3091
3092 /* Clocks for AM35XX */
3093 static struct clk ipss_ick = {
3094 .name = "ipss_ick",
3095 .ops = &clkops_am35xx_ipss_wait,
3096 .parent = &core_l3_ick,
3097 .clkdm_name = "core_l3_clkdm",
3098 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3099 .enable_bit = AM35XX_EN_IPSS_SHIFT,
3100 .recalc = &followparent_recalc,
3101 };
3102
3103 static struct clk emac_ick = {
3104 .name = "emac_ick",
3105 .ops = &clkops_am35xx_ipss_module_wait,
3106 .parent = &ipss_ick,
3107 .clkdm_name = "core_l3_clkdm",
3108 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3109 .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
3110 .recalc = &followparent_recalc,
3111 };
3112
3113 static struct clk rmii_ck = {
3114 .name = "rmii_ck",
3115 .ops = &clkops_null,
3116 .rate = 50000000,
3117 };
3118
3119 static struct clk emac_fck = {
3120 .name = "emac_fck",
3121 .ops = &clkops_omap2_dflt,
3122 .parent = &rmii_ck,
3123 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3124 .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT,
3125 .recalc = &followparent_recalc,
3126 };
3127
3128 static struct clk hsotgusb_ick_am35xx = {
3129 .name = "hsotgusb_ick",
3130 .ops = &clkops_am35xx_ipss_module_wait,
3131 .parent = &ipss_ick,
3132 .clkdm_name = "core_l3_clkdm",
3133 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3134 .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
3135 .recalc = &followparent_recalc,
3136 };
3137
3138 static struct clk hsotgusb_fck_am35xx = {
3139 .name = "hsotgusb_fck",
3140 .ops = &clkops_omap2_dflt,
3141 .parent = &sys_ck,
3142 .clkdm_name = "core_l3_clkdm",
3143 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3144 .enable_bit = AM35XX_USBOTG_FCLK_SHIFT,
3145 .recalc = &followparent_recalc,
3146 };
3147
3148 static struct clk hecc_ck = {
3149 .name = "hecc_ck",
3150 .ops = &clkops_am35xx_ipss_module_wait,
3151 .parent = &sys_ck,
3152 .clkdm_name = "core_l3_clkdm",
3153 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3154 .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT,
3155 .recalc = &followparent_recalc,
3156 };
3157
3158 static struct clk vpfe_ick = {
3159 .name = "vpfe_ick",
3160 .ops = &clkops_am35xx_ipss_module_wait,
3161 .parent = &ipss_ick,
3162 .clkdm_name = "core_l3_clkdm",
3163 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3164 .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3165 .recalc = &followparent_recalc,
3166 };
3167
3168 static struct clk pclk_ck = {
3169 .name = "pclk_ck",
3170 .ops = &clkops_null,
3171 .rate = 27000000,
3172 };
3173
3174 static struct clk vpfe_fck = {
3175 .name = "vpfe_fck",
3176 .ops = &clkops_omap2_dflt,
3177 .parent = &pclk_ck,
3178 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3179 .enable_bit = AM35XX_VPFE_FCLK_SHIFT,
3180 .recalc = &followparent_recalc,
3181 };
3182
3183 /*
3184 * The UART1/2 functional clock acts as the functional
3185 * clock for UART4. No separate fclk control available.
3186 */
3187 static struct clk uart4_ick_am35xx = {
3188 .name = "uart4_ick",
3189 .ops = &clkops_omap2_dflt_wait,
3190 .parent = &core_l4_ick,
3191 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3192 .enable_bit = AM35XX_EN_UART4_SHIFT,
3193 .clkdm_name = "core_l4_clkdm",
3194 .recalc = &followparent_recalc,
3195 };
3196
3197 static struct clk dummy_apb_pclk = {
3198 .name = "apb_pclk",
3199 .ops = &clkops_null,
3200 };
3201
3202 /*
3203 * clkdev
3204 */
3205
3206 /* XXX At some point we should rename this file to clock3xxx_data.c */
3207 static struct omap_clk omap3xxx_clks[] = {
3208 CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX),
3209 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX),
3210 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX),
3211 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX),
3212 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3213 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
3214 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX),
3215 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
3216 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX),
3217 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX),
3218 CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX),
3219 CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_3XXX),
3220 CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_3XXX),
3221 CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_3XXX),
3222 CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_3XXX),
3223 CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_3XXX),
3224 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX),
3225 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX),
3226 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX),
3227 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX),
3228 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
3229 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_34XX | CK_36XX),
3230 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_34XX | CK_36XX),
3231 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX),
3232 CLK(NULL, "core_ck", &core_ck, CK_3XXX),
3233 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX),
3234 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX),
3235 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
3236 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX),
3237 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
3238 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
3239 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX),
3240 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX),
3241 CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
3242 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
3243 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX),
3244 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX),
3245 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX),
3246 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX),
3247 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX),
3248 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX),
3249 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
3250 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX),
3251 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
3252 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX),
3253 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
3254 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX),
3255 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
3256 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX),
3257 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
3258 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3259 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3260 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3261 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
3262 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX),
3263 CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX),
3264 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX),
3265 CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX),
3266 CLK(NULL, "arm_fck", &arm_fck, CK_3XXX),
3267 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
3268 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX),
3269 CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX),
3270 CLK(NULL, "l3_ick", &l3_ick, CK_3XXX),
3271 CLK(NULL, "l4_ick", &l4_ick, CK_3XXX),
3272 CLK(NULL, "rm_ick", &rm_ick, CK_3XXX),
3273 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
3274 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
3275 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
3276 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
3277 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
3278 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_3517 | CK_36XX),
3279 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_3517 | CK_36XX),
3280 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
3281 CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX),
3282 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX),
3283 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_34XX | CK_36XX),
3284 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX),
3285 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX),
3286 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3287 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3288 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3289 CLK("ehci-omap.0", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3290 CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX),
3291 CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX),
3292 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
3293 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3294 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX),
3295 CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX),
3296 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX),
3297 CLK("omap_i2c.3", "fck", &i2c3_fck, CK_3XXX),
3298 CLK("omap_i2c.2", "fck", &i2c2_fck, CK_3XXX),
3299 CLK("omap_i2c.1", "fck", &i2c1_fck, CK_3XXX),
3300 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_3XXX),
3301 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_3XXX),
3302 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX),
3303 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_3XXX),
3304 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_3XXX),
3305 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_3XXX),
3306 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_3XXX),
3307 CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX),
3308 CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX),
3309 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
3310 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
3311 CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
3312 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
3313 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
3314 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
3315 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
3316 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX),
3317 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
3318 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3319 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX),
3320 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX),
3321 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
3322 CLK(NULL, "pka_ick", &pka_ick, CK_34XX | CK_36XX),
3323 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
3324 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3325 CLK("ehci-omap.0", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3326 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3327 CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX),
3328 CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX),
3329 CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX),
3330 CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX),
3331 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX),
3332 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX),
3333 CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX),
3334 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
3335 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
3336 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX),
3337 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX),
3338 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX),
3339 CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX),
3340 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX),
3341 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX),
3342 CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX),
3343 CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX),
3344 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX),
3345 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX),
3346 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX),
3347 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX),
3348 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
3349 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
3350 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX),
3351 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_34XX | CK_36XX),
3352 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
3353 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3354 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
3355 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX),
3356 CLK(NULL, "aes1_ick", &aes1_ick, CK_34XX | CK_36XX),
3357 CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX),
3358 CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX),
3359 CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX),
3360 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
3361 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3362 CLK("omapdss", "tv_fck", &dss_tv_fck, CK_3XXX),
3363 CLK("omapdss", "video_fck", &dss_96m_fck, CK_3XXX),
3364 CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_3XXX),
3365 CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1),
3366 CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3367 CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX),
3368 CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX),
3369 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX),
3370 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3371 CLK("ehci-omap.0", "hs_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3372 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3373 CLK("ehci-omap.0", "fs_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3374 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3375 CLK("ehci-omap.0", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3376 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX),
3377 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
3378 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
3379 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
3380 CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX),
3381 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX),
3382 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX),
3383 CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
3384 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX),
3385 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX),
3386 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3387 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX),
3388 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX),
3389 CLK("omap-mcbsp.2", "prcm_fck", &per_96m_fck, CK_3XXX),
3390 CLK("omap-mcbsp.3", "prcm_fck", &per_96m_fck, CK_3XXX),
3391 CLK("omap-mcbsp.4", "prcm_fck", &per_96m_fck, CK_3XXX),
3392 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX),
3393 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
3394 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
3395 CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX),
3396 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
3397 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
3398 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
3399 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX),
3400 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX),
3401 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX),
3402 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX),
3403 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX),
3404 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
3405 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX),
3406 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX),
3407 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_3XXX),
3408 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_3XXX),
3409 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_3XXX),
3410 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_3XXX),
3411 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_3XXX),
3412 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_3XXX),
3413 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_3XXX),
3414 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_3XXX),
3415 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_3XXX),
3416 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX),
3417 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX),
3418 CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX),
3419 CLK(NULL, "uart4_ick", &uart4_ick, CK_36XX),
3420 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX),
3421 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX),
3422 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX),
3423 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_3XXX),
3424 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_3XXX),
3425 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_3XXX),
3426 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_3XXX),
3427 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_3XXX),
3428 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
3429 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
3430 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
3431 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_3XXX),
3432 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_3XXX),
3433 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_3XXX),
3434 CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX),
3435 CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX),
3436 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX),
3437 CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX),
3438 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
3439 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX),
3440 CLK(NULL, "sr1_fck", &sr1_fck, CK_34XX | CK_36XX),
3441 CLK(NULL, "sr2_fck", &sr2_fck, CK_34XX | CK_36XX),
3442 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_34XX | CK_36XX),
3443 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX),
3444 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX),
3445 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX),
3446 CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
3447 CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
3448 CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
3449 CLK("davinci_emac", "emac_clk", &emac_ick, CK_AM35XX),
3450 CLK("davinci_emac", "phy_clk", &emac_fck, CK_AM35XX),
3451 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
3452 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
3453 CLK("musb-am35x", "ick", &hsotgusb_ick_am35xx, CK_AM35XX),
3454 CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX),
3455 CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
3456 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
3457 };
3458
3459
3460 int __init omap3xxx_clk_init(void)
3461 {
3462 struct omap_clk *c;
3463 u32 cpu_clkflg = 0;
3464
3465 if (cpu_is_omap3517()) {
3466 cpu_mask = RATE_IN_34XX;
3467 cpu_clkflg = CK_3517;
3468 } else if (cpu_is_omap3505()) {
3469 cpu_mask = RATE_IN_34XX;
3470 cpu_clkflg = CK_3505;
3471 } else if (cpu_is_omap3630()) {
3472 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3473 cpu_clkflg = CK_36XX;
3474 } else if (cpu_is_omap34xx()) {
3475 if (omap_rev() == OMAP3430_REV_ES1_0) {
3476 cpu_mask = RATE_IN_3430ES1;
3477 cpu_clkflg = CK_3430ES1;
3478 } else {
3479 /*
3480 * Assume that anything that we haven't matched yet
3481 * has 3430ES2-type clocks.
3482 */
3483 cpu_mask = RATE_IN_3430ES2PLUS;
3484 cpu_clkflg = CK_3430ES2PLUS;
3485 }
3486 } else {
3487 WARN(1, "clock: could not identify OMAP3 variant\n");
3488 }
3489
3490 if (omap3_has_192mhz_clk())
3491 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3492
3493 if (cpu_is_omap3630()) {
3494 /*
3495 * XXX This type of dynamic rewriting of the clock tree is
3496 * deprecated and should be revised soon.
3497 *
3498 * For 3630: override clkops_omap2_dflt_wait for the
3499 * clocks affected from PWRDN reset Limitation
3500 */
3501 dpll3_m3x2_ck.ops =
3502 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3503 dpll4_m2x2_ck.ops =
3504 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3505 dpll4_m3x2_ck.ops =
3506 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3507 dpll4_m4x2_ck.ops =
3508 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3509 dpll4_m5x2_ck.ops =
3510 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3511 dpll4_m6x2_ck.ops =
3512 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3513 }
3514
3515 /*
3516 * XXX This type of dynamic rewriting of the clock tree is
3517 * deprecated and should be revised soon.
3518 */
3519 if (cpu_is_omap3630())
3520 dpll4_dd = dpll4_dd_3630;
3521 else
3522 dpll4_dd = dpll4_dd_34xx;
3523
3524 clk_init(&omap2_clk_functions);
3525
3526 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3527 c++)
3528 clk_preinit(c->lk.clk);
3529
3530 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3531 c++)
3532 if (c->cpu & cpu_clkflg) {
3533 clkdev_add(&c->lk);
3534 clk_register(c->lk.clk);
3535 omap2_init_clk_clkdm(c->lk.clk);
3536 }
3537
3538 recalculate_root_clocks();
3539
3540 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3541 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3542 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
3543
3544 /*
3545 * Only enable those clocks we will need, let the drivers
3546 * enable other clocks as necessary
3547 */
3548 clk_enable_init_clocks();
3549
3550 /*
3551 * Lock DPLL5 and put it in autoidle.
3552 */
3553 if (omap_rev() >= OMAP3430_REV_ES2_0)
3554 omap3_clk_lock_dpll5();
3555
3556 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3557 sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3558 arm_fck_p = clk_get(NULL, "arm_fck");
3559
3560 return 0;
3561 }