2 * arch/arm/mach-pxa/include/mach/irqs.h
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #ifndef __ASM_MACH_IRQS_H
13 #define __ASM_MACH_IRQS_H
15 #ifdef CONFIG_PXA_HAVE_ISA_IRQS
16 #define PXA_ISA_IRQ(x) (x)
17 #define PXA_ISA_IRQ_NUM (16)
19 #define PXA_ISA_IRQ_NUM (0)
22 #define PXA_IRQ(x) (PXA_ISA_IRQ_NUM + (x))
24 #define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */
25 #define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */
26 #define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI,PXA27x) */
27 #define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI,PXA27x) */
28 #define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */
29 #define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt (PXA27x) */
30 #define IRQ_ACIPC0 PXA_IRQ(5) /* AP-CP Communication (PXA930) */
31 #define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */
32 #define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */
33 #define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */
34 #define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */
35 #define IRQ_GPIO1 PXA_IRQ(9) /* GPIO1 Edge Detect */
36 #define IRQ_GPIO_2_x PXA_IRQ(10) /* GPIO[2-x] Edge Detect */
37 #define IRQ_USB PXA_IRQ(11) /* USB Service */
38 #define IRQ_PMU PXA_IRQ(12) /* Performance Monitoring Unit */
39 #define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt (PXA27x) */
40 #define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request (PXA3xx) */
41 #define IRQ_AC97 PXA_IRQ(14) /* AC97 Interrupt */
42 #define IRQ_ASSP PXA_IRQ(15) /* Audio SSP Service Request (PXA25x) */
43 #define IRQ_USIM PXA_IRQ(15) /* Smart Card interface interrupt (PXA27x) */
44 #define IRQ_NSSP PXA_IRQ(16) /* Network SSP Service Request (PXA25x) */
45 #define IRQ_SSP2 PXA_IRQ(16) /* SSP2 interrupt (PXA27x) */
46 #define IRQ_LCD PXA_IRQ(17) /* LCD Controller Service Request */
47 #define IRQ_I2C PXA_IRQ(18) /* I2C Service Request */
48 #define IRQ_ICP PXA_IRQ(19) /* ICP Transmit/Receive/Error */
49 #define IRQ_ACIPC2 PXA_IRQ(19) /* AP-CP Communication (PXA930) */
50 #define IRQ_STUART PXA_IRQ(20) /* STUART Transmit/Receive/Error */
51 #define IRQ_BTUART PXA_IRQ(21) /* BTUART Transmit/Receive/Error */
52 #define IRQ_FFUART PXA_IRQ(22) /* FFUART Transmit/Receive/Error*/
53 #define IRQ_MMC PXA_IRQ(23) /* MMC Status/Error Detection */
54 #define IRQ_SSP PXA_IRQ(24) /* SSP Service Request */
55 #define IRQ_DMA PXA_IRQ(25) /* DMA Channel Service Request */
56 #define IRQ_OST0 PXA_IRQ(26) /* OS Timer match 0 */
57 #define IRQ_OST1 PXA_IRQ(27) /* OS Timer match 1 */
58 #define IRQ_OST2 PXA_IRQ(28) /* OS Timer match 2 */
59 #define IRQ_OST3 PXA_IRQ(29) /* OS Timer match 3 */
60 #define IRQ_RTC1Hz PXA_IRQ(30) /* RTC HZ Clock Tick */
61 #define IRQ_RTCAlrm PXA_IRQ(31) /* RTC Alarm */
63 #define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */
64 #define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */
65 #define IRQ_CIR PXA_IRQ(34) /* Consumer IR */
66 #define IRQ_COMM_WDT PXA_IRQ(35) /* Comm WDT interrupt */
67 #define IRQ_TSI PXA_IRQ(36) /* Touch Screen Interface (PXA320) */
68 #define IRQ_ENHROT PXA_IRQ(37) /* Enhanced Rotary (PXA930) */
69 #define IRQ_USIM2 PXA_IRQ(38) /* USIM2 Controller */
70 #define IRQ_GCU PXA_IRQ(39) /* Graphics Controller (PXA3xx) */
71 #define IRQ_ACIPC1 PXA_IRQ(40) /* AP-CP Communication (PXA930) */
72 #define IRQ_MMC2 PXA_IRQ(41) /* MMC2 Controller */
73 #define IRQ_TRKBALL PXA_IRQ(43) /* Track Ball (PXA930) */
74 #define IRQ_1WIRE PXA_IRQ(44) /* 1-Wire Controller */
75 #define IRQ_NAND PXA_IRQ(45) /* NAND Controller */
76 #define IRQ_USB2 PXA_IRQ(46) /* USB 2.0 Device Controller */
77 #define IRQ_WAKEUP0 PXA_IRQ(49) /* EXT_WAKEUP0 */
78 #define IRQ_WAKEUP1 PXA_IRQ(50) /* EXT_WAKEUP1 */
79 #define IRQ_DMEMC PXA_IRQ(51) /* Dynamic Memory Controller */
80 #define IRQ_MMC3 PXA_IRQ(55) /* MMC3 Controller (PXA310) */
82 #define IRQ_U2O PXA_IRQ(64) /* USB OTG 2.0 Controller (PXA935) */
83 #define IRQ_U2H PXA_IRQ(65) /* USB Host 2.0 Controller (PXA935) */
84 #define IRQ_PXA935_MMC0 PXA_IRQ(72) /* MMC0 Controller (PXA935) */
85 #define IRQ_PXA935_MMC1 PXA_IRQ(73) /* MMC1 Controller (PXA935) */
86 #define IRQ_PXA935_MMC2 PXA_IRQ(74) /* MMC2 Controller (PXA935) */
87 #define IRQ_PXA955_MMC3 PXA_IRQ(75) /* MMC3 Controller (PXA955) */
88 #define IRQ_U2P PXA_IRQ(93) /* USB PHY D+/D- Lines (PXA935) */
90 #define PXA_GPIO_IRQ_BASE PXA_IRQ(96)
91 #define PXA_GPIO_IRQ_NUM (192)
93 #define GPIO_2_x_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x))
94 #define IRQ_GPIO(x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x))
96 #define IRQ_TO_GPIO_2_x(i) ((i) - PXA_GPIO_IRQ_BASE)
97 #define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i))
100 * The following interrupts are for board specific purposes. Since
101 * the kernel can only run on one machine at a time, we can re-use
103 * By default, no board IRQ is reserved. It should be finished in
104 * custom board since sparse IRQ is already enabled.
106 #define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM)
108 #define NR_IRQS (IRQ_BOARD_START)
110 #endif /* __ASM_MACH_IRQS_H */
