1 #ifndef __ASM_ARCH_REGS_UART_H
2 #define __ASM_ARCH_REGS_UART_H
8 /* Full Function UART (FFUART) */
10 #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
11 #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
12 #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
13 #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
14 #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
15 #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
16 #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
17 #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
18 #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
19 #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
20 #define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
21 #define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
22 #define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
24 /* Bluetooth UART (BTUART) */
26 #define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */
27 #define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
28 #define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */
29 #define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */
30 #define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
31 #define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */
32 #define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */
33 #define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
34 #define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */
35 #define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */
36 #define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */
37 #define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
38 #define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
40 /* Standard UART (STUART) */
42 #define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */
43 #define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
44 #define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */
45 #define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */
46 #define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
47 #define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */
48 #define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */
49 #define STLSR __REG(0x40700014) /* Line Status Register (read only) */
50 #define STMSR __REG(0x40700018) /* Reserved */
51 #define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */
52 #define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */
53 #define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
54 #define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
56 /* Hardware UART (HWUART) */
58 #define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */
59 #define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */
60 #define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */
61 #define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */
62 #define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */
63 #define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */
64 #define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */
65 #define HWLSR __REG(0x41600014) /* Line Status Register (read only) */
66 #define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */
67 #define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */
68 #define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */
69 #define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */
70 #define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */
71 #define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */
72 #define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
73 #define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
75 #define IER_DMAE (1 << 7) /* DMA Requests Enable */
76 #define IER_UUE (1 << 6) /* UART Unit Enable */
77 #define IER_NRZE (1 << 5) /* NRZ coding Enable */
78 #define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
79 #define IER_MIE (1 << 3) /* Modem Interrupt Enable */
80 #define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
81 #define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
82 #define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
84 #define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
85 #define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
86 #define IIR_TOD (1 << 3) /* Time Out Detected */
87 #define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
88 #define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
89 #define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
91 #define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
92 #define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
93 #define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
94 #define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
95 #define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
97 #define FCR_ITL_8 (FCR_ITL1)
98 #define FCR_ITL_16 (FCR_ITL2)
99 #define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
101 #define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
102 #define LCR_SB (1 << 6) /* Set Break */
103 #define LCR_STKYP (1 << 5) /* Sticky Parity */
104 #define LCR_EPS (1 << 4) /* Even Parity Select */
105 #define LCR_PEN (1 << 3) /* Parity Enable */
106 #define LCR_STB (1 << 2) /* Stop Bit */
107 #define LCR_WLS1 (1 << 1) /* Word Length Select */
108 #define LCR_WLS0 (1 << 0) /* Word Length Select */
110 #define LSR_FIFOE (1 << 7) /* FIFO Error Status */
111 #define LSR_TEMT (1 << 6) /* Transmitter Empty */
112 #define LSR_TDRQ (1 << 5) /* Transmit Data Request */
113 #define LSR_BI (1 << 4) /* Break Interrupt */
114 #define LSR_FE (1 << 3) /* Framing Error */
115 #define LSR_PE (1 << 2) /* Parity Error */
116 #define LSR_OE (1 << 1) /* Overrun Error */
117 #define LSR_DR (1 << 0) /* Data Ready */
119 #define MCR_LOOP (1 << 4)
120 #define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
121 #define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
122 #define MCR_RTS (1 << 1) /* Request to Send */
123 #define MCR_DTR (1 << 0) /* Data Terminal Ready */
125 #define MSR_DCD (1 << 7) /* Data Carrier Detect */
126 #define MSR_RI (1 << 6) /* Ring Indicator */
127 #define MSR_DSR (1 << 5) /* Data Set Ready */
128 #define MSR_CTS (1 << 4) /* Clear To Send */
129 #define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
130 #define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
131 #define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
132 #define MSR_DCTS (1 << 0) /* Delta Clear To Send */
135 * IrSR (Infrared Selection Register)
137 #define STISR_RXPL (1 << 4) /* Receive Data Polarity */
138 #define STISR_TXPL (1 << 3) /* Transmit Data Polarity */
139 #define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */
140 #define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */
141 #define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */
143 #endif /* __ASM_ARCH_REGS_UART_H */
