drivers/gpu/drm/nouveau/nv50_display.h

   1 /*
   2  * Copyright (C) 2008 Maarten Maathuis.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #ifndef __NV50_DISPLAY_H__
  28 #define __NV50_DISPLAY_H__
  29
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "nouveau_drv.h"
  33 #include "nouveau_dma.h"
  34 #include "nouveau_reg.h"
  35 #include "nouveau_crtc.h"
  36 #include "nv50_evo.h"
  37
  38 struct nv50_display_crtc {
  39         struct nouveau_channel *sync;
  40         struct {
  41                 struct nouveau_bo *bo;
  42                 u32 offset;
  43                 u16 value;
  44         } sem;
  45 };
  46
  47 struct nv50_display {
  48         struct nouveau_channel *master;
  49         struct nouveau_gpuobj *ntfy;
  50
  51         struct nv50_display_crtc crtc[2];
  52
  53         struct tasklet_struct tasklet;
  54         struct {
  55                 struct dcb_entry *dcb;
  56                 u16 script;
  57                 u32 pclk;
  58         } irq;
  59 };
  60
  61 static inline struct nv50_display *
  62 nv50_display(struct drm_device *dev)
  63 {
  64         struct drm_nouveau_private *dev_priv = dev->dev_private;
  65         return dev_priv->engine.display.priv;
  66 }
  67
  68 int nv50_display_early_init(struct drm_device *dev);
  69 void nv50_display_late_takedown(struct drm_device *dev);
  70 int nv50_display_create(struct drm_device *dev);
  71 int nv50_display_init(struct drm_device *dev);
  72 void nv50_display_fini(struct drm_device *dev);
  73 void nv50_display_destroy(struct drm_device *dev);
  74 int nv50_crtc_blank(struct nouveau_crtc *, bool blank);
  75 int nv50_crtc_set_clock(struct drm_device *, int head, int pclk);
  76
  77 int  nv50_display_sync(struct drm_device *);
  78 int  nv50_display_flip_next(struct drm_crtc *, struct drm_framebuffer *,
  79                             struct nouveau_channel *chan);
  80 void nv50_display_flip_stop(struct drm_crtc *);
  81
  82 int  nv50_evo_create(struct drm_device *dev);
  83 void nv50_evo_destroy(struct drm_device *dev);
  84 int  nv50_evo_init(struct drm_device *dev);
  85 void nv50_evo_fini(struct drm_device *dev);
  86 void nv50_evo_dmaobj_init(struct nouveau_gpuobj *, u32 memtype, u64 base,
  87                           u64 size);
  88 int  nv50_evo_dmaobj_new(struct nouveau_channel *, u32 handle, u32 memtype,
  89                          u64 base, u64 size, struct nouveau_gpuobj **);
  90
  91 #endif /* __NV50_DISPLAY_H__ */