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percpu, x86: don't use PMD_SIZE as embedded atom_size on 32bit
[zen-stable.git] / drivers / gpu / drm / radeon / r300.c
blob6829638cca4032810822d5eb766d61f0f7658ee3
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include <drm/drmP.h>
31 #include <drm/drm.h>
32 #include <drm/drm_crtc_helper.h>
33 #include "radeon_reg.h"
34 #include "radeon.h"
35 #include "radeon_asic.h"
36 #include "radeon_drm.h"
37 #include "r100_track.h"
38 #include "r300d.h"
39 #include "rv350d.h"
40 #include "r300_reg_safe.h"
41
42 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
43 *
44 * GPU Errata:
45 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
46 * using MMIO to flush host path read cache, this lead to HARDLOCKUP.
47 * However, scheduling such write to the ring seems harmless, i suspect
48 * the CP read collide with the flush somehow, or maybe the MC, hard to
49 * tell. (Jerome Glisse)
50 */
51
52 /*
53 * rv370,rv380 PCIE GART
54 */
55 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
56
57 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
58 {
59 uint32_t tmp;
60 int i;
61
62 /* Workaround HW bug do flush 2 times */
63 for (i = 0; i < 2; i++) {
64 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
65 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
66 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
67 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
68 }
69 mb();
70 }
71
72 #define R300_PTE_WRITEABLE (1 << 2)
73 #define R300_PTE_READABLE (1 << 3)
74
75 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
76 {
77 void __iomem *ptr = rdev->gart.ptr;
78
79 if (i < 0 || i > rdev->gart.num_gpu_pages) {
80 return -EINVAL;
81 }
82 addr = (lower_32_bits(addr) >> 8) |
83 ((upper_32_bits(addr) & 0xff) << 24) |
84 R300_PTE_WRITEABLE | R300_PTE_READABLE;
85 /* on x86 we want this to be CPU endian, on powerpc
86 * on powerpc without HW swappers, it'll get swapped on way
87 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
88 writel(addr, ((void __iomem *)ptr) + (i * 4));
89 return 0;
90 }
91
92 int rv370_pcie_gart_init(struct radeon_device *rdev)
93 {
94 int r;
95
96 if (rdev->gart.robj) {
97 WARN(1, "RV370 PCIE GART already initialized\n");
98 return 0;
99 }
100 /* Initialize common gart structure */
101 r = radeon_gart_init(rdev);
102 if (r)
103 return r;
104 r = rv370_debugfs_pcie_gart_info_init(rdev);
105 if (r)
106 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
107 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
108 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
109 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
110 return radeon_gart_table_vram_alloc(rdev);
111 }
112
113 int rv370_pcie_gart_enable(struct radeon_device *rdev)
114 {
115 uint32_t table_addr;
116 uint32_t tmp;
117 int r;
118
119 if (rdev->gart.robj == NULL) {
120 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
121 return -EINVAL;
122 }
123 r = radeon_gart_table_vram_pin(rdev);
124 if (r)
125 return r;
126 radeon_gart_restore(rdev);
127 /* discard memory request outside of configured range */
128 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
129 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
130 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
131 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
132 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
133 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
134 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
135 table_addr = rdev->gart.table_addr;
136 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
137 /* FIXME: setup default page */
138 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
139 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
140 /* Clear error */
141 WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0);
142 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
143 tmp |= RADEON_PCIE_TX_GART_EN;
144 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
145 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
146 rv370_pcie_gart_tlb_flush(rdev);
147 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
148 (unsigned)(rdev->mc.gtt_size >> 20),
149 (unsigned long long)table_addr);
150 rdev->gart.ready = true;
151 return 0;
152 }
153
154 void rv370_pcie_gart_disable(struct radeon_device *rdev)
155 {
156 u32 tmp;
157
158 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0);
159 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0);
160 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
161 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
162 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
163 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
164 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
165 radeon_gart_table_vram_unpin(rdev);
166 }
167
168 void rv370_pcie_gart_fini(struct radeon_device *rdev)
169 {
170 radeon_gart_fini(rdev);
171 rv370_pcie_gart_disable(rdev);
172 radeon_gart_table_vram_free(rdev);
173 }
174
175 void r300_fence_ring_emit(struct radeon_device *rdev,
176 struct radeon_fence *fence)
177 {
178 struct radeon_ring *ring = &rdev->ring[fence->ring];
179
180 /* Who ever call radeon_fence_emit should call ring_lock and ask
181 * for enough space (today caller are ib schedule and buffer move) */
182 /* Write SC register so SC & US assert idle */
183 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0));
184 radeon_ring_write(ring, 0);
185 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0));
186 radeon_ring_write(ring, 0);
187 /* Flush 3D cache */
188 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
189 radeon_ring_write(ring, R300_RB3D_DC_FLUSH);
190 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
191 radeon_ring_write(ring, R300_ZC_FLUSH);
192 /* Wait until IDLE & CLEAN */
193 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
194 radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN |
195 RADEON_WAIT_2D_IDLECLEAN |
196 RADEON_WAIT_DMA_GUI_IDLE));
197 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
198 radeon_ring_write(ring, rdev->config.r300.hdp_cntl |
199 RADEON_HDP_READ_BUFFER_INVALIDATE);
200 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
201 radeon_ring_write(ring, rdev->config.r300.hdp_cntl);
202 /* Emit fence sequence & fire IRQ */
203 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
204 radeon_ring_write(ring, fence->seq);
205 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
206 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
207 }
208
209 void r300_ring_start(struct radeon_device *rdev)
210 {
211 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
212 unsigned gb_tile_config;
213 int r;
214
215 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
216 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
217 switch(rdev->num_gb_pipes) {
218 case 2:
219 gb_tile_config |= R300_PIPE_COUNT_R300;
220 break;
221 case 3:
222 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
223 break;
224 case 4:
225 gb_tile_config |= R300_PIPE_COUNT_R420;
226 break;
227 case 1:
228 default:
229 gb_tile_config |= R300_PIPE_COUNT_RV350;
230 break;
231 }
232
233 r = radeon_ring_lock(rdev, ring, 64);
234 if (r) {
235 return;
236 }
237 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
238 radeon_ring_write(ring,
239 RADEON_ISYNC_ANY2D_IDLE3D |
240 RADEON_ISYNC_ANY3D_IDLE2D |
241 RADEON_ISYNC_WAIT_IDLEGUI |
242 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
243 radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0));
244 radeon_ring_write(ring, gb_tile_config);
245 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
246 radeon_ring_write(ring,
247 RADEON_WAIT_2D_IDLECLEAN |
248 RADEON_WAIT_3D_IDLECLEAN);
249 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
250 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
251 radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0));
252 radeon_ring_write(ring, 0);
253 radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0));
254 radeon_ring_write(ring, 0);
255 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
256 radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
257 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
258 radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);
259 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
260 radeon_ring_write(ring,
261 RADEON_WAIT_2D_IDLECLEAN |
262 RADEON_WAIT_3D_IDLECLEAN);
263 radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0));
264 radeon_ring_write(ring, 0);
265 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
266 radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
267 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
268 radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);
269 radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0));
270 radeon_ring_write(ring,
271 ((6 << R300_MS_X0_SHIFT) |
272 (6 << R300_MS_Y0_SHIFT) |
273 (6 << R300_MS_X1_SHIFT) |
274 (6 << R300_MS_Y1_SHIFT) |
275 (6 << R300_MS_X2_SHIFT) |
276 (6 << R300_MS_Y2_SHIFT) |
277 (6 << R300_MSBD0_Y_SHIFT) |
278 (6 << R300_MSBD0_X_SHIFT)));
279 radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0));
280 radeon_ring_write(ring,
281 ((6 << R300_MS_X3_SHIFT) |
282 (6 << R300_MS_Y3_SHIFT) |
283 (6 << R300_MS_X4_SHIFT) |
284 (6 << R300_MS_Y4_SHIFT) |
285 (6 << R300_MS_X5_SHIFT) |
286 (6 << R300_MS_Y5_SHIFT) |
287 (6 << R300_MSBD1_SHIFT)));
288 radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0));
289 radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
290 radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0));
291 radeon_ring_write(ring,
292 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
293 radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0));
294 radeon_ring_write(ring,
295 R300_GEOMETRY_ROUND_NEAREST |
296 R300_COLOR_ROUND_NEAREST);
297 radeon_ring_unlock_commit(rdev, ring);
298 }
299
300 void r300_errata(struct radeon_device *rdev)
301 {
302 rdev->pll_errata = 0;
303
304 if (rdev->family == CHIP_R300 &&
305 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
306 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
307 }
308 }
309
310 int r300_mc_wait_for_idle(struct radeon_device *rdev)
311 {
312 unsigned i;
313 uint32_t tmp;
314
315 for (i = 0; i < rdev->usec_timeout; i++) {
316 /* read MC_STATUS */
317 tmp = RREG32(RADEON_MC_STATUS);
318 if (tmp & R300_MC_IDLE) {
319 return 0;
320 }
321 DRM_UDELAY(1);
322 }
323 return -1;
324 }
325
326 void r300_gpu_init(struct radeon_device *rdev)
327 {
328 uint32_t gb_tile_config, tmp;
329
330 if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
331 (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) {
332 /* r300,r350 */
333 rdev->num_gb_pipes = 2;
334 } else {
335 /* rv350,rv370,rv380,r300 AD, r350 AH */
336 rdev->num_gb_pipes = 1;
337 }
338 rdev->num_z_pipes = 1;
339 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
340 switch (rdev->num_gb_pipes) {
341 case 2:
342 gb_tile_config |= R300_PIPE_COUNT_R300;
343 break;
344 case 3:
345 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
346 break;
347 case 4:
348 gb_tile_config |= R300_PIPE_COUNT_R420;
349 break;
350 default:
351 case 1:
352 gb_tile_config |= R300_PIPE_COUNT_RV350;
353 break;
354 }
355 WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
356
357 if (r100_gui_wait_for_idle(rdev)) {
358 printk(KERN_WARNING "Failed to wait GUI idle while "
359 "programming pipes. Bad things might happen.\n");
360 }
361
362 tmp = RREG32(R300_DST_PIPE_CONFIG);
363 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
364
365 WREG32(R300_RB2D_DSTCACHE_MODE,
366 R300_DC_AUTOFLUSH_ENABLE |
367 R300_DC_DC_DISABLE_IGNORE_PE);
368
369 if (r100_gui_wait_for_idle(rdev)) {
370 printk(KERN_WARNING "Failed to wait GUI idle while "
371 "programming pipes. Bad things might happen.\n");
372 }
373 if (r300_mc_wait_for_idle(rdev)) {
374 printk(KERN_WARNING "Failed to wait MC idle while "
375 "programming pipes. Bad things might happen.\n");
376 }
377 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
378 rdev->num_gb_pipes, rdev->num_z_pipes);
379 }
380
381 bool r300_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
382 {
383 u32 rbbm_status;
384 int r;
385
386 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
387 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
388 r100_gpu_lockup_update(&rdev->config.r300.lockup, ring);
389 return false;
390 }
391 /* force CP activities */
392 r = radeon_ring_lock(rdev, ring, 2);
393 if (!r) {
394 /* PACKET2 NOP */
395 radeon_ring_write(ring, 0x80000000);
396 radeon_ring_write(ring, 0x80000000);
397 radeon_ring_unlock_commit(rdev, ring);
398 }
399 ring->rptr = RREG32(RADEON_CP_RB_RPTR);
400 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, ring);
401 }
402
403 int r300_asic_reset(struct radeon_device *rdev)
404 {
405 struct r100_mc_save save;
406 u32 status, tmp;
407 int ret = 0;
408
409 status = RREG32(R_000E40_RBBM_STATUS);
410 if (!G_000E40_GUI_ACTIVE(status)) {
411 return 0;
412 }
413 r100_mc_stop(rdev, &save);
414 status = RREG32(R_000E40_RBBM_STATUS);
415 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
416 /* stop CP */
417 WREG32(RADEON_CP_CSQ_CNTL, 0);
418 tmp = RREG32(RADEON_CP_RB_CNTL);
419 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
420 WREG32(RADEON_CP_RB_RPTR_WR, 0);
421 WREG32(RADEON_CP_RB_WPTR, 0);
422 WREG32(RADEON_CP_RB_CNTL, tmp);
423 /* save PCI state */
424 pci_save_state(rdev->pdev);
425 /* disable bus mastering */
426 r100_bm_disable(rdev);
427 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
428 S_0000F0_SOFT_RESET_GA(1));
429 RREG32(R_0000F0_RBBM_SOFT_RESET);
430 mdelay(500);
431 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
432 mdelay(1);
433 status = RREG32(R_000E40_RBBM_STATUS);
434 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
435 /* resetting the CP seems to be problematic sometimes it end up
436 * hard locking the computer, but it's necessary for successful
437 * reset more test & playing is needed on R3XX/R4XX to find a
438 * reliable (if any solution)
439 */
440 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
441 RREG32(R_0000F0_RBBM_SOFT_RESET);
442 mdelay(500);
443 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
444 mdelay(1);
445 status = RREG32(R_000E40_RBBM_STATUS);
446 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
447 /* restore PCI & busmastering */
448 pci_restore_state(rdev->pdev);
449 r100_enable_bm(rdev);
450 /* Check if GPU is idle */
451 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
452 dev_err(rdev->dev, "failed to reset GPU\n");
453 rdev->gpu_lockup = true;
454 ret = -1;
455 } else
456 dev_info(rdev->dev, "GPU reset succeed\n");
457 r100_mc_resume(rdev, &save);
458 return ret;
459 }
460
461 /*
462 * r300,r350,rv350,rv380 VRAM info
463 */
464 void r300_mc_init(struct radeon_device *rdev)
465 {
466 u64 base;
467 u32 tmp;
468
469 /* DDR for all card after R300 & IGP */
470 rdev->mc.vram_is_ddr = true;
471 tmp = RREG32(RADEON_MEM_CNTL);
472 tmp &= R300_MEM_NUM_CHANNELS_MASK;
473 switch (tmp) {
474 case 0: rdev->mc.vram_width = 64; break;
475 case 1: rdev->mc.vram_width = 128; break;
476 case 2: rdev->mc.vram_width = 256; break;
477 default: rdev->mc.vram_width = 128; break;
478 }
479 r100_vram_init_sizes(rdev);
480 base = rdev->mc.aper_base;
481 if (rdev->flags & RADEON_IS_IGP)
482 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
483 radeon_vram_location(rdev, &rdev->mc, base);
484 rdev->mc.gtt_base_align = 0;
485 if (!(rdev->flags & RADEON_IS_AGP))
486 radeon_gtt_location(rdev, &rdev->mc);
487 radeon_update_bandwidth_info(rdev);
488 }
489
490 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
491 {
492 uint32_t link_width_cntl, mask;
493
494 if (rdev->flags & RADEON_IS_IGP)
495 return;
496
497 if (!(rdev->flags & RADEON_IS_PCIE))
498 return;
499
500 /* FIXME wait for idle */
501
502 switch (lanes) {
503 case 0:
504 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
505 break;
506 case 1:
507 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
508 break;
509 case 2:
510 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
511 break;
512 case 4:
513 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
514 break;
515 case 8:
516 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
517 break;
518 case 12:
519 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
520 break;
521 case 16:
522 default:
523 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
524 break;
525 }
526
527 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
528
529 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
530 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
531 return;
532
533 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
534 RADEON_PCIE_LC_RECONFIG_NOW |
535 RADEON_PCIE_LC_RECONFIG_LATER |
536 RADEON_PCIE_LC_SHORT_RECONFIG_EN);
537 link_width_cntl |= mask;
538 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
539 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
540 RADEON_PCIE_LC_RECONFIG_NOW));
541
542 /* wait for lane set to complete */
543 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
544 while (link_width_cntl == 0xffffffff)
545 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
546
547 }
548
549 int rv370_get_pcie_lanes(struct radeon_device *rdev)
550 {
551 u32 link_width_cntl;
552
553 if (rdev->flags & RADEON_IS_IGP)
554 return 0;
555
556 if (!(rdev->flags & RADEON_IS_PCIE))
557 return 0;
558
559 /* FIXME wait for idle */
560
561 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
562
563 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
564 case RADEON_PCIE_LC_LINK_WIDTH_X0:
565 return 0;
566 case RADEON_PCIE_LC_LINK_WIDTH_X1:
567 return 1;
568 case RADEON_PCIE_LC_LINK_WIDTH_X2:
569 return 2;
570 case RADEON_PCIE_LC_LINK_WIDTH_X4:
571 return 4;
572 case RADEON_PCIE_LC_LINK_WIDTH_X8:
573 return 8;
574 case RADEON_PCIE_LC_LINK_WIDTH_X16:
575 default:
576 return 16;
577 }
578 }
579
580 #if defined(CONFIG_DEBUG_FS)
581 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
582 {
583 struct drm_info_node *node = (struct drm_info_node *) m->private;
584 struct drm_device *dev = node->minor->dev;
585 struct radeon_device *rdev = dev->dev_private;
586 uint32_t tmp;
587
588 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
589 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
590 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
591 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
592 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
593 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
594 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
595 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
596 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
597 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
598 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
599 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
600 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
601 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
602 return 0;
603 }
604
605 static struct drm_info_list rv370_pcie_gart_info_list[] = {
606 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
607 };
608 #endif
609
610 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
611 {
612 #if defined(CONFIG_DEBUG_FS)
613 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
614 #else
615 return 0;
616 #endif
617 }
618
619 static int r300_packet0_check(struct radeon_cs_parser *p,
620 struct radeon_cs_packet *pkt,
621 unsigned idx, unsigned reg)
622 {
623 struct radeon_cs_reloc *reloc;
624 struct r100_cs_track *track;
625 volatile uint32_t *ib;
626 uint32_t tmp, tile_flags = 0;
627 unsigned i;
628 int r;
629 u32 idx_value;
630
631 ib = p->ib->ptr;
632 track = (struct r100_cs_track *)p->track;
633 idx_value = radeon_get_ib_value(p, idx);
634
635 switch(reg) {
636 case AVIVO_D1MODE_VLINE_START_END:
637 case RADEON_CRTC_GUI_TRIG_VLINE:
638 r = r100_cs_packet_parse_vline(p);
639 if (r) {
640 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
641 idx, reg);
642 r100_cs_dump_packet(p, pkt);
643 return r;
644 }
645 break;
646 case RADEON_DST_PITCH_OFFSET:
647 case RADEON_SRC_PITCH_OFFSET:
648 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
649 if (r)
650 return r;
651 break;
652 case R300_RB3D_COLOROFFSET0:
653 case R300_RB3D_COLOROFFSET1:
654 case R300_RB3D_COLOROFFSET2:
655 case R300_RB3D_COLOROFFSET3:
656 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
657 r = r100_cs_packet_next_reloc(p, &reloc);
658 if (r) {
659 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
660 idx, reg);
661 r100_cs_dump_packet(p, pkt);
662 return r;
663 }
664 track->cb[i].robj = reloc->robj;
665 track->cb[i].offset = idx_value;
666 track->cb_dirty = true;
667 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
668 break;
669 case R300_ZB_DEPTHOFFSET:
670 r = r100_cs_packet_next_reloc(p, &reloc);
671 if (r) {
672 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
673 idx, reg);
674 r100_cs_dump_packet(p, pkt);
675 return r;
676 }
677 track->zb.robj = reloc->robj;
678 track->zb.offset = idx_value;
679 track->zb_dirty = true;
680 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
681 break;
682 case R300_TX_OFFSET_0:
683 case R300_TX_OFFSET_0+4:
684 case R300_TX_OFFSET_0+8:
685 case R300_TX_OFFSET_0+12:
686 case R300_TX_OFFSET_0+16:
687 case R300_TX_OFFSET_0+20:
688 case R300_TX_OFFSET_0+24:
689 case R300_TX_OFFSET_0+28:
690 case R300_TX_OFFSET_0+32:
691 case R300_TX_OFFSET_0+36:
692 case R300_TX_OFFSET_0+40:
693 case R300_TX_OFFSET_0+44:
694 case R300_TX_OFFSET_0+48:
695 case R300_TX_OFFSET_0+52:
696 case R300_TX_OFFSET_0+56:
697 case R300_TX_OFFSET_0+60:
698 i = (reg - R300_TX_OFFSET_0) >> 2;
699 r = r100_cs_packet_next_reloc(p, &reloc);
700 if (r) {
701 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
702 idx, reg);
703 r100_cs_dump_packet(p, pkt);
704 return r;
705 }
706
707 if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) {
708 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */
709 ((idx_value & ~31) + (u32)reloc->lobj.gpu_offset);
710 } else {
711 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
712 tile_flags |= R300_TXO_MACRO_TILE;
713 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
714 tile_flags |= R300_TXO_MICRO_TILE;
715 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
716 tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
717
718 tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
719 tmp |= tile_flags;
720 ib[idx] = tmp;
721 }
722 track->textures[i].robj = reloc->robj;
723 track->tex_dirty = true;
724 break;
725 /* Tracked registers */
726 case 0x2084:
727 /* VAP_VF_CNTL */
728 track->vap_vf_cntl = idx_value;
729 break;
730 case 0x20B4:
731 /* VAP_VTX_SIZE */
732 track->vtx_size = idx_value & 0x7F;
733 break;
734 case 0x2134:
735 /* VAP_VF_MAX_VTX_INDX */
736 track->max_indx = idx_value & 0x00FFFFFFUL;
737 break;
738 case 0x2088:
739 /* VAP_ALT_NUM_VERTICES - only valid on r500 */
740 if (p->rdev->family < CHIP_RV515)
741 goto fail;
742 track->vap_alt_nverts = idx_value & 0xFFFFFF;
743 break;
744 case 0x43E4:
745 /* SC_SCISSOR1 */
746 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
747 if (p->rdev->family < CHIP_RV515) {
748 track->maxy -= 1440;
749 }
750 track->cb_dirty = true;
751 track->zb_dirty = true;
752 break;
753 case 0x4E00:
754 /* RB3D_CCTL */
755 if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */
756 p->rdev->cmask_filp != p->filp) {
757 DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n");
758 return -EINVAL;
759 }
760 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
761 track->cb_dirty = true;
762 break;
763 case 0x4E38:
764 case 0x4E3C:
765 case 0x4E40:
766 case 0x4E44:
767 /* RB3D_COLORPITCH0 */
768 /* RB3D_COLORPITCH1 */
769 /* RB3D_COLORPITCH2 */
770 /* RB3D_COLORPITCH3 */
771 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
772 r = r100_cs_packet_next_reloc(p, &reloc);
773 if (r) {
774 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
775 idx, reg);
776 r100_cs_dump_packet(p, pkt);
777 return r;
778 }
779
780 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
781 tile_flags |= R300_COLOR_TILE_ENABLE;
782 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
783 tile_flags |= R300_COLOR_MICROTILE_ENABLE;
784 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
785 tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
786
787 tmp = idx_value & ~(0x7 << 16);
788 tmp |= tile_flags;
789 ib[idx] = tmp;
790 }
791 i = (reg - 0x4E38) >> 2;
792 track->cb[i].pitch = idx_value & 0x3FFE;
793 switch (((idx_value >> 21) & 0xF)) {
794 case 9:
795 case 11:
796 case 12:
797 track->cb[i].cpp = 1;
798 break;
799 case 3:
800 case 4:
801 case 13:
802 case 15:
803 track->cb[i].cpp = 2;
804 break;
805 case 5:
806 if (p->rdev->family < CHIP_RV515) {
807 DRM_ERROR("Invalid color buffer format (%d)!\n",
808 ((idx_value >> 21) & 0xF));
809 return -EINVAL;
810 }
811 /* Pass through. */
812 case 6:
813 track->cb[i].cpp = 4;
814 break;
815 case 10:
816 track->cb[i].cpp = 8;
817 break;
818 case 7:
819 track->cb[i].cpp = 16;
820 break;
821 default:
822 DRM_ERROR("Invalid color buffer format (%d) !\n",
823 ((idx_value >> 21) & 0xF));
824 return -EINVAL;
825 }
826 track->cb_dirty = true;
827 break;
828 case 0x4F00:
829 /* ZB_CNTL */
830 if (idx_value & 2) {
831 track->z_enabled = true;
832 } else {
833 track->z_enabled = false;
834 }
835 track->zb_dirty = true;
836 break;
837 case 0x4F10:
838 /* ZB_FORMAT */
839 switch ((idx_value & 0xF)) {
840 case 0:
841 case 1:
842 track->zb.cpp = 2;
843 break;
844 case 2:
845 track->zb.cpp = 4;
846 break;
847 default:
848 DRM_ERROR("Invalid z buffer format (%d) !\n",
849 (idx_value & 0xF));
850 return -EINVAL;
851 }
852 track->zb_dirty = true;
853 break;
854 case 0x4F24:
855 /* ZB_DEPTHPITCH */
856 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
857 r = r100_cs_packet_next_reloc(p, &reloc);
858 if (r) {
859 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
860 idx, reg);
861 r100_cs_dump_packet(p, pkt);
862 return r;
863 }
864
865 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
866 tile_flags |= R300_DEPTHMACROTILE_ENABLE;
867 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
868 tile_flags |= R300_DEPTHMICROTILE_TILED;
869 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
870 tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
871
872 tmp = idx_value & ~(0x7 << 16);
873 tmp |= tile_flags;
874 ib[idx] = tmp;
875 }
876 track->zb.pitch = idx_value & 0x3FFC;
877 track->zb_dirty = true;
878 break;
879 case 0x4104:
880 /* TX_ENABLE */
881 for (i = 0; i < 16; i++) {
882 bool enabled;
883
884 enabled = !!(idx_value & (1 << i));
885 track->textures[i].enabled = enabled;
886 }
887 track->tex_dirty = true;
888 break;
889 case 0x44C0:
890 case 0x44C4:
891 case 0x44C8:
892 case 0x44CC:
893 case 0x44D0:
894 case 0x44D4:
895 case 0x44D8:
896 case 0x44DC:
897 case 0x44E0:
898 case 0x44E4:
899 case 0x44E8:
900 case 0x44EC:
901 case 0x44F0:
902 case 0x44F4:
903 case 0x44F8:
904 case 0x44FC:
905 /* TX_FORMAT1_[0-15] */
906 i = (reg - 0x44C0) >> 2;
907 tmp = (idx_value >> 25) & 0x3;
908 track->textures[i].tex_coord_type = tmp;
909 switch ((idx_value & 0x1F)) {
910 case R300_TX_FORMAT_X8:
911 case R300_TX_FORMAT_Y4X4:
912 case R300_TX_FORMAT_Z3Y3X2:
913 track->textures[i].cpp = 1;
914 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
915 break;
916 case R300_TX_FORMAT_X16:
917 case R300_TX_FORMAT_FL_I16:
918 case R300_TX_FORMAT_Y8X8:
919 case R300_TX_FORMAT_Z5Y6X5:
920 case R300_TX_FORMAT_Z6Y5X5:
921 case R300_TX_FORMAT_W4Z4Y4X4:
922 case R300_TX_FORMAT_W1Z5Y5X5:
923 case R300_TX_FORMAT_D3DMFT_CxV8U8:
924 case R300_TX_FORMAT_B8G8_B8G8:
925 case R300_TX_FORMAT_G8R8_G8B8:
926 track->textures[i].cpp = 2;
927 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
928 break;
929 case R300_TX_FORMAT_Y16X16:
930 case R300_TX_FORMAT_FL_I16A16:
931 case R300_TX_FORMAT_Z11Y11X10:
932 case R300_TX_FORMAT_Z10Y11X11:
933 case R300_TX_FORMAT_W8Z8Y8X8:
934 case R300_TX_FORMAT_W2Z10Y10X10:
935 case 0x17:
936 case R300_TX_FORMAT_FL_I32:
937 case 0x1e:
938 track->textures[i].cpp = 4;
939 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
940 break;
941 case R300_TX_FORMAT_W16Z16Y16X16:
942 case R300_TX_FORMAT_FL_R16G16B16A16:
943 case R300_TX_FORMAT_FL_I32A32:
944 track->textures[i].cpp = 8;
945 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
946 break;
947 case R300_TX_FORMAT_FL_R32G32B32A32:
948 track->textures[i].cpp = 16;
949 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
950 break;
951 case R300_TX_FORMAT_DXT1:
952 track->textures[i].cpp = 1;
953 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
954 break;
955 case R300_TX_FORMAT_ATI2N:
956 if (p->rdev->family < CHIP_R420) {
957 DRM_ERROR("Invalid texture format %u\n",
958 (idx_value & 0x1F));
959 return -EINVAL;
960 }
961 /* The same rules apply as for DXT3/5. */
962 /* Pass through. */
963 case R300_TX_FORMAT_DXT3:
964 case R300_TX_FORMAT_DXT5:
965 track->textures[i].cpp = 1;
966 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
967 break;
968 default:
969 DRM_ERROR("Invalid texture format %u\n",
970 (idx_value & 0x1F));
971 return -EINVAL;
972 }
973 track->tex_dirty = true;
974 break;
975 case 0x4400:
976 case 0x4404:
977 case 0x4408:
978 case 0x440C:
979 case 0x4410:
980 case 0x4414:
981 case 0x4418:
982 case 0x441C:
983 case 0x4420:
984 case 0x4424:
985 case 0x4428:
986 case 0x442C:
987 case 0x4430:
988 case 0x4434:
989 case 0x4438:
990 case 0x443C:
991 /* TX_FILTER0_[0-15] */
992 i = (reg - 0x4400) >> 2;
993 tmp = idx_value & 0x7;
994 if (tmp == 2 || tmp == 4 || tmp == 6) {
995 track->textures[i].roundup_w = false;
996 }
997 tmp = (idx_value >> 3) & 0x7;
998 if (tmp == 2 || tmp == 4 || tmp == 6) {
999 track->textures[i].roundup_h = false;
1000 }
1001 track->tex_dirty = true;
1002 break;
1003 case 0x4500:
1004 case 0x4504:
1005 case 0x4508:
1006 case 0x450C:
1007 case 0x4510:
1008 case 0x4514:
1009 case 0x4518:
1010 case 0x451C:
1011 case 0x4520:
1012 case 0x4524:
1013 case 0x4528:
1014 case 0x452C:
1015 case 0x4530:
1016 case 0x4534:
1017 case 0x4538:
1018 case 0x453C:
1019 /* TX_FORMAT2_[0-15] */
1020 i = (reg - 0x4500) >> 2;
1021 tmp = idx_value & 0x3FFF;
1022 track->textures[i].pitch = tmp + 1;
1023 if (p->rdev->family >= CHIP_RV515) {
1024 tmp = ((idx_value >> 15) & 1) << 11;
1025 track->textures[i].width_11 = tmp;
1026 tmp = ((idx_value >> 16) & 1) << 11;
1027 track->textures[i].height_11 = tmp;
1028
1029 /* ATI1N */
1030 if (idx_value & (1 << 14)) {
1031 /* The same rules apply as for DXT1. */
1032 track->textures[i].compress_format =
1033 R100_TRACK_COMP_DXT1;
1034 }
1035 } else if (idx_value & (1 << 14)) {
1036 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
1037 return -EINVAL;
1038 }
1039 track->tex_dirty = true;
1040 break;
1041 case 0x4480:
1042 case 0x4484:
1043 case 0x4488:
1044 case 0x448C:
1045 case 0x4490:
1046 case 0x4494:
1047 case 0x4498:
1048 case 0x449C:
1049 case 0x44A0:
1050 case 0x44A4:
1051 case 0x44A8:
1052 case 0x44AC:
1053 case 0x44B0:
1054 case 0x44B4:
1055 case 0x44B8:
1056 case 0x44BC:
1057 /* TX_FORMAT0_[0-15] */
1058 i = (reg - 0x4480) >> 2;
1059 tmp = idx_value & 0x7FF;
1060 track->textures[i].width = tmp + 1;
1061 tmp = (idx_value >> 11) & 0x7FF;
1062 track->textures[i].height = tmp + 1;
1063 tmp = (idx_value >> 26) & 0xF;
1064 track->textures[i].num_levels = tmp;
1065 tmp = idx_value & (1 << 31);
1066 track->textures[i].use_pitch = !!tmp;
1067 tmp = (idx_value >> 22) & 0xF;
1068 track->textures[i].txdepth = tmp;
1069 track->tex_dirty = true;
1070 break;
1071 case R300_ZB_ZPASS_ADDR:
1072 r = r100_cs_packet_next_reloc(p, &reloc);
1073 if (r) {
1074 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1075 idx, reg);
1076 r100_cs_dump_packet(p, pkt);
1077 return r;
1078 }
1079 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1080 break;
1081 case 0x4e0c:
1082 /* RB3D_COLOR_CHANNEL_MASK */
1083 track->color_channel_mask = idx_value;
1084 track->cb_dirty = true;
1085 break;
1086 case 0x43a4:
1087 /* SC_HYPERZ_EN */
1088 /* r300c emits this register - we need to disable hyperz for it
1089 * without complaining */
1090 if (p->rdev->hyperz_filp != p->filp) {
1091 if (idx_value & 0x1)
1092 ib[idx] = idx_value & ~1;
1093 }
1094 break;
1095 case 0x4f1c:
1096 /* ZB_BW_CNTL */
1097 track->zb_cb_clear = !!(idx_value & (1 << 5));
1098 track->cb_dirty = true;
1099 track->zb_dirty = true;
1100 if (p->rdev->hyperz_filp != p->filp) {
1101 if (idx_value & (R300_HIZ_ENABLE |
1102 R300_RD_COMP_ENABLE |
1103 R300_WR_COMP_ENABLE |
1104 R300_FAST_FILL_ENABLE))
1105 goto fail;
1106 }
1107 break;
1108 case 0x4e04:
1109 /* RB3D_BLENDCNTL */
1110 track->blend_read_enable = !!(idx_value & (1 << 2));
1111 track->cb_dirty = true;
1112 break;
1113 case R300_RB3D_AARESOLVE_OFFSET:
1114 r = r100_cs_packet_next_reloc(p, &reloc);
1115 if (r) {
1116 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1117 idx, reg);
1118 r100_cs_dump_packet(p, pkt);
1119 return r;
1120 }
1121 track->aa.robj = reloc->robj;
1122 track->aa.offset = idx_value;
1123 track->aa_dirty = true;
1124 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1125 break;
1126 case R300_RB3D_AARESOLVE_PITCH:
1127 track->aa.pitch = idx_value & 0x3FFE;
1128 track->aa_dirty = true;
1129 break;
1130 case R300_RB3D_AARESOLVE_CTL:
1131 track->aaresolve = idx_value & 0x1;
1132 track->aa_dirty = true;
1133 break;
1134 case 0x4f30: /* ZB_MASK_OFFSET */
1135 case 0x4f34: /* ZB_ZMASK_PITCH */
1136 case 0x4f44: /* ZB_HIZ_OFFSET */
1137 case 0x4f54: /* ZB_HIZ_PITCH */
1138 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1139 goto fail;
1140 break;
1141 case 0x4028:
1142 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1143 goto fail;
1144 /* GB_Z_PEQ_CONFIG */
1145 if (p->rdev->family >= CHIP_RV350)
1146 break;
1147 goto fail;
1148 break;
1149 case 0x4be8:
1150 /* valid register only on RV530 */
1151 if (p->rdev->family == CHIP_RV530)
1152 break;
1153 /* fallthrough do not move */
1154 default:
1155 goto fail;
1156 }
1157 return 0;
1158 fail:
1159 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n",
1160 reg, idx, idx_value);
1161 return -EINVAL;
1162 }
1163
1164 static int r300_packet3_check(struct radeon_cs_parser *p,
1165 struct radeon_cs_packet *pkt)
1166 {
1167 struct radeon_cs_reloc *reloc;
1168 struct r100_cs_track *track;
1169 volatile uint32_t *ib;
1170 unsigned idx;
1171 int r;
1172
1173 ib = p->ib->ptr;
1174 idx = pkt->idx + 1;
1175 track = (struct r100_cs_track *)p->track;
1176 switch(pkt->opcode) {
1177 case PACKET3_3D_LOAD_VBPNTR:
1178 r = r100_packet3_load_vbpntr(p, pkt, idx);
1179 if (r)
1180 return r;
1181 break;
1182 case PACKET3_INDX_BUFFER:
1183 r = r100_cs_packet_next_reloc(p, &reloc);
1184 if (r) {
1185 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1186 r100_cs_dump_packet(p, pkt);
1187 return r;
1188 }
1189 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1190 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1191 if (r) {
1192 return r;
1193 }
1194 break;
1195 /* Draw packet */
1196 case PACKET3_3D_DRAW_IMMD:
1197 /* Number of dwords is vtx_size * (num_vertices - 1)
1198 * PRIM_WALK must be equal to 3 vertex data in embedded
1199 * in cmd stream */
1200 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1201 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1202 return -EINVAL;
1203 }
1204 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1205 track->immd_dwords = pkt->count - 1;
1206 r = r100_cs_track_check(p->rdev, track);
1207 if (r) {
1208 return r;
1209 }
1210 break;
1211 case PACKET3_3D_DRAW_IMMD_2:
1212 /* Number of dwords is vtx_size * (num_vertices - 1)
1213 * PRIM_WALK must be equal to 3 vertex data in embedded
1214 * in cmd stream */
1215 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1216 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1217 return -EINVAL;
1218 }
1219 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1220 track->immd_dwords = pkt->count;
1221 r = r100_cs_track_check(p->rdev, track);
1222 if (r) {
1223 return r;
1224 }
1225 break;
1226 case PACKET3_3D_DRAW_VBUF:
1227 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1228 r = r100_cs_track_check(p->rdev, track);
1229 if (r) {
1230 return r;
1231 }
1232 break;
1233 case PACKET3_3D_DRAW_VBUF_2:
1234 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1235 r = r100_cs_track_check(p->rdev, track);
1236 if (r) {
1237 return r;
1238 }
1239 break;
1240 case PACKET3_3D_DRAW_INDX:
1241 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1242 r = r100_cs_track_check(p->rdev, track);
1243 if (r) {
1244 return r;
1245 }
1246 break;
1247 case PACKET3_3D_DRAW_INDX_2:
1248 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1249 r = r100_cs_track_check(p->rdev, track);
1250 if (r) {
1251 return r;
1252 }
1253 break;
1254 case PACKET3_3D_CLEAR_HIZ:
1255 case PACKET3_3D_CLEAR_ZMASK:
1256 if (p->rdev->hyperz_filp != p->filp)
1257 return -EINVAL;
1258 break;
1259 case PACKET3_3D_CLEAR_CMASK:
1260 if (p->rdev->cmask_filp != p->filp)
1261 return -EINVAL;
1262 break;
1263 case PACKET3_NOP:
1264 break;
1265 default:
1266 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1267 return -EINVAL;
1268 }
1269 return 0;
1270 }
1271
1272 int r300_cs_parse(struct radeon_cs_parser *p)
1273 {
1274 struct radeon_cs_packet pkt;
1275 struct r100_cs_track *track;
1276 int r;
1277
1278 track = kzalloc(sizeof(*track), GFP_KERNEL);
1279 if (track == NULL)
1280 return -ENOMEM;
1281 r100_cs_track_clear(p->rdev, track);
1282 p->track = track;
1283 do {
1284 r = r100_cs_packet_parse(p, &pkt, p->idx);
1285 if (r) {
1286 return r;
1287 }
1288 p->idx += pkt.count + 2;
1289 switch (pkt.type) {
1290 case PACKET_TYPE0:
1291 r = r100_cs_parse_packet0(p, &pkt,
1292 p->rdev->config.r300.reg_safe_bm,
1293 p->rdev->config.r300.reg_safe_bm_size,
1294 &r300_packet0_check);
1295 break;
1296 case PACKET_TYPE2:
1297 break;
1298 case PACKET_TYPE3:
1299 r = r300_packet3_check(p, &pkt);
1300 break;
1301 default:
1302 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1303 return -EINVAL;
1304 }
1305 if (r) {
1306 return r;
1307 }
1308 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1309 return 0;
1310 }
1311
1312 void r300_set_reg_safe(struct radeon_device *rdev)
1313 {
1314 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1315 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1316 }
1317
1318 void r300_mc_program(struct radeon_device *rdev)
1319 {
1320 struct r100_mc_save save;
1321 int r;
1322
1323 r = r100_debugfs_mc_info_init(rdev);
1324 if (r) {
1325 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1326 }
1327
1328 /* Stops all mc clients */
1329 r100_mc_stop(rdev, &save);
1330 if (rdev->flags & RADEON_IS_AGP) {
1331 WREG32(R_00014C_MC_AGP_LOCATION,
1332 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1333 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1334 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1335 WREG32(R_00015C_AGP_BASE_2,
1336 upper_32_bits(rdev->mc.agp_base) & 0xff);
1337 } else {
1338 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1339 WREG32(R_000170_AGP_BASE, 0);
1340 WREG32(R_00015C_AGP_BASE_2, 0);
1341 }
1342 /* Wait for mc idle */
1343 if (r300_mc_wait_for_idle(rdev))
1344 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1345 /* Program MC, should be a 32bits limited address space */
1346 WREG32(R_000148_MC_FB_LOCATION,
1347 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1348 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1349 r100_mc_resume(rdev, &save);
1350 }
1351
1352 void r300_clock_startup(struct radeon_device *rdev)
1353 {
1354 u32 tmp;
1355
1356 if (radeon_dynclks != -1 && radeon_dynclks)
1357 radeon_legacy_set_clock_gating(rdev, 1);
1358 /* We need to force on some of the block */
1359 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1360 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1361 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1362 tmp |= S_00000D_FORCE_VAP(1);
1363 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1364 }
1365
1366 static int r300_startup(struct radeon_device *rdev)
1367 {
1368 int r;
1369
1370 /* set common regs */
1371 r100_set_common_regs(rdev);
1372 /* program mc */
1373 r300_mc_program(rdev);
1374 /* Resume clock */
1375 r300_clock_startup(rdev);
1376 /* Initialize GPU configuration (# pipes, ...) */
1377 r300_gpu_init(rdev);
1378 /* Initialize GART (initialize after TTM so we can allocate
1379 * memory through TTM but finalize after TTM) */
1380 if (rdev->flags & RADEON_IS_PCIE) {
1381 r = rv370_pcie_gart_enable(rdev);
1382 if (r)
1383 return r;
1384 }
1385
1386 if (rdev->family == CHIP_R300 ||
1387 rdev->family == CHIP_R350 ||
1388 rdev->family == CHIP_RV350)
1389 r100_enable_bm(rdev);
1390
1391 if (rdev->flags & RADEON_IS_PCI) {
1392 r = r100_pci_gart_enable(rdev);
1393 if (r)
1394 return r;
1395 }
1396
1397 /* allocate wb buffer */
1398 r = radeon_wb_init(rdev);
1399 if (r)
1400 return r;
1401
1402 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1403 if (r) {
1404 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1405 return r;
1406 }
1407
1408 /* Enable IRQ */
1409 r100_irq_set(rdev);
1410 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1411 /* 1M ring buffer */
1412 r = r100_cp_init(rdev, 1024 * 1024);
1413 if (r) {
1414 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1415 return r;
1416 }
1417
1418 r = radeon_ib_pool_start(rdev);
1419 if (r)
1420 return r;
1421
1422 r = r100_ib_test(rdev);
1423 if (r) {
1424 dev_err(rdev->dev, "failed testing IB (%d).\n", r);
1425 rdev->accel_working = false;
1426 return r;
1427 }
1428
1429 return 0;
1430 }
1431
1432 int r300_resume(struct radeon_device *rdev)
1433 {
1434 int r;
1435
1436 /* Make sur GART are not working */
1437 if (rdev->flags & RADEON_IS_PCIE)
1438 rv370_pcie_gart_disable(rdev);
1439 if (rdev->flags & RADEON_IS_PCI)
1440 r100_pci_gart_disable(rdev);
1441 /* Resume clock before doing reset */
1442 r300_clock_startup(rdev);
1443 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1444 if (radeon_asic_reset(rdev)) {
1445 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1446 RREG32(R_000E40_RBBM_STATUS),
1447 RREG32(R_0007C0_CP_STAT));
1448 }
1449 /* post */
1450 radeon_combios_asic_init(rdev->ddev);
1451 /* Resume clock after posting */
1452 r300_clock_startup(rdev);
1453 /* Initialize surface registers */
1454 radeon_surface_init(rdev);
1455
1456 rdev->accel_working = true;
1457 r = r300_startup(rdev);
1458 if (r) {
1459 rdev->accel_working = false;
1460 }
1461 return r;
1462 }
1463
1464 int r300_suspend(struct radeon_device *rdev)
1465 {
1466 radeon_ib_pool_suspend(rdev);
1467 r100_cp_disable(rdev);
1468 radeon_wb_disable(rdev);
1469 r100_irq_disable(rdev);
1470 if (rdev->flags & RADEON_IS_PCIE)
1471 rv370_pcie_gart_disable(rdev);
1472 if (rdev->flags & RADEON_IS_PCI)
1473 r100_pci_gart_disable(rdev);
1474 return 0;
1475 }
1476
1477 void r300_fini(struct radeon_device *rdev)
1478 {
1479 r100_cp_fini(rdev);
1480 radeon_wb_fini(rdev);
1481 r100_ib_fini(rdev);
1482 radeon_gem_fini(rdev);
1483 if (rdev->flags & RADEON_IS_PCIE)
1484 rv370_pcie_gart_fini(rdev);
1485 if (rdev->flags & RADEON_IS_PCI)
1486 r100_pci_gart_fini(rdev);
1487 radeon_agp_fini(rdev);
1488 radeon_irq_kms_fini(rdev);
1489 radeon_fence_driver_fini(rdev);
1490 radeon_bo_fini(rdev);
1491 radeon_atombios_fini(rdev);
1492 kfree(rdev->bios);
1493 rdev->bios = NULL;
1494 }
1495
1496 int r300_init(struct radeon_device *rdev)
1497 {
1498 int r;
1499
1500 /* Disable VGA */
1501 r100_vga_render_disable(rdev);
1502 /* Initialize scratch registers */
1503 radeon_scratch_init(rdev);
1504 /* Initialize surface registers */
1505 radeon_surface_init(rdev);
1506 /* TODO: disable VGA need to use VGA request */
1507 /* restore some register to sane defaults */
1508 r100_restore_sanity(rdev);
1509 /* BIOS*/
1510 if (!radeon_get_bios(rdev)) {
1511 if (ASIC_IS_AVIVO(rdev))
1512 return -EINVAL;
1513 }
1514 if (rdev->is_atom_bios) {
1515 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1516 return -EINVAL;
1517 } else {
1518 r = radeon_combios_init(rdev);
1519 if (r)
1520 return r;
1521 }
1522 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1523 if (radeon_asic_reset(rdev)) {
1524 dev_warn(rdev->dev,
1525 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1526 RREG32(R_000E40_RBBM_STATUS),
1527 RREG32(R_0007C0_CP_STAT));
1528 }
1529 /* check if cards are posted or not */
1530 if (radeon_boot_test_post_card(rdev) == false)
1531 return -EINVAL;
1532 /* Set asic errata */
1533 r300_errata(rdev);
1534 /* Initialize clocks */
1535 radeon_get_clock_info(rdev->ddev);
1536 /* initialize AGP */
1537 if (rdev->flags & RADEON_IS_AGP) {
1538 r = radeon_agp_init(rdev);
1539 if (r) {
1540 radeon_agp_disable(rdev);
1541 }
1542 }
1543 /* initialize memory controller */
1544 r300_mc_init(rdev);
1545 /* Fence driver */
1546 r = radeon_fence_driver_init(rdev);
1547 if (r)
1548 return r;
1549 r = radeon_irq_kms_init(rdev);
1550 if (r)
1551 return r;
1552 /* Memory manager */
1553 r = radeon_bo_init(rdev);
1554 if (r)
1555 return r;
1556 if (rdev->flags & RADEON_IS_PCIE) {
1557 r = rv370_pcie_gart_init(rdev);
1558 if (r)
1559 return r;
1560 }
1561 if (rdev->flags & RADEON_IS_PCI) {
1562 r = r100_pci_gart_init(rdev);
1563 if (r)
1564 return r;
1565 }
1566 r300_set_reg_safe(rdev);
1567
1568 r = radeon_ib_pool_init(rdev);
1569 rdev->accel_working = true;
1570 if (r) {
1571 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1572 rdev->accel_working = false;
1573 }
1574
1575 r = r300_startup(rdev);
1576 if (r) {
1577 /* Somethings want wront with the accel init stop accel */
1578 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1579 r100_cp_fini(rdev);
1580 radeon_wb_fini(rdev);
1581 r100_ib_fini(rdev);
1582 radeon_irq_kms_fini(rdev);
1583 if (rdev->flags & RADEON_IS_PCIE)
1584 rv370_pcie_gart_fini(rdev);
1585 if (rdev->flags & RADEON_IS_PCI)
1586 r100_pci_gart_fini(rdev);
1587 radeon_agp_fini(rdev);
1588 rdev->accel_working = false;
1589 }
1590 return 0;
1591 }