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percpu, x86: don't use PMD_SIZE as embedded atom_size on 32bit
[zen-stable.git] / drivers / gpu / drm / radeon / radeon_cp.c
blob72ae8266b8e9d88edaa7d8369e7512cbde13c734
1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2 /*
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2007 Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 */
31
32 #include <linux/module.h>
33
34 #include "drmP.h"
35 #include "drm.h"
36 #include "drm_sarea.h"
37 #include "radeon_drm.h"
38 #include "radeon_drv.h"
39 #include "r300_reg.h"
40
41 #define RADEON_FIFO_DEBUG 0
42
43 /* Firmware Names */
44 #define FIRMWARE_R100 "radeon/R100_cp.bin"
45 #define FIRMWARE_R200 "radeon/R200_cp.bin"
46 #define FIRMWARE_R300 "radeon/R300_cp.bin"
47 #define FIRMWARE_R420 "radeon/R420_cp.bin"
48 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
49 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
50 #define FIRMWARE_R520 "radeon/R520_cp.bin"
51
52 MODULE_FIRMWARE(FIRMWARE_R100);
53 MODULE_FIRMWARE(FIRMWARE_R200);
54 MODULE_FIRMWARE(FIRMWARE_R300);
55 MODULE_FIRMWARE(FIRMWARE_R420);
56 MODULE_FIRMWARE(FIRMWARE_RS690);
57 MODULE_FIRMWARE(FIRMWARE_RS600);
58 MODULE_FIRMWARE(FIRMWARE_R520);
59
60 static int radeon_do_cleanup_cp(struct drm_device * dev);
61 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
62
63 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
64 {
65 u32 val;
66
67 if (dev_priv->flags & RADEON_IS_AGP) {
68 val = DRM_READ32(dev_priv->ring_rptr, off);
69 } else {
70 val = *(((volatile u32 *)
71 dev_priv->ring_rptr->handle) +
72 (off / sizeof(u32)));
73 val = le32_to_cpu(val);
74 }
75 return val;
76 }
77
78 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
79 {
80 if (dev_priv->writeback_works)
81 return radeon_read_ring_rptr(dev_priv, 0);
82 else {
83 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
84 return RADEON_READ(R600_CP_RB_RPTR);
85 else
86 return RADEON_READ(RADEON_CP_RB_RPTR);
87 }
88 }
89
90 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
91 {
92 if (dev_priv->flags & RADEON_IS_AGP)
93 DRM_WRITE32(dev_priv->ring_rptr, off, val);
94 else
95 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
96 (off / sizeof(u32))) = cpu_to_le32(val);
97 }
98
99 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
100 {
101 radeon_write_ring_rptr(dev_priv, 0, val);
102 }
103
104 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
105 {
106 if (dev_priv->writeback_works) {
107 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
108 return radeon_read_ring_rptr(dev_priv,
109 R600_SCRATCHOFF(index));
110 else
111 return radeon_read_ring_rptr(dev_priv,
112 RADEON_SCRATCHOFF(index));
113 } else {
114 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
115 return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
116 else
117 return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
118 }
119 }
120
121 u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr)
122 {
123 u32 ret;
124
125 if (addr < 0x10000)
126 ret = DRM_READ32(dev_priv->mmio, addr);
127 else {
128 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr);
129 ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA);
130 }
131
132 return ret;
133 }
134
135 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
136 {
137 u32 ret;
138 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
139 ret = RADEON_READ(R520_MC_IND_DATA);
140 RADEON_WRITE(R520_MC_IND_INDEX, 0);
141 return ret;
142 }
143
144 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
145 {
146 u32 ret;
147 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
148 ret = RADEON_READ(RS480_NB_MC_DATA);
149 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
150 return ret;
151 }
152
153 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
154 {
155 u32 ret;
156 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
157 ret = RADEON_READ(RS690_MC_DATA);
158 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
159 return ret;
160 }
161
162 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
163 {
164 u32 ret;
165 RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
166 RS600_MC_IND_CITF_ARB0));
167 ret = RADEON_READ(RS600_MC_DATA);
168 return ret;
169 }
170
171 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
172 {
173 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
174 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
175 return RS690_READ_MCIND(dev_priv, addr);
176 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
177 return RS600_READ_MCIND(dev_priv, addr);
178 else
179 return RS480_READ_MCIND(dev_priv, addr);
180 }
181
182 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
183 {
184
185 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
186 return RADEON_READ(R700_MC_VM_FB_LOCATION);
187 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
188 return RADEON_READ(R600_MC_VM_FB_LOCATION);
189 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
190 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
191 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
192 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
193 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
194 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
195 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
196 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
197 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
198 else
199 return RADEON_READ(RADEON_MC_FB_LOCATION);
200 }
201
202 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
203 {
204 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
205 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
206 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
207 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
208 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
209 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
210 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
211 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
212 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
213 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
214 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
215 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
216 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
217 else
218 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
219 }
220
221 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
222 {
223 /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
224 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
225 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
226 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
227 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
228 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
229 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
230 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
231 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
232 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
233 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
234 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
235 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
236 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
237 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
238 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
239 else
240 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
241 }
242
243 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
244 {
245 u32 agp_base_hi = upper_32_bits(agp_base);
246 u32 agp_base_lo = agp_base & 0xffffffff;
247 u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
248
249 /* R6xx/R7xx must be aligned to a 4MB boundary */
250 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
251 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
252 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
253 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
254 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
255 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
256 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
257 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
258 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
259 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
260 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
261 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
262 RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
263 RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
264 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
265 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
266 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
267 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
268 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
269 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
270 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
271 } else {
272 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
273 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
274 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
275 }
276 }
277
278 void radeon_enable_bm(struct drm_radeon_private *dev_priv)
279 {
280 u32 tmp;
281 /* Turn on bus mastering */
282 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
283 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
284 /* rs600/rs690/rs740 */
285 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
286 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
287 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
288 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
289 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
290 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
291 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
292 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
293 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
294 } /* PCIE cards appears to not need this */
295 }
296
297 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
298 {
299 drm_radeon_private_t *dev_priv = dev->dev_private;
300
301 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
302 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
303 }
304
305 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
306 {
307 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
308 return RADEON_READ(RADEON_PCIE_DATA);
309 }
310
311 #if RADEON_FIFO_DEBUG
312 static void radeon_status(drm_radeon_private_t * dev_priv)
313 {
314 printk("%s:\n", __func__);
315 printk("RBBM_STATUS = 0x%08x\n",
316 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
317 printk("CP_RB_RTPR = 0x%08x\n",
318 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
319 printk("CP_RB_WTPR = 0x%08x\n",
320 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
321 printk("AIC_CNTL = 0x%08x\n",
322 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
323 printk("AIC_STAT = 0x%08x\n",
324 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
325 printk("AIC_PT_BASE = 0x%08x\n",
326 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
327 printk("TLB_ADDR = 0x%08x\n",
328 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
329 printk("TLB_DATA = 0x%08x\n",
330 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
331 }
332 #endif
333
334 /* ================================================================
335 * Engine, FIFO control
336 */
337
338 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
339 {
340 u32 tmp;
341 int i;
342
343 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
344
345 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
346 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
347 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
348 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
349
350 for (i = 0; i < dev_priv->usec_timeout; i++) {
351 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
352 & RADEON_RB3D_DC_BUSY)) {
353 return 0;
354 }
355 DRM_UDELAY(1);
356 }
357 } else {
358 /* don't flush or purge cache here or lockup */
359 return 0;
360 }
361
362 #if RADEON_FIFO_DEBUG
363 DRM_ERROR("failed!\n");
364 radeon_status(dev_priv);
365 #endif
366 return -EBUSY;
367 }
368
369 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
370 {
371 int i;
372
373 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
374
375 for (i = 0; i < dev_priv->usec_timeout; i++) {
376 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
377 & RADEON_RBBM_FIFOCNT_MASK);
378 if (slots >= entries)
379 return 0;
380 DRM_UDELAY(1);
381 }
382 DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
383 RADEON_READ(RADEON_RBBM_STATUS),
384 RADEON_READ(R300_VAP_CNTL_STATUS));
385
386 #if RADEON_FIFO_DEBUG
387 DRM_ERROR("failed!\n");
388 radeon_status(dev_priv);
389 #endif
390 return -EBUSY;
391 }
392
393 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
394 {
395 int i, ret;
396
397 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
398
399 ret = radeon_do_wait_for_fifo(dev_priv, 64);
400 if (ret)
401 return ret;
402
403 for (i = 0; i < dev_priv->usec_timeout; i++) {
404 if (!(RADEON_READ(RADEON_RBBM_STATUS)
405 & RADEON_RBBM_ACTIVE)) {
406 radeon_do_pixcache_flush(dev_priv);
407 return 0;
408 }
409 DRM_UDELAY(1);
410 }
411 DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
412 RADEON_READ(RADEON_RBBM_STATUS),
413 RADEON_READ(R300_VAP_CNTL_STATUS));
414
415 #if RADEON_FIFO_DEBUG
416 DRM_ERROR("failed!\n");
417 radeon_status(dev_priv);
418 #endif
419 return -EBUSY;
420 }
421
422 static void radeon_init_pipes(struct drm_device *dev)
423 {
424 drm_radeon_private_t *dev_priv = dev->dev_private;
425 uint32_t gb_tile_config, gb_pipe_sel = 0;
426
427 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
428 uint32_t z_pipe_sel = RADEON_READ(RV530_GB_PIPE_SELECT2);
429 if ((z_pipe_sel & 3) == 3)
430 dev_priv->num_z_pipes = 2;
431 else
432 dev_priv->num_z_pipes = 1;
433 } else
434 dev_priv->num_z_pipes = 1;
435
436 /* RS4xx/RS6xx/R4xx/R5xx */
437 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
438 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
439 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
440 /* SE cards have 1 pipe */
441 if ((dev->pdev->device == 0x5e4c) ||
442 (dev->pdev->device == 0x5e4f))
443 dev_priv->num_gb_pipes = 1;
444 } else {
445 /* R3xx */
446 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300 &&
447 dev->pdev->device != 0x4144) ||
448 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350 &&
449 dev->pdev->device != 0x4148)) {
450 dev_priv->num_gb_pipes = 2;
451 } else {
452 /* RV3xx/R300 AD/R350 AH */
453 dev_priv->num_gb_pipes = 1;
454 }
455 }
456 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
457
458 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
459
460 switch (dev_priv->num_gb_pipes) {
461 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
462 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
463 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
464 default:
465 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
466 }
467
468 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
469 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
470 RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
471 }
472 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
473 radeon_do_wait_for_idle(dev_priv);
474 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
475 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
476 R300_DC_AUTOFLUSH_ENABLE |
477 R300_DC_DC_DISABLE_IGNORE_PE));
478
479
480 }
481
482 /* ================================================================
483 * CP control, initialization
484 */
485
486 /* Load the microcode for the CP */
487 static int radeon_cp_init_microcode(drm_radeon_private_t *dev_priv)
488 {
489 struct platform_device *pdev;
490 const char *fw_name = NULL;
491 int err;
492
493 DRM_DEBUG("\n");
494
495 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
496 err = IS_ERR(pdev);
497 if (err) {
498 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
499 return -EINVAL;
500 }
501
502 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
503 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
504 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
505 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
506 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
507 DRM_INFO("Loading R100 Microcode\n");
508 fw_name = FIRMWARE_R100;
509 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
510 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
511 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
512 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
513 DRM_INFO("Loading R200 Microcode\n");
514 fw_name = FIRMWARE_R200;
515 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
516 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
517 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
518 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
519 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
520 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
521 DRM_INFO("Loading R300 Microcode\n");
522 fw_name = FIRMWARE_R300;
523 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
524 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
525 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
526 DRM_INFO("Loading R400 Microcode\n");
527 fw_name = FIRMWARE_R420;
528 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
529 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
530 DRM_INFO("Loading RS690/RS740 Microcode\n");
531 fw_name = FIRMWARE_RS690;
532 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
533 DRM_INFO("Loading RS600 Microcode\n");
534 fw_name = FIRMWARE_RS600;
535 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
536 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
537 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
538 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
539 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
540 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
541 DRM_INFO("Loading R500 Microcode\n");
542 fw_name = FIRMWARE_R520;
543 }
544
545 err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev);
546 platform_device_unregister(pdev);
547 if (err) {
548 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
549 fw_name);
550 } else if (dev_priv->me_fw->size % 8) {
551 printk(KERN_ERR
552 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
553 dev_priv->me_fw->size, fw_name);
554 err = -EINVAL;
555 release_firmware(dev_priv->me_fw);
556 dev_priv->me_fw = NULL;
557 }
558 return err;
559 }
560
561 static void radeon_cp_load_microcode(drm_radeon_private_t *dev_priv)
562 {
563 const __be32 *fw_data;
564 int i, size;
565
566 radeon_do_wait_for_idle(dev_priv);
567
568 if (dev_priv->me_fw) {
569 size = dev_priv->me_fw->size / 4;
570 fw_data = (const __be32 *)&dev_priv->me_fw->data[0];
571 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
572 for (i = 0; i < size; i += 2) {
573 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
574 be32_to_cpup(&fw_data[i]));
575 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
576 be32_to_cpup(&fw_data[i + 1]));
577 }
578 }
579 }
580
581 /* Flush any pending commands to the CP. This should only be used just
582 * prior to a wait for idle, as it informs the engine that the command
583 * stream is ending.
584 */
585 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
586 {
587 DRM_DEBUG("\n");
588 #if 0
589 u32 tmp;
590
591 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
592 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
593 #endif
594 }
595
596 /* Wait for the CP to go idle.
597 */
598 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
599 {
600 RING_LOCALS;
601 DRM_DEBUG("\n");
602
603 BEGIN_RING(6);
604
605 RADEON_PURGE_CACHE();
606 RADEON_PURGE_ZCACHE();
607 RADEON_WAIT_UNTIL_IDLE();
608
609 ADVANCE_RING();
610 COMMIT_RING();
611
612 return radeon_do_wait_for_idle(dev_priv);
613 }
614
615 /* Start the Command Processor.
616 */
617 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
618 {
619 RING_LOCALS;
620 DRM_DEBUG("\n");
621
622 radeon_do_wait_for_idle(dev_priv);
623
624 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
625
626 dev_priv->cp_running = 1;
627
628 /* on r420, any DMA from CP to system memory while 2D is active
629 * can cause a hang. workaround is to queue a CP RESYNC token
630 */
631 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
632 BEGIN_RING(3);
633 OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1));
634 OUT_RING(5); /* scratch reg 5 */
635 OUT_RING(0xdeadbeef);
636 ADVANCE_RING();
637 COMMIT_RING();
638 }
639
640 BEGIN_RING(8);
641 /* isync can only be written through cp on r5xx write it here */
642 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
643 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
644 RADEON_ISYNC_ANY3D_IDLE2D |
645 RADEON_ISYNC_WAIT_IDLEGUI |
646 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
647 RADEON_PURGE_CACHE();
648 RADEON_PURGE_ZCACHE();
649 RADEON_WAIT_UNTIL_IDLE();
650 ADVANCE_RING();
651 COMMIT_RING();
652
653 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
654 }
655
656 /* Reset the Command Processor. This will not flush any pending
657 * commands, so you must wait for the CP command stream to complete
658 * before calling this routine.
659 */
660 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
661 {
662 u32 cur_read_ptr;
663 DRM_DEBUG("\n");
664
665 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
666 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
667 SET_RING_HEAD(dev_priv, cur_read_ptr);
668 dev_priv->ring.tail = cur_read_ptr;
669 }
670
671 /* Stop the Command Processor. This will not flush any pending
672 * commands, so you must flush the command stream and wait for the CP
673 * to go idle before calling this routine.
674 */
675 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
676 {
677 RING_LOCALS;
678 DRM_DEBUG("\n");
679
680 /* finish the pending CP_RESYNC token */
681 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
682 BEGIN_RING(2);
683 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
684 OUT_RING(R300_RB3D_DC_FINISH);
685 ADVANCE_RING();
686 COMMIT_RING();
687 radeon_do_wait_for_idle(dev_priv);
688 }
689
690 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
691
692 dev_priv->cp_running = 0;
693 }
694
695 /* Reset the engine. This will stop the CP if it is running.
696 */
697 static int radeon_do_engine_reset(struct drm_device * dev)
698 {
699 drm_radeon_private_t *dev_priv = dev->dev_private;
700 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
701 DRM_DEBUG("\n");
702
703 radeon_do_pixcache_flush(dev_priv);
704
705 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
706 /* may need something similar for newer chips */
707 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
708 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
709
710 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
711 RADEON_FORCEON_MCLKA |
712 RADEON_FORCEON_MCLKB |
713 RADEON_FORCEON_YCLKA |
714 RADEON_FORCEON_YCLKB |
715 RADEON_FORCEON_MC |
716 RADEON_FORCEON_AIC));
717 }
718
719 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
720
721 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
722 RADEON_SOFT_RESET_CP |
723 RADEON_SOFT_RESET_HI |
724 RADEON_SOFT_RESET_SE |
725 RADEON_SOFT_RESET_RE |
726 RADEON_SOFT_RESET_PP |
727 RADEON_SOFT_RESET_E2 |
728 RADEON_SOFT_RESET_RB));
729 RADEON_READ(RADEON_RBBM_SOFT_RESET);
730 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
731 ~(RADEON_SOFT_RESET_CP |
732 RADEON_SOFT_RESET_HI |
733 RADEON_SOFT_RESET_SE |
734 RADEON_SOFT_RESET_RE |
735 RADEON_SOFT_RESET_PP |
736 RADEON_SOFT_RESET_E2 |
737 RADEON_SOFT_RESET_RB)));
738 RADEON_READ(RADEON_RBBM_SOFT_RESET);
739
740 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
741 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
742 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
743 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
744 }
745
746 /* setup the raster pipes */
747 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
748 radeon_init_pipes(dev);
749
750 /* Reset the CP ring */
751 radeon_do_cp_reset(dev_priv);
752
753 /* The CP is no longer running after an engine reset */
754 dev_priv->cp_running = 0;
755
756 /* Reset any pending vertex, indirect buffers */
757 radeon_freelist_reset(dev);
758
759 return 0;
760 }
761
762 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
763 drm_radeon_private_t *dev_priv,
764 struct drm_file *file_priv)
765 {
766 struct drm_radeon_master_private *master_priv;
767 u32 ring_start, cur_read_ptr;
768
769 /* Initialize the memory controller. With new memory map, the fb location
770 * is not changed, it should have been properly initialized already. Part
771 * of the problem is that the code below is bogus, assuming the GART is
772 * always appended to the fb which is not necessarily the case
773 */
774 if (!dev_priv->new_memmap)
775 radeon_write_fb_location(dev_priv,
776 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
777 | (dev_priv->fb_location >> 16));
778
779 #if __OS_HAS_AGP
780 if (dev_priv->flags & RADEON_IS_AGP) {
781 radeon_write_agp_base(dev_priv, dev->agp->base);
782
783 radeon_write_agp_location(dev_priv,
784 (((dev_priv->gart_vm_start - 1 +
785 dev_priv->gart_size) & 0xffff0000) |
786 (dev_priv->gart_vm_start >> 16)));
787
788 ring_start = (dev_priv->cp_ring->offset
789 - dev->agp->base
790 + dev_priv->gart_vm_start);
791 } else
792 #endif
793 ring_start = (dev_priv->cp_ring->offset
794 - (unsigned long)dev->sg->virtual
795 + dev_priv->gart_vm_start);
796
797 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
798
799 /* Set the write pointer delay */
800 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
801
802 /* Initialize the ring buffer's read and write pointers */
803 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
804 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
805 SET_RING_HEAD(dev_priv, cur_read_ptr);
806 dev_priv->ring.tail = cur_read_ptr;
807
808 #if __OS_HAS_AGP
809 if (dev_priv->flags & RADEON_IS_AGP) {
810 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
811 dev_priv->ring_rptr->offset
812 - dev->agp->base + dev_priv->gart_vm_start);
813 } else
814 #endif
815 {
816 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
817 dev_priv->ring_rptr->offset
818 - ((unsigned long) dev->sg->virtual)
819 + dev_priv->gart_vm_start);
820 }
821
822 /* Set ring buffer size */
823 #ifdef __BIG_ENDIAN
824 RADEON_WRITE(RADEON_CP_RB_CNTL,
825 RADEON_BUF_SWAP_32BIT |
826 (dev_priv->ring.fetch_size_l2ow << 18) |
827 (dev_priv->ring.rptr_update_l2qw << 8) |
828 dev_priv->ring.size_l2qw);
829 #else
830 RADEON_WRITE(RADEON_CP_RB_CNTL,
831 (dev_priv->ring.fetch_size_l2ow << 18) |
832 (dev_priv->ring.rptr_update_l2qw << 8) |
833 dev_priv->ring.size_l2qw);
834 #endif
835
836
837 /* Initialize the scratch register pointer. This will cause
838 * the scratch register values to be written out to memory
839 * whenever they are updated.
840 *
841 * We simply put this behind the ring read pointer, this works
842 * with PCI GART as well as (whatever kind of) AGP GART
843 */
844 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
845 + RADEON_SCRATCH_REG_OFFSET);
846
847 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
848
849 radeon_enable_bm(dev_priv);
850
851 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
852 RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
853
854 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
855 RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
856
857 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
858 RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
859
860 /* reset sarea copies of these */
861 master_priv = file_priv->master->driver_priv;
862 if (master_priv->sarea_priv) {
863 master_priv->sarea_priv->last_frame = 0;
864 master_priv->sarea_priv->last_dispatch = 0;
865 master_priv->sarea_priv->last_clear = 0;
866 }
867
868 radeon_do_wait_for_idle(dev_priv);
869
870 /* Sync everything up */
871 RADEON_WRITE(RADEON_ISYNC_CNTL,
872 (RADEON_ISYNC_ANY2D_IDLE3D |
873 RADEON_ISYNC_ANY3D_IDLE2D |
874 RADEON_ISYNC_WAIT_IDLEGUI |
875 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
876
877 }
878
879 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
880 {
881 u32 tmp;
882
883 /* Start with assuming that writeback doesn't work */
884 dev_priv->writeback_works = 0;
885
886 /* Writeback doesn't seem to work everywhere, test it here and possibly
887 * enable it if it appears to work
888 */
889 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
890
891 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
892
893 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
894 u32 val;
895
896 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
897 if (val == 0xdeadbeef)
898 break;
899 DRM_UDELAY(1);
900 }
901
902 if (tmp < dev_priv->usec_timeout) {
903 dev_priv->writeback_works = 1;
904 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
905 } else {
906 dev_priv->writeback_works = 0;
907 DRM_INFO("writeback test failed\n");
908 }
909 if (radeon_no_wb == 1) {
910 dev_priv->writeback_works = 0;
911 DRM_INFO("writeback forced off\n");
912 }
913
914 if (!dev_priv->writeback_works) {
915 /* Disable writeback to avoid unnecessary bus master transfer */
916 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
917 RADEON_RB_NO_UPDATE);
918 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
919 }
920 }
921
922 /* Enable or disable IGP GART on the chip */
923 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
924 {
925 u32 temp;
926
927 if (on) {
928 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
929 dev_priv->gart_vm_start,
930 (long)dev_priv->gart_info.bus_addr,
931 dev_priv->gart_size);
932
933 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
934 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
935 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
936 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
937 RS690_BLOCK_GFX_D3_EN));
938 else
939 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
940
941 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
942 RS480_VA_SIZE_32MB));
943
944 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
945 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
946 RS480_TLB_ENABLE |
947 RS480_GTW_LAC_EN |
948 RS480_1LEVEL_GART));
949
950 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
951 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
952 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
953
954 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
955 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
956 RS480_REQ_TYPE_SNOOP_DIS));
957
958 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
959
960 dev_priv->gart_size = 32*1024*1024;
961 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
962 0xffff0000) | (dev_priv->gart_vm_start >> 16));
963
964 radeon_write_agp_location(dev_priv, temp);
965
966 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
967 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
968 RS480_VA_SIZE_32MB));
969
970 do {
971 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
972 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
973 break;
974 DRM_UDELAY(1);
975 } while (1);
976
977 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
978 RS480_GART_CACHE_INVALIDATE);
979
980 do {
981 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
982 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
983 break;
984 DRM_UDELAY(1);
985 } while (1);
986
987 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
988 } else {
989 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
990 }
991 }
992
993 /* Enable or disable IGP GART on the chip */
994 static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
995 {
996 u32 temp;
997 int i;
998
999 if (on) {
1000 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
1001 dev_priv->gart_vm_start,
1002 (long)dev_priv->gart_info.bus_addr,
1003 dev_priv->gart_size);
1004
1005 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
1006 RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
1007
1008 for (i = 0; i < 19; i++)
1009 IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
1010 (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
1011 RS600_SYSTEM_ACCESS_MODE_IN_SYS |
1012 RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
1013 RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
1014 RS600_ENABLE_FRAGMENT_PROCESSING |
1015 RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
1016
1017 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
1018 RS600_PAGE_TABLE_TYPE_FLAT));
1019
1020 /* disable all other contexts */
1021 for (i = 1; i < 8; i++)
1022 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
1023
1024 /* setup the page table aperture */
1025 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
1026 dev_priv->gart_info.bus_addr);
1027 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
1028 dev_priv->gart_vm_start);
1029 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
1030 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1031 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
1032
1033 /* setup the system aperture */
1034 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
1035 dev_priv->gart_vm_start);
1036 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
1037 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1038
1039 /* enable page tables */
1040 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1041 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
1042
1043 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1044 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
1045
1046 /* invalidate the cache */
1047 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1048
1049 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1050 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1051 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1052
1053 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
1054 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1055 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1056
1057 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1058 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1059 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1060
1061 } else {
1062 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
1063 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1064 temp &= ~RS600_ENABLE_PAGE_TABLES;
1065 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
1066 }
1067 }
1068
1069 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1070 {
1071 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1072 if (on) {
1073
1074 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1075 dev_priv->gart_vm_start,
1076 (long)dev_priv->gart_info.bus_addr,
1077 dev_priv->gart_size);
1078 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1079 dev_priv->gart_vm_start);
1080 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1081 dev_priv->gart_info.bus_addr);
1082 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1083 dev_priv->gart_vm_start);
1084 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1085 dev_priv->gart_vm_start +
1086 dev_priv->gart_size - 1);
1087
1088 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1089
1090 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1091 RADEON_PCIE_TX_GART_EN);
1092 } else {
1093 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1094 tmp & ~RADEON_PCIE_TX_GART_EN);
1095 }
1096 }
1097
1098 /* Enable or disable PCI GART on the chip */
1099 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1100 {
1101 u32 tmp;
1102
1103 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1104 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
1105 (dev_priv->flags & RADEON_IS_IGPGART)) {
1106 radeon_set_igpgart(dev_priv, on);
1107 return;
1108 }
1109
1110 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1111 rs600_set_igpgart(dev_priv, on);
1112 return;
1113 }
1114
1115 if (dev_priv->flags & RADEON_IS_PCIE) {
1116 radeon_set_pciegart(dev_priv, on);
1117 return;
1118 }
1119
1120 tmp = RADEON_READ(RADEON_AIC_CNTL);
1121
1122 if (on) {
1123 RADEON_WRITE(RADEON_AIC_CNTL,
1124 tmp | RADEON_PCIGART_TRANSLATE_EN);
1125
1126 /* set PCI GART page-table base address
1127 */
1128 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1129
1130 /* set address range for PCI address translate
1131 */
1132 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1133 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1134 + dev_priv->gart_size - 1);
1135
1136 /* Turn off AGP aperture -- is this required for PCI GART?
1137 */
1138 radeon_write_agp_location(dev_priv, 0xffffffc0);
1139 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
1140 } else {
1141 RADEON_WRITE(RADEON_AIC_CNTL,
1142 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1143 }
1144 }
1145
1146 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
1147 {
1148 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
1149 struct radeon_virt_surface *vp;
1150 int i;
1151
1152 for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
1153 if (!dev_priv->virt_surfaces[i].file_priv ||
1154 dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
1155 break;
1156 }
1157 if (i >= 2 * RADEON_MAX_SURFACES)
1158 return -ENOMEM;
1159 vp = &dev_priv->virt_surfaces[i];
1160
1161 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1162 struct radeon_surface *sp = &dev_priv->surfaces[i];
1163 if (sp->refcount)
1164 continue;
1165
1166 vp->surface_index = i;
1167 vp->lower = gart_info->bus_addr;
1168 vp->upper = vp->lower + gart_info->table_size;
1169 vp->flags = 0;
1170 vp->file_priv = PCIGART_FILE_PRIV;
1171
1172 sp->refcount = 1;
1173 sp->lower = vp->lower;
1174 sp->upper = vp->upper;
1175 sp->flags = 0;
1176
1177 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
1178 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
1179 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
1180 return 0;
1181 }
1182
1183 return -ENOMEM;
1184 }
1185
1186 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1187 struct drm_file *file_priv)
1188 {
1189 drm_radeon_private_t *dev_priv = dev->dev_private;
1190 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
1191
1192 DRM_DEBUG("\n");
1193
1194 /* if we require new memory map but we don't have it fail */
1195 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1196 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1197 radeon_do_cleanup_cp(dev);
1198 return -EINVAL;
1199 }
1200
1201 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1202 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1203 dev_priv->flags &= ~RADEON_IS_AGP;
1204 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1205 && !init->is_pci) {
1206 DRM_DEBUG("Restoring AGP flag\n");
1207 dev_priv->flags |= RADEON_IS_AGP;
1208 }
1209
1210 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1211 DRM_ERROR("PCI GART memory not allocated!\n");
1212 radeon_do_cleanup_cp(dev);
1213 return -EINVAL;
1214 }
1215
1216 dev_priv->usec_timeout = init->usec_timeout;
1217 if (dev_priv->usec_timeout < 1 ||
1218 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1219 DRM_DEBUG("TIMEOUT problem!\n");
1220 radeon_do_cleanup_cp(dev);
1221 return -EINVAL;
1222 }
1223
1224 /* Enable vblank on CRTC1 for older X servers
1225 */
1226 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1227
1228 switch(init->func) {
1229 case RADEON_INIT_R200_CP:
1230 dev_priv->microcode_version = UCODE_R200;
1231 break;
1232 case RADEON_INIT_R300_CP:
1233 dev_priv->microcode_version = UCODE_R300;
1234 break;
1235 default:
1236 dev_priv->microcode_version = UCODE_R100;
1237 }
1238
1239 dev_priv->do_boxes = 0;
1240 dev_priv->cp_mode = init->cp_mode;
1241
1242 /* We don't support anything other than bus-mastering ring mode,
1243 * but the ring can be in either AGP or PCI space for the ring
1244 * read pointer.
1245 */
1246 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1247 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1248 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1249 radeon_do_cleanup_cp(dev);
1250 return -EINVAL;
1251 }
1252
1253 switch (init->fb_bpp) {
1254 case 16:
1255 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1256 break;
1257 case 32:
1258 default:
1259 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1260 break;
1261 }
1262 dev_priv->front_offset = init->front_offset;
1263 dev_priv->front_pitch = init->front_pitch;
1264 dev_priv->back_offset = init->back_offset;
1265 dev_priv->back_pitch = init->back_pitch;
1266
1267 switch (init->depth_bpp) {
1268 case 16:
1269 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1270 break;
1271 case 32:
1272 default:
1273 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1274 break;
1275 }
1276 dev_priv->depth_offset = init->depth_offset;
1277 dev_priv->depth_pitch = init->depth_pitch;
1278
1279 /* Hardware state for depth clears. Remove this if/when we no
1280 * longer clear the depth buffer with a 3D rectangle. Hard-code
1281 * all values to prevent unwanted 3D state from slipping through
1282 * and screwing with the clear operation.
1283 */
1284 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1285 (dev_priv->color_fmt << 10) |
1286 (dev_priv->microcode_version ==
1287 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1288
1289 dev_priv->depth_clear.rb3d_zstencilcntl =
1290 (dev_priv->depth_fmt |
1291 RADEON_Z_TEST_ALWAYS |
1292 RADEON_STENCIL_TEST_ALWAYS |
1293 RADEON_STENCIL_S_FAIL_REPLACE |
1294 RADEON_STENCIL_ZPASS_REPLACE |
1295 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1296
1297 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1298 RADEON_BFACE_SOLID |
1299 RADEON_FFACE_SOLID |
1300 RADEON_FLAT_SHADE_VTX_LAST |
1301 RADEON_DIFFUSE_SHADE_FLAT |
1302 RADEON_ALPHA_SHADE_FLAT |
1303 RADEON_SPECULAR_SHADE_FLAT |
1304 RADEON_FOG_SHADE_FLAT |
1305 RADEON_VTX_PIX_CENTER_OGL |
1306 RADEON_ROUND_MODE_TRUNC |
1307 RADEON_ROUND_PREC_8TH_PIX);
1308
1309
1310 dev_priv->ring_offset = init->ring_offset;
1311 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1312 dev_priv->buffers_offset = init->buffers_offset;
1313 dev_priv->gart_textures_offset = init->gart_textures_offset;
1314
1315 master_priv->sarea = drm_getsarea(dev);
1316 if (!master_priv->sarea) {
1317 DRM_ERROR("could not find sarea!\n");
1318 radeon_do_cleanup_cp(dev);
1319 return -EINVAL;
1320 }
1321
1322 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1323 if (!dev_priv->cp_ring) {
1324 DRM_ERROR("could not find cp ring region!\n");
1325 radeon_do_cleanup_cp(dev);
1326 return -EINVAL;
1327 }
1328 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1329 if (!dev_priv->ring_rptr) {
1330 DRM_ERROR("could not find ring read pointer!\n");
1331 radeon_do_cleanup_cp(dev);
1332 return -EINVAL;
1333 }
1334 dev->agp_buffer_token = init->buffers_offset;
1335 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1336 if (!dev->agp_buffer_map) {
1337 DRM_ERROR("could not find dma buffer region!\n");
1338 radeon_do_cleanup_cp(dev);
1339 return -EINVAL;
1340 }
1341
1342 if (init->gart_textures_offset) {
1343 dev_priv->gart_textures =
1344 drm_core_findmap(dev, init->gart_textures_offset);
1345 if (!dev_priv->gart_textures) {
1346 DRM_ERROR("could not find GART texture region!\n");
1347 radeon_do_cleanup_cp(dev);
1348 return -EINVAL;
1349 }
1350 }
1351
1352 #if __OS_HAS_AGP
1353 if (dev_priv->flags & RADEON_IS_AGP) {
1354 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1355 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1356 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1357 if (!dev_priv->cp_ring->handle ||
1358 !dev_priv->ring_rptr->handle ||
1359 !dev->agp_buffer_map->handle) {
1360 DRM_ERROR("could not find ioremap agp regions!\n");
1361 radeon_do_cleanup_cp(dev);
1362 return -EINVAL;
1363 }
1364 } else
1365 #endif
1366 {
1367 dev_priv->cp_ring->handle =
1368 (void *)(unsigned long)dev_priv->cp_ring->offset;
1369 dev_priv->ring_rptr->handle =
1370 (void *)(unsigned long)dev_priv->ring_rptr->offset;
1371 dev->agp_buffer_map->handle =
1372 (void *)(unsigned long)dev->agp_buffer_map->offset;
1373
1374 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1375 dev_priv->cp_ring->handle);
1376 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1377 dev_priv->ring_rptr->handle);
1378 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1379 dev->agp_buffer_map->handle);
1380 }
1381
1382 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1383 dev_priv->fb_size =
1384 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1385 - dev_priv->fb_location;
1386
1387 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1388 ((dev_priv->front_offset
1389 + dev_priv->fb_location) >> 10));
1390
1391 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1392 ((dev_priv->back_offset
1393 + dev_priv->fb_location) >> 10));
1394
1395 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1396 ((dev_priv->depth_offset
1397 + dev_priv->fb_location) >> 10));
1398
1399 dev_priv->gart_size = init->gart_size;
1400
1401 /* New let's set the memory map ... */
1402 if (dev_priv->new_memmap) {
1403 u32 base = 0;
1404
1405 DRM_INFO("Setting GART location based on new memory map\n");
1406
1407 /* If using AGP, try to locate the AGP aperture at the same
1408 * location in the card and on the bus, though we have to
1409 * align it down.
1410 */
1411 #if __OS_HAS_AGP
1412 if (dev_priv->flags & RADEON_IS_AGP) {
1413 base = dev->agp->base;
1414 /* Check if valid */
1415 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1416 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1417 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1418 dev->agp->base);
1419 base = 0;
1420 }
1421 }
1422 #endif
1423 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1424 if (base == 0) {
1425 base = dev_priv->fb_location + dev_priv->fb_size;
1426 if (base < dev_priv->fb_location ||
1427 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1428 base = dev_priv->fb_location
1429 - dev_priv->gart_size;
1430 }
1431 dev_priv->gart_vm_start = base & 0xffc00000u;
1432 if (dev_priv->gart_vm_start != base)
1433 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1434 base, dev_priv->gart_vm_start);
1435 } else {
1436 DRM_INFO("Setting GART location based on old memory map\n");
1437 dev_priv->gart_vm_start = dev_priv->fb_location +
1438 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1439 }
1440
1441 #if __OS_HAS_AGP
1442 if (dev_priv->flags & RADEON_IS_AGP)
1443 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1444 - dev->agp->base
1445 + dev_priv->gart_vm_start);
1446 else
1447 #endif
1448 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1449 - (unsigned long)dev->sg->virtual
1450 + dev_priv->gart_vm_start);
1451
1452 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1453 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1454 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1455 dev_priv->gart_buffers_offset);
1456
1457 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1458 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1459 + init->ring_size / sizeof(u32));
1460 dev_priv->ring.size = init->ring_size;
1461 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1462
1463 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1464 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1465
1466 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1467 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1468 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1469
1470 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1471
1472 #if __OS_HAS_AGP
1473 if (dev_priv->flags & RADEON_IS_AGP) {
1474 /* Turn off PCI GART */
1475 radeon_set_pcigart(dev_priv, 0);
1476 } else
1477 #endif
1478 {
1479 u32 sctrl;
1480 int ret;
1481
1482 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1483 /* if we have an offset set from userspace */
1484 if (dev_priv->pcigart_offset_set) {
1485 dev_priv->gart_info.bus_addr =
1486 (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location;
1487 dev_priv->gart_info.mapping.offset =
1488 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1489 dev_priv->gart_info.mapping.size =
1490 dev_priv->gart_info.table_size;
1491
1492 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1493 dev_priv->gart_info.addr =
1494 dev_priv->gart_info.mapping.handle;
1495
1496 if (dev_priv->flags & RADEON_IS_PCIE)
1497 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1498 else
1499 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1500 dev_priv->gart_info.gart_table_location =
1501 DRM_ATI_GART_FB;
1502
1503 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1504 dev_priv->gart_info.addr,
1505 dev_priv->pcigart_offset);
1506 } else {
1507 if (dev_priv->flags & RADEON_IS_IGPGART)
1508 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1509 else
1510 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1511 dev_priv->gart_info.gart_table_location =
1512 DRM_ATI_GART_MAIN;
1513 dev_priv->gart_info.addr = NULL;
1514 dev_priv->gart_info.bus_addr = 0;
1515 if (dev_priv->flags & RADEON_IS_PCIE) {
1516 DRM_ERROR
1517 ("Cannot use PCI Express without GART in FB memory\n");
1518 radeon_do_cleanup_cp(dev);
1519 return -EINVAL;
1520 }
1521 }
1522
1523 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1524 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1525 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1526 ret = r600_page_table_init(dev);
1527 else
1528 ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1529 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1530
1531 if (!ret) {
1532 DRM_ERROR("failed to init PCI GART!\n");
1533 radeon_do_cleanup_cp(dev);
1534 return -ENOMEM;
1535 }
1536
1537 ret = radeon_setup_pcigart_surface(dev_priv);
1538 if (ret) {
1539 DRM_ERROR("failed to setup GART surface!\n");
1540 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1541 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1542 else
1543 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1544 radeon_do_cleanup_cp(dev);
1545 return ret;
1546 }
1547
1548 /* Turn on PCI GART */
1549 radeon_set_pcigart(dev_priv, 1);
1550 }
1551
1552 if (!dev_priv->me_fw) {
1553 int err = radeon_cp_init_microcode(dev_priv);
1554 if (err) {
1555 DRM_ERROR("Failed to load firmware!\n");
1556 radeon_do_cleanup_cp(dev);
1557 return err;
1558 }
1559 }
1560 radeon_cp_load_microcode(dev_priv);
1561 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1562
1563 dev_priv->last_buf = 0;
1564
1565 radeon_do_engine_reset(dev);
1566 radeon_test_writeback(dev_priv);
1567
1568 return 0;
1569 }
1570
1571 static int radeon_do_cleanup_cp(struct drm_device * dev)
1572 {
1573 drm_radeon_private_t *dev_priv = dev->dev_private;
1574 DRM_DEBUG("\n");
1575
1576 /* Make sure interrupts are disabled here because the uninstall ioctl
1577 * may not have been called from userspace and after dev_private
1578 * is freed, it's too late.
1579 */
1580 if (dev->irq_enabled)
1581 drm_irq_uninstall(dev);
1582
1583 #if __OS_HAS_AGP
1584 if (dev_priv->flags & RADEON_IS_AGP) {
1585 if (dev_priv->cp_ring != NULL) {
1586 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1587 dev_priv->cp_ring = NULL;
1588 }
1589 if (dev_priv->ring_rptr != NULL) {
1590 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1591 dev_priv->ring_rptr = NULL;
1592 }
1593 if (dev->agp_buffer_map != NULL) {
1594 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1595 dev->agp_buffer_map = NULL;
1596 }
1597 } else
1598 #endif
1599 {
1600
1601 if (dev_priv->gart_info.bus_addr) {
1602 /* Turn off PCI GART */
1603 radeon_set_pcigart(dev_priv, 0);
1604 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1605 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1606 else {
1607 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1608 DRM_ERROR("failed to cleanup PCI GART!\n");
1609 }
1610 }
1611
1612 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1613 {
1614 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1615 dev_priv->gart_info.addr = NULL;
1616 }
1617 }
1618 /* only clear to the start of flags */
1619 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1620
1621 return 0;
1622 }
1623
1624 /* This code will reinit the Radeon CP hardware after a resume from disc.
1625 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1626 * here we make sure that all Radeon hardware initialisation is re-done without
1627 * affecting running applications.
1628 *
1629 * Charl P. Botha <http://cpbotha.net>
1630 */
1631 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1632 {
1633 drm_radeon_private_t *dev_priv = dev->dev_private;
1634
1635 if (!dev_priv) {
1636 DRM_ERROR("Called with no initialization\n");
1637 return -EINVAL;
1638 }
1639
1640 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1641
1642 #if __OS_HAS_AGP
1643 if (dev_priv->flags & RADEON_IS_AGP) {
1644 /* Turn off PCI GART */
1645 radeon_set_pcigart(dev_priv, 0);
1646 } else
1647 #endif
1648 {
1649 /* Turn on PCI GART */
1650 radeon_set_pcigart(dev_priv, 1);
1651 }
1652
1653 radeon_cp_load_microcode(dev_priv);
1654 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1655
1656 dev_priv->have_z_offset = 0;
1657 radeon_do_engine_reset(dev);
1658 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1659
1660 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1661
1662 return 0;
1663 }
1664
1665 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1666 {
1667 drm_radeon_private_t *dev_priv = dev->dev_private;
1668 drm_radeon_init_t *init = data;
1669
1670 LOCK_TEST_WITH_RETURN(dev, file_priv);
1671
1672 if (init->func == RADEON_INIT_R300_CP)
1673 r300_init_reg_flags(dev);
1674
1675 switch (init->func) {
1676 case RADEON_INIT_CP:
1677 case RADEON_INIT_R200_CP:
1678 case RADEON_INIT_R300_CP:
1679 return radeon_do_init_cp(dev, init, file_priv);
1680 case RADEON_INIT_R600_CP:
1681 return r600_do_init_cp(dev, init, file_priv);
1682 case RADEON_CLEANUP_CP:
1683 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1684 return r600_do_cleanup_cp(dev);
1685 else
1686 return radeon_do_cleanup_cp(dev);
1687 }
1688
1689 return -EINVAL;
1690 }
1691
1692 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1693 {
1694 drm_radeon_private_t *dev_priv = dev->dev_private;
1695 DRM_DEBUG("\n");
1696
1697 LOCK_TEST_WITH_RETURN(dev, file_priv);
1698
1699 if (dev_priv->cp_running) {
1700 DRM_DEBUG("while CP running\n");
1701 return 0;
1702 }
1703 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1704 DRM_DEBUG("called with bogus CP mode (%d)\n",
1705 dev_priv->cp_mode);
1706 return 0;
1707 }
1708
1709 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1710 r600_do_cp_start(dev_priv);
1711 else
1712 radeon_do_cp_start(dev_priv);
1713
1714 return 0;
1715 }
1716
1717 /* Stop the CP. The engine must have been idled before calling this
1718 * routine.
1719 */
1720 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1721 {
1722 drm_radeon_private_t *dev_priv = dev->dev_private;
1723 drm_radeon_cp_stop_t *stop = data;
1724 int ret;
1725 DRM_DEBUG("\n");
1726
1727 LOCK_TEST_WITH_RETURN(dev, file_priv);
1728
1729 if (!dev_priv->cp_running)
1730 return 0;
1731
1732 /* Flush any pending CP commands. This ensures any outstanding
1733 * commands are exectuted by the engine before we turn it off.
1734 */
1735 if (stop->flush) {
1736 radeon_do_cp_flush(dev_priv);
1737 }
1738
1739 /* If we fail to make the engine go idle, we return an error
1740 * code so that the DRM ioctl wrapper can try again.
1741 */
1742 if (stop->idle) {
1743 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1744 ret = r600_do_cp_idle(dev_priv);
1745 else
1746 ret = radeon_do_cp_idle(dev_priv);
1747 if (ret)
1748 return ret;
1749 }
1750
1751 /* Finally, we can turn off the CP. If the engine isn't idle,
1752 * we will get some dropped triangles as they won't be fully
1753 * rendered before the CP is shut down.
1754 */
1755 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1756 r600_do_cp_stop(dev_priv);
1757 else
1758 radeon_do_cp_stop(dev_priv);
1759
1760 /* Reset the engine */
1761 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1762 r600_do_engine_reset(dev);
1763 else
1764 radeon_do_engine_reset(dev);
1765
1766 return 0;
1767 }
1768
1769 void radeon_do_release(struct drm_device * dev)
1770 {
1771 drm_radeon_private_t *dev_priv = dev->dev_private;
1772 int i, ret;
1773
1774 if (dev_priv) {
1775 if (dev_priv->cp_running) {
1776 /* Stop the cp */
1777 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1778 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1779 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1780 #ifdef __linux__
1781 schedule();
1782 #else
1783 tsleep(&ret, PZERO, "rdnrel", 1);
1784 #endif
1785 }
1786 } else {
1787 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1788 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1789 #ifdef __linux__
1790 schedule();
1791 #else
1792 tsleep(&ret, PZERO, "rdnrel", 1);
1793 #endif
1794 }
1795 }
1796 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1797 r600_do_cp_stop(dev_priv);
1798 r600_do_engine_reset(dev);
1799 } else {
1800 radeon_do_cp_stop(dev_priv);
1801 radeon_do_engine_reset(dev);
1802 }
1803 }
1804
1805 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1806 /* Disable *all* interrupts */
1807 if (dev_priv->mmio) /* remove this after permanent addmaps */
1808 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1809
1810 if (dev_priv->mmio) { /* remove all surfaces */
1811 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1812 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1813 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1814 16 * i, 0);
1815 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1816 16 * i, 0);
1817 }
1818 }
1819 }
1820
1821 /* Free memory heap structures */
1822 radeon_mem_takedown(&(dev_priv->gart_heap));
1823 radeon_mem_takedown(&(dev_priv->fb_heap));
1824
1825 /* deallocate kernel resources */
1826 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1827 r600_do_cleanup_cp(dev);
1828 else
1829 radeon_do_cleanup_cp(dev);
1830 if (dev_priv->me_fw) {
1831 release_firmware(dev_priv->me_fw);
1832 dev_priv->me_fw = NULL;
1833 }
1834 if (dev_priv->pfp_fw) {
1835 release_firmware(dev_priv->pfp_fw);
1836 dev_priv->pfp_fw = NULL;
1837 }
1838 }
1839 }
1840
1841 /* Just reset the CP ring. Called as part of an X Server engine reset.
1842 */
1843 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1844 {
1845 drm_radeon_private_t *dev_priv = dev->dev_private;
1846 DRM_DEBUG("\n");
1847
1848 LOCK_TEST_WITH_RETURN(dev, file_priv);
1849
1850 if (!dev_priv) {
1851 DRM_DEBUG("called before init done\n");
1852 return -EINVAL;
1853 }
1854
1855 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1856 r600_do_cp_reset(dev_priv);
1857 else
1858 radeon_do_cp_reset(dev_priv);
1859
1860 /* The CP is no longer running after an engine reset */
1861 dev_priv->cp_running = 0;
1862
1863 return 0;
1864 }
1865
1866 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1867 {
1868 drm_radeon_private_t *dev_priv = dev->dev_private;
1869 DRM_DEBUG("\n");
1870
1871 LOCK_TEST_WITH_RETURN(dev, file_priv);
1872
1873 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1874 return r600_do_cp_idle(dev_priv);
1875 else
1876 return radeon_do_cp_idle(dev_priv);
1877 }
1878
1879 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1880 */
1881 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1882 {
1883 drm_radeon_private_t *dev_priv = dev->dev_private;
1884 DRM_DEBUG("\n");
1885
1886 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1887 return r600_do_resume_cp(dev, file_priv);
1888 else
1889 return radeon_do_resume_cp(dev, file_priv);
1890 }
1891
1892 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1893 {
1894 drm_radeon_private_t *dev_priv = dev->dev_private;
1895 DRM_DEBUG("\n");
1896
1897 LOCK_TEST_WITH_RETURN(dev, file_priv);
1898
1899 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1900 return r600_do_engine_reset(dev);
1901 else
1902 return radeon_do_engine_reset(dev);
1903 }
1904
1905 /* ================================================================
1906 * Fullscreen mode
1907 */
1908
1909 /* KW: Deprecated to say the least:
1910 */
1911 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1912 {
1913 return 0;
1914 }
1915
1916 /* ================================================================
1917 * Freelist management
1918 */
1919
1920 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1921 * bufs until freelist code is used. Note this hides a problem with
1922 * the scratch register * (used to keep track of last buffer
1923 * completed) being written to before * the last buffer has actually
1924 * completed rendering.
1925 *
1926 * KW: It's also a good way to find free buffers quickly.
1927 *
1928 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1929 * sleep. However, bugs in older versions of radeon_accel.c mean that
1930 * we essentially have to do this, else old clients will break.
1931 *
1932 * However, it does leave open a potential deadlock where all the
1933 * buffers are held by other clients, which can't release them because
1934 * they can't get the lock.
1935 */
1936
1937 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1938 {
1939 struct drm_device_dma *dma = dev->dma;
1940 drm_radeon_private_t *dev_priv = dev->dev_private;
1941 drm_radeon_buf_priv_t *buf_priv;
1942 struct drm_buf *buf;
1943 int i, t;
1944 int start;
1945
1946 if (++dev_priv->last_buf >= dma->buf_count)
1947 dev_priv->last_buf = 0;
1948
1949 start = dev_priv->last_buf;
1950
1951 for (t = 0; t < dev_priv->usec_timeout; t++) {
1952 u32 done_age = GET_SCRATCH(dev_priv, 1);
1953 DRM_DEBUG("done_age = %d\n", done_age);
1954 for (i = 0; i < dma->buf_count; i++) {
1955 buf = dma->buflist[start];
1956 buf_priv = buf->dev_private;
1957 if (buf->file_priv == NULL || (buf->pending &&
1958 buf_priv->age <=
1959 done_age)) {
1960 dev_priv->stats.requested_bufs++;
1961 buf->pending = 0;
1962 return buf;
1963 }
1964 if (++start >= dma->buf_count)
1965 start = 0;
1966 }
1967
1968 if (t) {
1969 DRM_UDELAY(1);
1970 dev_priv->stats.freelist_loops++;
1971 }
1972 }
1973
1974 return NULL;
1975 }
1976
1977 void radeon_freelist_reset(struct drm_device * dev)
1978 {
1979 struct drm_device_dma *dma = dev->dma;
1980 drm_radeon_private_t *dev_priv = dev->dev_private;
1981 int i;
1982
1983 dev_priv->last_buf = 0;
1984 for (i = 0; i < dma->buf_count; i++) {
1985 struct drm_buf *buf = dma->buflist[i];
1986 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1987 buf_priv->age = 0;
1988 }
1989 }
1990
1991 /* ================================================================
1992 * CP command submission
1993 */
1994
1995 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1996 {
1997 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1998 int i;
1999 u32 last_head = GET_RING_HEAD(dev_priv);
2000
2001 for (i = 0; i < dev_priv->usec_timeout; i++) {
2002 u32 head = GET_RING_HEAD(dev_priv);
2003
2004 ring->space = (head - ring->tail) * sizeof(u32);
2005 if (ring->space <= 0)
2006 ring->space += ring->size;
2007 if (ring->space > n)
2008 return 0;
2009
2010 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
2011
2012 if (head != last_head)
2013 i = 0;
2014 last_head = head;
2015
2016 DRM_UDELAY(1);
2017 }
2018
2019 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
2020 #if RADEON_FIFO_DEBUG
2021 radeon_status(dev_priv);
2022 DRM_ERROR("failed!\n");
2023 #endif
2024 return -EBUSY;
2025 }
2026
2027 static int radeon_cp_get_buffers(struct drm_device *dev,
2028 struct drm_file *file_priv,
2029 struct drm_dma * d)
2030 {
2031 int i;
2032 struct drm_buf *buf;
2033
2034 for (i = d->granted_count; i < d->request_count; i++) {
2035 buf = radeon_freelist_get(dev);
2036 if (!buf)
2037 return -EBUSY; /* NOTE: broken client */
2038
2039 buf->file_priv = file_priv;
2040
2041 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
2042 sizeof(buf->idx)))
2043 return -EFAULT;
2044 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
2045 sizeof(buf->total)))
2046 return -EFAULT;
2047
2048 d->granted_count++;
2049 }
2050 return 0;
2051 }
2052
2053 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
2054 {
2055 struct drm_device_dma *dma = dev->dma;
2056 int ret = 0;
2057 struct drm_dma *d = data;
2058
2059 LOCK_TEST_WITH_RETURN(dev, file_priv);
2060
2061 /* Please don't send us buffers.
2062 */
2063 if (d->send_count != 0) {
2064 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2065 DRM_CURRENTPID, d->send_count);
2066 return -EINVAL;
2067 }
2068
2069 /* We'll send you buffers.
2070 */
2071 if (d->request_count < 0 || d->request_count > dma->buf_count) {
2072 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2073 DRM_CURRENTPID, d->request_count, dma->buf_count);
2074 return -EINVAL;
2075 }
2076
2077 d->granted_count = 0;
2078
2079 if (d->request_count) {
2080 ret = radeon_cp_get_buffers(dev, file_priv, d);
2081 }
2082
2083 return ret;
2084 }
2085
2086 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2087 {
2088 drm_radeon_private_t *dev_priv;
2089 int ret = 0;
2090
2091 dev_priv = kzalloc(sizeof(drm_radeon_private_t), GFP_KERNEL);
2092 if (dev_priv == NULL)
2093 return -ENOMEM;
2094
2095 dev->dev_private = (void *)dev_priv;
2096 dev_priv->flags = flags;
2097
2098 switch (flags & RADEON_FAMILY_MASK) {
2099 case CHIP_R100:
2100 case CHIP_RV200:
2101 case CHIP_R200:
2102 case CHIP_R300:
2103 case CHIP_R350:
2104 case CHIP_R420:
2105 case CHIP_R423:
2106 case CHIP_RV410:
2107 case CHIP_RV515:
2108 case CHIP_R520:
2109 case CHIP_RV570:
2110 case CHIP_R580:
2111 dev_priv->flags |= RADEON_HAS_HIERZ;
2112 break;
2113 default:
2114 /* all other chips have no hierarchical z buffer */
2115 break;
2116 }
2117
2118 if (drm_pci_device_is_agp(dev))
2119 dev_priv->flags |= RADEON_IS_AGP;
2120 else if (pci_is_pcie(dev->pdev))
2121 dev_priv->flags |= RADEON_IS_PCIE;
2122 else
2123 dev_priv->flags |= RADEON_IS_PCI;
2124
2125 ret = drm_addmap(dev, pci_resource_start(dev->pdev, 2),
2126 pci_resource_len(dev->pdev, 2), _DRM_REGISTERS,
2127 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2128 if (ret != 0)
2129 return ret;
2130
2131 ret = drm_vblank_init(dev, 2);
2132 if (ret) {
2133 radeon_driver_unload(dev);
2134 return ret;
2135 }
2136
2137 DRM_DEBUG("%s card detected\n",
2138 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2139 return ret;
2140 }
2141
2142 int radeon_master_create(struct drm_device *dev, struct drm_master *master)
2143 {
2144 struct drm_radeon_master_private *master_priv;
2145 unsigned long sareapage;
2146 int ret;
2147
2148 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
2149 if (!master_priv)
2150 return -ENOMEM;
2151
2152 /* prebuild the SAREA */
2153 sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
2154 ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK,
2155 &master_priv->sarea);
2156 if (ret) {
2157 DRM_ERROR("SAREA setup failed\n");
2158 kfree(master_priv);
2159 return ret;
2160 }
2161 master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
2162 master_priv->sarea_priv->pfCurrentPage = 0;
2163
2164 master->driver_priv = master_priv;
2165 return 0;
2166 }
2167
2168 void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
2169 {
2170 struct drm_radeon_master_private *master_priv = master->driver_priv;
2171
2172 if (!master_priv)
2173 return;
2174
2175 if (master_priv->sarea_priv &&
2176 master_priv->sarea_priv->pfCurrentPage != 0)
2177 radeon_cp_dispatch_flip(dev, master);
2178
2179 master_priv->sarea_priv = NULL;
2180 if (master_priv->sarea)
2181 drm_rmmap_locked(dev, master_priv->sarea);
2182
2183 kfree(master_priv);
2184
2185 master->driver_priv = NULL;
2186 }
2187
2188 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2189 * have to find them.
2190 */
2191 int radeon_driver_firstopen(struct drm_device *dev)
2192 {
2193 int ret;
2194 drm_local_map_t *map;
2195 drm_radeon_private_t *dev_priv = dev->dev_private;
2196
2197 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2198
2199 dev_priv->fb_aper_offset = pci_resource_start(dev->pdev, 0);
2200 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2201 pci_resource_len(dev->pdev, 0), _DRM_FRAME_BUFFER,
2202 _DRM_WRITE_COMBINING, &map);
2203 if (ret != 0)
2204 return ret;
2205
2206 return 0;
2207 }
2208
2209 int radeon_driver_unload(struct drm_device *dev)
2210 {
2211 drm_radeon_private_t *dev_priv = dev->dev_private;
2212
2213 DRM_DEBUG("\n");
2214
2215 drm_rmmap(dev, dev_priv->mmio);
2216
2217 kfree(dev_priv);
2218
2219 dev->dev_private = NULL;
2220 return 0;
2221 }
2222
2223 void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2224 {
2225 int i;
2226 u32 *ring;
2227 int tail_aligned;
2228
2229 /* check if the ring is padded out to 16-dword alignment */
2230
2231 tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN-1);
2232 if (tail_aligned) {
2233 int num_p2 = RADEON_RING_ALIGN - tail_aligned;
2234
2235 ring = dev_priv->ring.start;
2236 /* pad with some CP_PACKET2 */
2237 for (i = 0; i < num_p2; i++)
2238 ring[dev_priv->ring.tail + i] = CP_PACKET2();
2239
2240 dev_priv->ring.tail += i;
2241
2242 dev_priv->ring.space -= num_p2 * sizeof(u32);
2243 }
2244
2245 dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2246
2247 DRM_MEMORYBARRIER();
2248 GET_RING_HEAD( dev_priv );
2249
2250 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2251 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2252 /* read from PCI bus to ensure correct posting */
2253 RADEON_READ(R600_CP_RB_RPTR);
2254 } else {
2255 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
2256 /* read from PCI bus to ensure correct posting */
2257 RADEON_READ(RADEON_CP_RB_RPTR);
2258 }
2259 }