percpu, x86: don't use PMD_SIZE as embedded atom_size on 32bit
[zen-stable.git] / drivers / usb / gadget / amd5536udc.h
blobf87e29c65325dbde896976d75e5492b55cfb1aa8
1 /*
2 * amd5536.h -- header for AMD 5536 UDC high/full speed USB device controller
4 * Copyright (C) 2007 AMD (http://www.amd.com)
5 * Author: Thomas Dahlmann
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #ifndef AMD5536UDC_H
14 #define AMD5536UDC_H
16 /* various constants */
17 #define UDC_RDE_TIMER_SECONDS 1
18 #define UDC_RDE_TIMER_DIV 10
19 #define UDC_POLLSTALL_TIMER_USECONDS 500
21 /* Hs AMD5536 chip rev. */
22 #define UDC_HSA0_REV 1
23 #define UDC_HSB1_REV 2
26 * SETUP usb commands
27 * needed, because some SETUP's are handled in hw, but must be passed to
28 * gadget driver above
29 * SET_CONFIG
31 #define UDC_SETCONFIG_DWORD0 0x00000900
32 #define UDC_SETCONFIG_DWORD0_VALUE_MASK 0xffff0000
33 #define UDC_SETCONFIG_DWORD0_VALUE_OFS 16
35 #define UDC_SETCONFIG_DWORD1 0x00000000
37 /* SET_INTERFACE */
38 #define UDC_SETINTF_DWORD0 0x00000b00
39 #define UDC_SETINTF_DWORD0_ALT_MASK 0xffff0000
40 #define UDC_SETINTF_DWORD0_ALT_OFS 16
42 #define UDC_SETINTF_DWORD1 0x00000000
43 #define UDC_SETINTF_DWORD1_INTF_MASK 0x0000ffff
44 #define UDC_SETINTF_DWORD1_INTF_OFS 0
46 /* Mass storage reset */
47 #define UDC_MSCRES_DWORD0 0x0000ff21
48 #define UDC_MSCRES_DWORD1 0x00000000
50 /* Global CSR's -------------------------------------------------------------*/
51 #define UDC_CSR_ADDR 0x500
53 /* EP NE bits */
54 /* EP number */
55 #define UDC_CSR_NE_NUM_MASK 0x0000000f
56 #define UDC_CSR_NE_NUM_OFS 0
57 /* EP direction */
58 #define UDC_CSR_NE_DIR_MASK 0x00000010
59 #define UDC_CSR_NE_DIR_OFS 4
60 /* EP type */
61 #define UDC_CSR_NE_TYPE_MASK 0x00000060
62 #define UDC_CSR_NE_TYPE_OFS 5
63 /* EP config number */
64 #define UDC_CSR_NE_CFG_MASK 0x00000780
65 #define UDC_CSR_NE_CFG_OFS 7
66 /* EP interface number */
67 #define UDC_CSR_NE_INTF_MASK 0x00007800
68 #define UDC_CSR_NE_INTF_OFS 11
69 /* EP alt setting */
70 #define UDC_CSR_NE_ALT_MASK 0x00078000
71 #define UDC_CSR_NE_ALT_OFS 15
73 /* max pkt */
74 #define UDC_CSR_NE_MAX_PKT_MASK 0x3ff80000
75 #define UDC_CSR_NE_MAX_PKT_OFS 19
77 /* Device Config Register ---------------------------------------------------*/
78 #define UDC_DEVCFG_ADDR 0x400
80 #define UDC_DEVCFG_SOFTRESET 31
81 #define UDC_DEVCFG_HNPSFEN 30
82 #define UDC_DEVCFG_DMARST 29
83 #define UDC_DEVCFG_SET_DESC 18
84 #define UDC_DEVCFG_CSR_PRG 17
85 #define UDC_DEVCFG_STATUS 7
86 #define UDC_DEVCFG_DIR 6
87 #define UDC_DEVCFG_PI 5
88 #define UDC_DEVCFG_SS 4
89 #define UDC_DEVCFG_SP 3
90 #define UDC_DEVCFG_RWKP 2
92 #define UDC_DEVCFG_SPD_MASK 0x3
93 #define UDC_DEVCFG_SPD_OFS 0
94 #define UDC_DEVCFG_SPD_HS 0x0
95 #define UDC_DEVCFG_SPD_FS 0x1
96 #define UDC_DEVCFG_SPD_LS 0x2
97 /*#define UDC_DEVCFG_SPD_FS 0x3*/
100 /* Device Control Register --------------------------------------------------*/
101 #define UDC_DEVCTL_ADDR 0x404
103 #define UDC_DEVCTL_THLEN_MASK 0xff000000
104 #define UDC_DEVCTL_THLEN_OFS 24
106 #define UDC_DEVCTL_BRLEN_MASK 0x00ff0000
107 #define UDC_DEVCTL_BRLEN_OFS 16
109 #define UDC_DEVCTL_CSR_DONE 13
110 #define UDC_DEVCTL_DEVNAK 12
111 #define UDC_DEVCTL_SD 10
112 #define UDC_DEVCTL_MODE 9
113 #define UDC_DEVCTL_BREN 8
114 #define UDC_DEVCTL_THE 7
115 #define UDC_DEVCTL_BF 6
116 #define UDC_DEVCTL_BE 5
117 #define UDC_DEVCTL_DU 4
118 #define UDC_DEVCTL_TDE 3
119 #define UDC_DEVCTL_RDE 2
120 #define UDC_DEVCTL_RES 0
123 /* Device Status Register ---------------------------------------------------*/
124 #define UDC_DEVSTS_ADDR 0x408
126 #define UDC_DEVSTS_TS_MASK 0xfffc0000
127 #define UDC_DEVSTS_TS_OFS 18
129 #define UDC_DEVSTS_SESSVLD 17
130 #define UDC_DEVSTS_PHY_ERROR 16
131 #define UDC_DEVSTS_RXFIFO_EMPTY 15
133 #define UDC_DEVSTS_ENUM_SPEED_MASK 0x00006000
134 #define UDC_DEVSTS_ENUM_SPEED_OFS 13
135 #define UDC_DEVSTS_ENUM_SPEED_FULL 1
136 #define UDC_DEVSTS_ENUM_SPEED_HIGH 0
138 #define UDC_DEVSTS_SUSP 12
140 #define UDC_DEVSTS_ALT_MASK 0x00000f00
141 #define UDC_DEVSTS_ALT_OFS 8
143 #define UDC_DEVSTS_INTF_MASK 0x000000f0
144 #define UDC_DEVSTS_INTF_OFS 4
146 #define UDC_DEVSTS_CFG_MASK 0x0000000f
147 #define UDC_DEVSTS_CFG_OFS 0
150 /* Device Interrupt Register ------------------------------------------------*/
151 #define UDC_DEVINT_ADDR 0x40c
153 #define UDC_DEVINT_SVC 7
154 #define UDC_DEVINT_ENUM 6
155 #define UDC_DEVINT_SOF 5
156 #define UDC_DEVINT_US 4
157 #define UDC_DEVINT_UR 3
158 #define UDC_DEVINT_ES 2
159 #define UDC_DEVINT_SI 1
160 #define UDC_DEVINT_SC 0
162 /* Device Interrupt Mask Register -------------------------------------------*/
163 #define UDC_DEVINT_MSK_ADDR 0x410
165 #define UDC_DEVINT_MSK 0x7f
167 /* Endpoint Interrupt Register ----------------------------------------------*/
168 #define UDC_EPINT_ADDR 0x414
170 #define UDC_EPINT_OUT_MASK 0xffff0000
171 #define UDC_EPINT_OUT_OFS 16
172 #define UDC_EPINT_IN_MASK 0x0000ffff
173 #define UDC_EPINT_IN_OFS 0
175 #define UDC_EPINT_IN_EP0 0
176 #define UDC_EPINT_IN_EP1 1
177 #define UDC_EPINT_IN_EP2 2
178 #define UDC_EPINT_IN_EP3 3
179 #define UDC_EPINT_OUT_EP0 16
180 #define UDC_EPINT_OUT_EP1 17
181 #define UDC_EPINT_OUT_EP2 18
182 #define UDC_EPINT_OUT_EP3 19
184 #define UDC_EPINT_EP0_ENABLE_MSK 0x001e001e
186 /* Endpoint Interrupt Mask Register -----------------------------------------*/
187 #define UDC_EPINT_MSK_ADDR 0x418
189 #define UDC_EPINT_OUT_MSK_MASK 0xffff0000
190 #define UDC_EPINT_OUT_MSK_OFS 16
191 #define UDC_EPINT_IN_MSK_MASK 0x0000ffff
192 #define UDC_EPINT_IN_MSK_OFS 0
194 #define UDC_EPINT_MSK_DISABLE_ALL 0xffffffff
195 /* mask non-EP0 endpoints */
196 #define UDC_EPDATAINT_MSK_DISABLE 0xfffefffe
197 /* mask all dev interrupts */
198 #define UDC_DEV_MSK_DISABLE 0x7f
200 /* Endpoint-specific CSR's --------------------------------------------------*/
201 #define UDC_EPREGS_ADDR 0x0
202 #define UDC_EPIN_REGS_ADDR 0x0
203 #define UDC_EPOUT_REGS_ADDR 0x200
205 #define UDC_EPCTL_ADDR 0x0
207 #define UDC_EPCTL_RRDY 9
208 #define UDC_EPCTL_CNAK 8
209 #define UDC_EPCTL_SNAK 7
210 #define UDC_EPCTL_NAK 6
212 #define UDC_EPCTL_ET_MASK 0x00000030
213 #define UDC_EPCTL_ET_OFS 4
214 #define UDC_EPCTL_ET_CONTROL 0
215 #define UDC_EPCTL_ET_ISO 1
216 #define UDC_EPCTL_ET_BULK 2
217 #define UDC_EPCTL_ET_INTERRUPT 3
219 #define UDC_EPCTL_P 3
220 #define UDC_EPCTL_SN 2
221 #define UDC_EPCTL_F 1
222 #define UDC_EPCTL_S 0
224 /* Endpoint Status Registers ------------------------------------------------*/
225 #define UDC_EPSTS_ADDR 0x4
227 #define UDC_EPSTS_RX_PKT_SIZE_MASK 0x007ff800
228 #define UDC_EPSTS_RX_PKT_SIZE_OFS 11
230 #define UDC_EPSTS_TDC 10
231 #define UDC_EPSTS_HE 9
232 #define UDC_EPSTS_BNA 7
233 #define UDC_EPSTS_IN 6
235 #define UDC_EPSTS_OUT_MASK 0x00000030
236 #define UDC_EPSTS_OUT_OFS 4
237 #define UDC_EPSTS_OUT_DATA 1
238 #define UDC_EPSTS_OUT_DATA_CLEAR 0x10
239 #define UDC_EPSTS_OUT_SETUP 2
240 #define UDC_EPSTS_OUT_SETUP_CLEAR 0x20
241 #define UDC_EPSTS_OUT_CLEAR 0x30
243 /* Endpoint Buffer Size IN/ Receive Packet Frame Number OUT Registers ------*/
244 #define UDC_EPIN_BUFF_SIZE_ADDR 0x8
245 #define UDC_EPOUT_FRAME_NUMBER_ADDR 0x8
247 #define UDC_EPIN_BUFF_SIZE_MASK 0x0000ffff
248 #define UDC_EPIN_BUFF_SIZE_OFS 0
249 /* EP0in txfifo = 128 bytes*/
250 #define UDC_EPIN0_BUFF_SIZE 32
251 /* EP0in fullspeed txfifo = 128 bytes*/
252 #define UDC_FS_EPIN0_BUFF_SIZE 32
254 /* fifo size mult = fifo size / max packet */
255 #define UDC_EPIN_BUFF_SIZE_MULT 2
257 /* EPin data fifo size = 1024 bytes DOUBLE BUFFERING */
258 #define UDC_EPIN_BUFF_SIZE 256
259 /* EPin small INT data fifo size = 128 bytes */
260 #define UDC_EPIN_SMALLINT_BUFF_SIZE 32
262 /* EPin fullspeed data fifo size = 128 bytes DOUBLE BUFFERING */
263 #define UDC_FS_EPIN_BUFF_SIZE 32
265 #define UDC_EPOUT_FRAME_NUMBER_MASK 0x0000ffff
266 #define UDC_EPOUT_FRAME_NUMBER_OFS 0
268 /* Endpoint Buffer Size OUT/Max Packet Size Registers -----------------------*/
269 #define UDC_EPOUT_BUFF_SIZE_ADDR 0x0c
270 #define UDC_EP_MAX_PKT_SIZE_ADDR 0x0c
272 #define UDC_EPOUT_BUFF_SIZE_MASK 0xffff0000
273 #define UDC_EPOUT_BUFF_SIZE_OFS 16
274 #define UDC_EP_MAX_PKT_SIZE_MASK 0x0000ffff
275 #define UDC_EP_MAX_PKT_SIZE_OFS 0
276 /* EP0in max packet size = 64 bytes */
277 #define UDC_EP0IN_MAX_PKT_SIZE 64
278 /* EP0out max packet size = 64 bytes */
279 #define UDC_EP0OUT_MAX_PKT_SIZE 64
280 /* EP0in fullspeed max packet size = 64 bytes */
281 #define UDC_FS_EP0IN_MAX_PKT_SIZE 64
282 /* EP0out fullspeed max packet size = 64 bytes */
283 #define UDC_FS_EP0OUT_MAX_PKT_SIZE 64
286 * Endpoint dma descriptors ------------------------------------------------
288 * Setup data, Status dword
290 #define UDC_DMA_STP_STS_CFG_MASK 0x0fff0000
291 #define UDC_DMA_STP_STS_CFG_OFS 16
292 #define UDC_DMA_STP_STS_CFG_ALT_MASK 0x000f0000
293 #define UDC_DMA_STP_STS_CFG_ALT_OFS 16
294 #define UDC_DMA_STP_STS_CFG_INTF_MASK 0x00f00000
295 #define UDC_DMA_STP_STS_CFG_INTF_OFS 20
296 #define UDC_DMA_STP_STS_CFG_NUM_MASK 0x0f000000
297 #define UDC_DMA_STP_STS_CFG_NUM_OFS 24
298 #define UDC_DMA_STP_STS_RX_MASK 0x30000000
299 #define UDC_DMA_STP_STS_RX_OFS 28
300 #define UDC_DMA_STP_STS_BS_MASK 0xc0000000
301 #define UDC_DMA_STP_STS_BS_OFS 30
302 #define UDC_DMA_STP_STS_BS_HOST_READY 0
303 #define UDC_DMA_STP_STS_BS_DMA_BUSY 1
304 #define UDC_DMA_STP_STS_BS_DMA_DONE 2
305 #define UDC_DMA_STP_STS_BS_HOST_BUSY 3
306 /* IN data, Status dword */
307 #define UDC_DMA_IN_STS_TXBYTES_MASK 0x0000ffff
308 #define UDC_DMA_IN_STS_TXBYTES_OFS 0
309 #define UDC_DMA_IN_STS_FRAMENUM_MASK 0x07ff0000
310 #define UDC_DMA_IN_STS_FRAMENUM_OFS 0
311 #define UDC_DMA_IN_STS_L 27
312 #define UDC_DMA_IN_STS_TX_MASK 0x30000000
313 #define UDC_DMA_IN_STS_TX_OFS 28
314 #define UDC_DMA_IN_STS_BS_MASK 0xc0000000
315 #define UDC_DMA_IN_STS_BS_OFS 30
316 #define UDC_DMA_IN_STS_BS_HOST_READY 0
317 #define UDC_DMA_IN_STS_BS_DMA_BUSY 1
318 #define UDC_DMA_IN_STS_BS_DMA_DONE 2
319 #define UDC_DMA_IN_STS_BS_HOST_BUSY 3
320 /* OUT data, Status dword */
321 #define UDC_DMA_OUT_STS_RXBYTES_MASK 0x0000ffff
322 #define UDC_DMA_OUT_STS_RXBYTES_OFS 0
323 #define UDC_DMA_OUT_STS_FRAMENUM_MASK 0x07ff0000
324 #define UDC_DMA_OUT_STS_FRAMENUM_OFS 0
325 #define UDC_DMA_OUT_STS_L 27
326 #define UDC_DMA_OUT_STS_RX_MASK 0x30000000
327 #define UDC_DMA_OUT_STS_RX_OFS 28
328 #define UDC_DMA_OUT_STS_BS_MASK 0xc0000000
329 #define UDC_DMA_OUT_STS_BS_OFS 30
330 #define UDC_DMA_OUT_STS_BS_HOST_READY 0
331 #define UDC_DMA_OUT_STS_BS_DMA_BUSY 1
332 #define UDC_DMA_OUT_STS_BS_DMA_DONE 2
333 #define UDC_DMA_OUT_STS_BS_HOST_BUSY 3
334 /* max ep0in packet */
335 #define UDC_EP0IN_MAXPACKET 1000
336 /* max dma packet */
337 #define UDC_DMA_MAXPACKET 65536
339 /* un-usable DMA address */
340 #define DMA_DONT_USE (~(dma_addr_t) 0 )
342 /* other Endpoint register addresses and values-----------------------------*/
343 #define UDC_EP_SUBPTR_ADDR 0x10
344 #define UDC_EP_DESPTR_ADDR 0x14
345 #define UDC_EP_WRITE_CONFIRM_ADDR 0x1c
347 /* EP number as layouted in AHB space */
348 #define UDC_EP_NUM 32
349 #define UDC_EPIN_NUM 16
350 #define UDC_EPIN_NUM_USED 5
351 #define UDC_EPOUT_NUM 16
352 /* EP number of EP's really used = EP0 + 8 data EP's */
353 #define UDC_USED_EP_NUM 9
354 /* UDC CSR regs are aligned but AHB regs not - offset for OUT EP's */
355 #define UDC_CSR_EP_OUT_IX_OFS 12
357 #define UDC_EP0OUT_IX 16
358 #define UDC_EP0IN_IX 0
360 /* Rx fifo address and size = 1k -------------------------------------------*/
361 #define UDC_RXFIFO_ADDR 0x800
362 #define UDC_RXFIFO_SIZE 0x400
364 /* Tx fifo address and size = 1.5k -----------------------------------------*/
365 #define UDC_TXFIFO_ADDR 0xc00
366 #define UDC_TXFIFO_SIZE 0x600
368 /* default data endpoints --------------------------------------------------*/
369 #define UDC_EPIN_STATUS_IX 1
370 #define UDC_EPIN_IX 2
371 #define UDC_EPOUT_IX 18
373 /* general constants -------------------------------------------------------*/
374 #define UDC_DWORD_BYTES 4
375 #define UDC_BITS_PER_BYTE_SHIFT 3
376 #define UDC_BYTE_MASK 0xff
377 #define UDC_BITS_PER_BYTE 8
379 /*---------------------------------------------------------------------------*/
380 /* UDC CSR's */
381 struct udc_csrs {
383 /* sca - setup command address */
384 u32 sca;
386 /* ep ne's */
387 u32 ne[UDC_USED_EP_NUM];
388 } __attribute__ ((packed));
390 /* AHB subsystem CSR registers */
391 struct udc_regs {
393 /* device configuration */
394 u32 cfg;
396 /* device control */
397 u32 ctl;
399 /* device status */
400 u32 sts;
402 /* device interrupt */
403 u32 irqsts;
405 /* device interrupt mask */
406 u32 irqmsk;
408 /* endpoint interrupt */
409 u32 ep_irqsts;
411 /* endpoint interrupt mask */
412 u32 ep_irqmsk;
413 } __attribute__ ((packed));
415 /* endpoint specific registers */
416 struct udc_ep_regs {
418 /* endpoint control */
419 u32 ctl;
421 /* endpoint status */
422 u32 sts;
424 /* endpoint buffer size in/ receive packet frame number out */
425 u32 bufin_framenum;
427 /* endpoint buffer size out/max packet size */
428 u32 bufout_maxpkt;
430 /* endpoint setup buffer pointer */
431 u32 subptr;
433 /* endpoint data descriptor pointer */
434 u32 desptr;
436 /* reserverd */
437 u32 reserved;
439 /* write/read confirmation */
440 u32 confirm;
442 } __attribute__ ((packed));
444 /* control data DMA desc */
445 struct udc_stp_dma {
446 /* status quadlet */
447 u32 status;
448 /* reserved */
449 u32 _reserved;
450 /* first setup word */
451 u32 data12;
452 /* second setup word */
453 u32 data34;
454 } __attribute__ ((aligned (16)));
456 /* normal data DMA desc */
457 struct udc_data_dma {
458 /* status quadlet */
459 u32 status;
460 /* reserved */
461 u32 _reserved;
462 /* buffer pointer */
463 u32 bufptr;
464 /* next descriptor pointer */
465 u32 next;
466 } __attribute__ ((aligned (16)));
468 /* request packet */
469 struct udc_request {
470 /* embedded gadget ep */
471 struct usb_request req;
473 /* flags */
474 unsigned dma_going : 1,
475 dma_mapping : 1,
476 dma_done : 1;
477 /* phys. address */
478 dma_addr_t td_phys;
479 /* first dma desc. of chain */
480 struct udc_data_dma *td_data;
481 /* last dma desc. of chain */
482 struct udc_data_dma *td_data_last;
483 struct list_head queue;
485 /* chain length */
486 unsigned chain_len;
490 /* UDC specific endpoint parameters */
491 struct udc_ep {
492 struct usb_ep ep;
493 struct udc_ep_regs __iomem *regs;
494 u32 __iomem *txfifo;
495 u32 __iomem *dma;
496 dma_addr_t td_phys;
497 dma_addr_t td_stp_dma;
498 struct udc_stp_dma *td_stp;
499 struct udc_data_dma *td;
500 /* temp request */
501 struct udc_request *req;
502 unsigned req_used;
503 unsigned req_completed;
504 /* dummy DMA desc for BNA dummy */
505 struct udc_request *bna_dummy_req;
506 unsigned bna_occurred;
508 /* NAK state */
509 unsigned naking;
511 struct udc *dev;
513 /* queue for requests */
514 struct list_head queue;
515 const struct usb_endpoint_descriptor *desc;
516 unsigned halted;
517 unsigned cancel_transfer;
518 unsigned num : 5,
519 fifo_depth : 14,
520 in : 1;
523 /* device struct */
524 struct udc {
525 struct usb_gadget gadget;
526 spinlock_t lock; /* protects all state */
527 /* all endpoints */
528 struct udc_ep ep[UDC_EP_NUM];
529 struct usb_gadget_driver *driver;
530 /* operational flags */
531 unsigned active : 1,
532 stall_ep0in : 1,
533 waiting_zlp_ack_ep0in : 1,
534 set_cfg_not_acked : 1,
535 irq_registered : 1,
536 data_ep_enabled : 1,
537 data_ep_queued : 1,
538 mem_region : 1,
539 sys_suspended : 1,
540 connected;
542 u16 chiprev;
544 /* registers */
545 struct pci_dev *pdev;
546 struct udc_csrs __iomem *csr;
547 struct udc_regs __iomem *regs;
548 struct udc_ep_regs __iomem *ep_regs;
549 u32 __iomem *rxfifo;
550 u32 __iomem *txfifo;
552 /* DMA desc pools */
553 struct pci_pool *data_requests;
554 struct pci_pool *stp_requests;
556 /* device data */
557 unsigned long phys_addr;
558 void __iomem *virt_addr;
559 unsigned irq;
561 /* states */
562 u16 cur_config;
563 u16 cur_intf;
564 u16 cur_alt;
567 /* setup request data */
568 union udc_setup_data {
569 u32 data[2];
570 struct usb_ctrlrequest request;
574 *---------------------------------------------------------------------------
575 * SET and GET bitfields in u32 values
576 * via constants for mask/offset:
577 * <bit_field_stub_name> is the text between
578 * UDC_ and _MASK|_OFS of appropriate
579 * constant
581 * set bitfield value in u32 u32Val
583 #define AMD_ADDBITS(u32Val, bitfield_val, bitfield_stub_name) \
584 (((u32Val) & (((u32) ~((u32) bitfield_stub_name##_MASK)))) \
585 | (((bitfield_val) << ((u32) bitfield_stub_name##_OFS)) \
586 & ((u32) bitfield_stub_name##_MASK)))
589 * set bitfield value in zero-initialized u32 u32Val
590 * => bitfield bits in u32Val are all zero
592 #define AMD_INIT_SETBITS(u32Val, bitfield_val, bitfield_stub_name) \
593 ((u32Val) \
594 | (((bitfield_val) << ((u32) bitfield_stub_name##_OFS)) \
595 & ((u32) bitfield_stub_name##_MASK)))
597 /* get bitfield value from u32 u32Val */
598 #define AMD_GETBITS(u32Val, bitfield_stub_name) \
599 ((u32Val & ((u32) bitfield_stub_name##_MASK)) \
600 >> ((u32) bitfield_stub_name##_OFS))
602 /* SET and GET bits in u32 values ------------------------------------------*/
603 #define AMD_BIT(bit_stub_name) (1 << bit_stub_name)
604 #define AMD_UNMASK_BIT(bit_stub_name) (~AMD_BIT(bit_stub_name))
605 #define AMD_CLEAR_BIT(bit_stub_name) (~AMD_BIT(bit_stub_name))
607 /* debug macros ------------------------------------------------------------*/
609 #define DBG(udc , args...) dev_dbg(&(udc)->pdev->dev, args)
611 #ifdef UDC_VERBOSE
612 #define VDBG DBG
613 #else
614 #define VDBG(udc , args...) do {} while (0)
615 #endif
617 #endif /* #ifdef AMD5536UDC_H */