include/drm/drm_dp_helper.h

   1 /*
   2  * Copyright © 2008 Keith Packard
   3  *
   4  * Permission to use, copy, modify, distribute, and sell this software and its
   5  * documentation for any purpose is hereby granted without fee, provided that
   6  * the above copyright notice appear in all copies and that both that copyright
   7  * notice and this permission notice appear in supporting documentation, and
   8  * that the name of the copyright holders not be used in advertising or
   9  * publicity pertaining to distribution of the software without specific,
  10  * written prior permission.  The copyright holders make no representations
  11  * about the suitability of this software for any purpose.  It is provided "as
  12  * is" without express or implied warranty.
  13  *
  14  * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
  15  * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
  16  * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
  17  * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
  18  * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  19  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
  20  * OF THIS SOFTWARE.
  21  */
  22
  23 #ifndef _DRM_DP_HELPER_H_
  24 #define _DRM_DP_HELPER_H_
  25
  26 #include <linux/types.h>
  27 #include <linux/i2c.h>
  28
  29 /* From the VESA DisplayPort spec */
  30
  31 #define AUX_NATIVE_WRITE        0x8
  32 #define AUX_NATIVE_READ         0x9
  33 #define AUX_I2C_WRITE           0x0
  34 #define AUX_I2C_READ            0x1
  35 #define AUX_I2C_STATUS          0x2
  36 #define AUX_I2C_MOT             0x4
  37
  38 #define AUX_NATIVE_REPLY_ACK    (0x0 << 4)
  39 #define AUX_NATIVE_REPLY_NACK   (0x1 << 4)
  40 #define AUX_NATIVE_REPLY_DEFER  (0x2 << 4)
  41 #define AUX_NATIVE_REPLY_MASK   (0x3 << 4)
  42
  43 #define AUX_I2C_REPLY_ACK       (0x0 << 6)
  44 #define AUX_I2C_REPLY_NACK      (0x1 << 6)
  45 #define AUX_I2C_REPLY_DEFER     (0x2 << 6)
  46 #define AUX_I2C_REPLY_MASK      (0x3 << 6)
  47
  48 /* AUX CH addresses */
  49 /* DPCD */
  50 #define DP_DPCD_REV                         0x000
  51
  52 #define DP_MAX_LINK_RATE                    0x001
  53
  54 #define DP_MAX_LANE_COUNT                   0x002
  55 # define DP_MAX_LANE_COUNT_MASK             0x1f
  56 # define DP_TPS3_SUPPORTED                  (1 << 6)
  57 # define DP_ENHANCED_FRAME_CAP              (1 << 7)
  58
  59 #define DP_MAX_DOWNSPREAD                   0x003
  60 # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING  (1 << 6)
  61
  62 #define DP_NORP                             0x004
  63
  64 #define DP_DOWNSTREAMPORT_PRESENT           0x005
  65 # define DP_DWN_STRM_PORT_PRESENT           (1 << 0)
  66 # define DP_DWN_STRM_PORT_TYPE_MASK         0x06
  67 /* 00b = DisplayPort */
  68 /* 01b = Analog */
  69 /* 10b = TMDS or HDMI */
  70 /* 11b = Other */
  71 # define DP_FORMAT_CONVERSION               (1 << 3)
  72
  73 #define DP_MAIN_LINK_CHANNEL_CODING         0x006
  74
  75 #define DP_EDP_CONFIGURATION_CAP            0x00d
  76 #define DP_TRAINING_AUX_RD_INTERVAL         0x00e
  77
  78 #define DP_PSR_SUPPORT                      0x070
  79 # define DP_PSR_IS_SUPPORTED                1
  80 #define DP_PSR_CAPS                         0x071
  81 # define DP_PSR_NO_TRAIN_ON_EXIT            1
  82 # define DP_PSR_SETUP_TIME_330              (0 << 1)
  83 # define DP_PSR_SETUP_TIME_275              (1 << 1)
  84 # define DP_PSR_SETUP_TIME_220              (2 << 1)
  85 # define DP_PSR_SETUP_TIME_165              (3 << 1)
  86 # define DP_PSR_SETUP_TIME_110              (4 << 1)
  87 # define DP_PSR_SETUP_TIME_55               (5 << 1)
  88 # define DP_PSR_SETUP_TIME_0                (6 << 1)
  89 # define DP_PSR_SETUP_TIME_MASK             (7 << 1)
  90 # define DP_PSR_SETUP_TIME_SHIFT            1
  91
  92 /* link configuration */
  93 #define DP_LINK_BW_SET                      0x100
  94 # define DP_LINK_BW_1_62                    0x06
  95 # define DP_LINK_BW_2_7                     0x0a
  96 # define DP_LINK_BW_5_4                     0x14
  97
  98 #define DP_LANE_COUNT_SET                   0x101
  99 # define DP_LANE_COUNT_MASK                 0x0f
 100 # define DP_LANE_COUNT_ENHANCED_FRAME_EN    (1 << 7)
 101
 102 #define DP_TRAINING_PATTERN_SET             0x102
 103 # define DP_TRAINING_PATTERN_DISABLE        0
 104 # define DP_TRAINING_PATTERN_1              1
 105 # define DP_TRAINING_PATTERN_2              2
 106 # define DP_TRAINING_PATTERN_3              3
 107 # define DP_TRAINING_PATTERN_MASK           0x3
 108
 109 # define DP_LINK_QUAL_PATTERN_DISABLE       (0 << 2)
 110 # define DP_LINK_QUAL_PATTERN_D10_2         (1 << 2)
 111 # define DP_LINK_QUAL_PATTERN_ERROR_RATE    (2 << 2)
 112 # define DP_LINK_QUAL_PATTERN_PRBS7         (3 << 2)
 113 # define DP_LINK_QUAL_PATTERN_MASK          (3 << 2)
 114
 115 # define DP_RECOVERED_CLOCK_OUT_EN          (1 << 4)
 116 # define DP_LINK_SCRAMBLING_DISABLE         (1 << 5)
 117
 118 # define DP_SYMBOL_ERROR_COUNT_BOTH         (0 << 6)
 119 # define DP_SYMBOL_ERROR_COUNT_DISPARITY    (1 << 6)
 120 # define DP_SYMBOL_ERROR_COUNT_SYMBOL       (2 << 6)
 121 # define DP_SYMBOL_ERROR_COUNT_MASK         (3 << 6)
 122
 123 #define DP_TRAINING_LANE0_SET               0x103
 124 #define DP_TRAINING_LANE1_SET               0x104
 125 #define DP_TRAINING_LANE2_SET               0x105
 126 #define DP_TRAINING_LANE3_SET               0x106
 127
 128 # define DP_TRAIN_VOLTAGE_SWING_MASK        0x3
 129 # define DP_TRAIN_VOLTAGE_SWING_SHIFT       0
 130 # define DP_TRAIN_MAX_SWING_REACHED         (1 << 2)
 131 # define DP_TRAIN_VOLTAGE_SWING_400         (0 << 0)
 132 # define DP_TRAIN_VOLTAGE_SWING_600         (1 << 0)
 133 # define DP_TRAIN_VOLTAGE_SWING_800         (2 << 0)
 134 # define DP_TRAIN_VOLTAGE_SWING_1200        (3 << 0)
 135
 136 # define DP_TRAIN_PRE_EMPHASIS_MASK         (3 << 3)
 137 # define DP_TRAIN_PRE_EMPHASIS_0            (0 << 3)
 138 # define DP_TRAIN_PRE_EMPHASIS_3_5          (1 << 3)
 139 # define DP_TRAIN_PRE_EMPHASIS_6            (2 << 3)
 140 # define DP_TRAIN_PRE_EMPHASIS_9_5          (3 << 3)
 141
 142 # define DP_TRAIN_PRE_EMPHASIS_SHIFT        3
 143 # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED  (1 << 5)
 144
 145 #define DP_DOWNSPREAD_CTRL                  0x107
 146 # define DP_SPREAD_AMP_0_5                  (1 << 4)
 147
 148 #define DP_MAIN_LINK_CHANNEL_CODING_SET     0x108
 149 # define DP_SET_ANSI_8B10B                  (1 << 0)
 150
 151 #define DP_PSR_EN_CFG                       0x170
 152 # define DP_PSR_ENABLE                      (1 << 0)
 153 # define DP_PSR_MAIN_LINK_ACTIVE            (1 << 1)
 154 # define DP_PSR_CRC_VERIFICATION            (1 << 2)
 155 # define DP_PSR_FRAME_CAPTURE               (1 << 3)
 156
 157 #define DP_DEVICE_SERVICE_IRQ_VECTOR        0x201
 158 # define DP_REMOTE_CONTROL_COMMAND_PENDING  (1 << 0)
 159 # define DP_AUTOMATED_TEST_REQUEST          (1 << 1)
 160 # define DP_CP_IRQ                          (1 << 2)
 161 # define DP_SINK_SPECIFIC_IRQ               (1 << 6)
 162
 163 #define DP_EDP_CONFIGURATION_SET            0x10a
 164
 165 #define DP_LANE0_1_STATUS                   0x202
 166 #define DP_LANE2_3_STATUS                   0x203
 167 # define DP_LANE_CR_DONE                    (1 << 0)
 168 # define DP_LANE_CHANNEL_EQ_DONE            (1 << 1)
 169 # define DP_LANE_SYMBOL_LOCKED              (1 << 2)
 170
 171 #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE |           \
 172                             DP_LANE_CHANNEL_EQ_DONE |   \
 173                             DP_LANE_SYMBOL_LOCKED)
 174
 175 #define DP_LANE_ALIGN_STATUS_UPDATED        0x204
 176
 177 #define DP_INTERLANE_ALIGN_DONE             (1 << 0)
 178 #define DP_DOWNSTREAM_PORT_STATUS_CHANGED   (1 << 6)
 179 #define DP_LINK_STATUS_UPDATED              (1 << 7)
 180
 181 #define DP_SINK_STATUS                      0x205
 182
 183 #define DP_RECEIVE_PORT_0_STATUS            (1 << 0)
 184 #define DP_RECEIVE_PORT_1_STATUS            (1 << 1)
 185
 186 #define DP_ADJUST_REQUEST_LANE0_1           0x206
 187 #define DP_ADJUST_REQUEST_LANE2_3           0x207
 188 # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK  0x03
 189 # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
 190 # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK   0x0c
 191 # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT  2
 192 # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK  0x30
 193 # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
 194 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK   0xc0
 195 # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT  6
 196
 197 #define DP_TEST_REQUEST                     0x218
 198 # define DP_TEST_LINK_TRAINING              (1 << 0)
 199 # define DP_TEST_LINK_PATTERN               (1 << 1)
 200 # define DP_TEST_LINK_EDID_READ             (1 << 2)
 201 # define DP_TEST_LINK_PHY_TEST_PATTERN      (1 << 3) /* DPCD >= 1.1 */
 202
 203 #define DP_TEST_LINK_RATE                   0x219
 204 # define DP_LINK_RATE_162                   (0x6)
 205 # define DP_LINK_RATE_27                    (0xa)
 206
 207 #define DP_TEST_LANE_COUNT                  0x220
 208
 209 #define DP_TEST_PATTERN                     0x221
 210
 211 #define DP_TEST_RESPONSE                    0x260
 212 # define DP_TEST_ACK                        (1 << 0)
 213 # define DP_TEST_NAK                        (1 << 1)
 214 # define DP_TEST_EDID_CHECKSUM_WRITE        (1 << 2)
 215
 216 #define DP_SET_POWER                        0x600
 217 # define DP_SET_POWER_D0                    0x1
 218 # define DP_SET_POWER_D3                    0x2
 219
 220 #define DP_PSR_ERROR_STATUS                 0x2006
 221 # define DP_PSR_LINK_CRC_ERROR              (1 << 0)
 222 # define DP_PSR_RFB_STORAGE_ERROR           (1 << 1)
 223
 224 #define DP_PSR_ESI                          0x2007
 225 # define DP_PSR_CAPS_CHANGE                 (1 << 0)
 226
 227 #define DP_PSR_STATUS                       0x2008
 228 # define DP_PSR_SINK_INACTIVE               0
 229 # define DP_PSR_SINK_ACTIVE_SRC_SYNCED      1
 230 # define DP_PSR_SINK_ACTIVE_RFB             2
 231 # define DP_PSR_SINK_ACTIVE_SINK_SYNCED     3
 232 # define DP_PSR_SINK_ACTIVE_RESYNC          4
 233 # define DP_PSR_SINK_INTERNAL_ERROR         7
 234 # define DP_PSR_SINK_STATE_MASK             0x07
 235
 236 #define MODE_I2C_START  1
 237 #define MODE_I2C_WRITE  2
 238 #define MODE_I2C_READ   4
 239 #define MODE_I2C_STOP   8
 240
 241 struct i2c_algo_dp_aux_data {
 242         bool running;
 243         u16 address;
 244         int (*aux_ch) (struct i2c_adapter *adapter,
 245                        int mode, uint8_t write_byte,
 246                        uint8_t *read_byte);
 247 };
 248
 249 int
 250 i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
 251
 252 #endif /* _DRM_DP_HELPER_H_ */