drivers/scsi/bfa/bfa_ioc_cb.c

   1 /*
   2  * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
   3  * All rights reserved
   4  * www.brocade.com
   5  *
   6  * Linux driver for Brocade Fibre Channel Host Bus Adapter.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License (GPL) Version 2 as
  10  * published by the Free Software Foundation
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  */
  17
  18 #include "bfad_drv.h"
  19 #include "bfa_ioc.h"
  20 #include "bfi_cbreg.h"
  21 #include "bfa_defs.h"
  22
  23 BFA_TRC_FILE(CNA, IOC_CB);
  24
  25 /*
  26  * forward declarations
  27  */
  28 static bfa_boolean_t bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc);
  29 static void bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc);
  30 static void bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc);
  31 static void bfa_ioc_cb_map_port(struct bfa_ioc_s *ioc);
  32 static void bfa_ioc_cb_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix);
  33 static void bfa_ioc_cb_notify_fail(struct bfa_ioc_s *ioc);
  34 static void bfa_ioc_cb_ownership_reset(struct bfa_ioc_s *ioc);
  35 static void bfa_ioc_cb_sync_join(struct bfa_ioc_s *ioc);
  36 static void bfa_ioc_cb_sync_leave(struct bfa_ioc_s *ioc);
  37 static void bfa_ioc_cb_sync_ack(struct bfa_ioc_s *ioc);
  38 static bfa_boolean_t bfa_ioc_cb_sync_complete(struct bfa_ioc_s *ioc);
  39
  40 static struct bfa_ioc_hwif_s hwif_cb;
  41
  42 /*
  43  * Called from bfa_ioc_attach() to map asic specific calls.
  44  */
  45 void
  46 bfa_ioc_set_cb_hwif(struct bfa_ioc_s *ioc)
  47 {
  48         hwif_cb.ioc_pll_init = bfa_ioc_cb_pll_init;
  49         hwif_cb.ioc_firmware_lock = bfa_ioc_cb_firmware_lock;
  50         hwif_cb.ioc_firmware_unlock = bfa_ioc_cb_firmware_unlock;
  51         hwif_cb.ioc_reg_init = bfa_ioc_cb_reg_init;
  52         hwif_cb.ioc_map_port = bfa_ioc_cb_map_port;
  53         hwif_cb.ioc_isr_mode_set = bfa_ioc_cb_isr_mode_set;
  54         hwif_cb.ioc_notify_fail = bfa_ioc_cb_notify_fail;
  55         hwif_cb.ioc_ownership_reset = bfa_ioc_cb_ownership_reset;
  56         hwif_cb.ioc_sync_join = bfa_ioc_cb_sync_join;
  57         hwif_cb.ioc_sync_leave = bfa_ioc_cb_sync_leave;
  58         hwif_cb.ioc_sync_ack = bfa_ioc_cb_sync_ack;
  59         hwif_cb.ioc_sync_complete = bfa_ioc_cb_sync_complete;
  60
  61         ioc->ioc_hwif = &hwif_cb;
  62 }
  63
  64 /*
  65  * Return true if firmware of current driver matches the running firmware.
  66  */
  67 static bfa_boolean_t
  68 bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc)
  69 {
  70         struct bfi_ioc_image_hdr_s fwhdr;
  71         uint32_t fwstate = readl(ioc->ioc_regs.ioc_fwstate);
  72
  73         if (fwstate == BFI_IOC_UNINIT)
  74                 return BFA_TRUE;
  75
  76         bfa_ioc_fwver_get(ioc, &fwhdr);
  77
  78         if (swab32(fwhdr.exec) == BFI_BOOT_TYPE_NORMAL)
  79                 return BFA_TRUE;
  80
  81         bfa_trc(ioc, fwstate);
  82         bfa_trc(ioc, fwhdr.exec);
  83         writel(BFI_IOC_UNINIT, ioc->ioc_regs.ioc_fwstate);
  84
  85         return BFA_TRUE;
  86 }
  87
  88 static void
  89 bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc)
  90 {
  91 }
  92
  93 /*
  94  * Notify other functions on HB failure.
  95  */
  96 static void
  97 bfa_ioc_cb_notify_fail(struct bfa_ioc_s *ioc)
  98 {
  99         writel(__PSS_ERR_STATUS_SET, ioc->ioc_regs.err_set);
 100         readl(ioc->ioc_regs.err_set);
 101 }
 102
 103 /*
 104  * Host to LPU mailbox message addresses
 105  */
 106 static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = {
 107         { HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 },
 108         { HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 }
 109 };
 110
 111 /*
 112  * Host <-> LPU mailbox command/status registers
 113  */
 114 static struct { u32 hfn, lpu; } iocreg_mbcmd[] = {
 115
 116         { HOSTFN0_LPU0_CMD_STAT, LPU0_HOSTFN0_CMD_STAT },
 117         { HOSTFN1_LPU1_CMD_STAT, LPU1_HOSTFN1_CMD_STAT }
 118 };
 119
 120 static void
 121 bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc)
 122 {
 123         void __iomem *rb;
 124         int             pcifn = bfa_ioc_pcifn(ioc);
 125
 126         rb = bfa_ioc_bar0(ioc);
 127
 128         ioc->ioc_regs.hfn_mbox = rb + iocreg_fnreg[pcifn].hfn_mbox;
 129         ioc->ioc_regs.lpu_mbox = rb + iocreg_fnreg[pcifn].lpu_mbox;
 130         ioc->ioc_regs.host_page_num_fn = rb + iocreg_fnreg[pcifn].hfn_pgn;
 131
 132         if (ioc->port_id == 0) {
 133                 ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG;
 134                 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG;
 135                 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC1_STATE_REG;
 136         } else {
 137                 ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG);
 138                 ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG);
 139                 ioc->ioc_regs.alt_ioc_fwstate = (rb + BFA_IOC0_STATE_REG);
 140         }
 141
 142         /*
 143          * Host <-> LPU mailbox command/status registers
 144          */
 145         ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd[pcifn].hfn;
 146         ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd[pcifn].lpu;
 147
 148         /*
 149          * PSS control registers
 150          */
 151         ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG);
 152         ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG);
 153         ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_400_CTL_REG);
 154         ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_212_CTL_REG);
 155
 156         /*
 157          * IOC semaphore registers and serialization
 158          */
 159         ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG);
 160         ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG);
 161
 162         /*
 163          * sram memory access
 164          */
 165         ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START);
 166         ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CB;
 167
 168         /*
 169          * err set reg : for notification of hb failure
 170          */
 171         ioc->ioc_regs.err_set = (rb + ERR_SET_REG);
 172 }
 173
 174 /*
 175  * Initialize IOC to port mapping.
 176  */
 177
 178 static void
 179 bfa_ioc_cb_map_port(struct bfa_ioc_s *ioc)
 180 {
 181         /*
 182          * For crossbow, port id is same as pci function.
 183          */
 184         ioc->port_id = bfa_ioc_pcifn(ioc);
 185
 186         bfa_trc(ioc, ioc->port_id);
 187 }
 188
 189 /*
 190  * Set interrupt mode for a function: INTX or MSIX
 191  */
 192 static void
 193 bfa_ioc_cb_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix)
 194 {
 195 }
 196
 197 /*
 198  * Cleanup hw semaphore and usecnt registers
 199  */
 200 static void
 201 bfa_ioc_cb_ownership_reset(struct bfa_ioc_s *ioc)
 202 {
 203
 204         /*
 205          * Read the hw sem reg to make sure that it is locked
 206          * before we clear it. If it is not locked, writing 1
 207          * will lock it instead of clearing it.
 208          */
 209         readl(ioc->ioc_regs.ioc_sem_reg);
 210         writel(1, ioc->ioc_regs.ioc_sem_reg);
 211 }
 212
 213 /*
 214  * Synchronized IOC failure processing routines
 215  */
 216 static void
 217 bfa_ioc_cb_sync_join(struct bfa_ioc_s *ioc)
 218 {
 219 }
 220
 221 static void
 222 bfa_ioc_cb_sync_leave(struct bfa_ioc_s *ioc)
 223 {
 224 }
 225
 226 static void
 227 bfa_ioc_cb_sync_ack(struct bfa_ioc_s *ioc)
 228 {
 229         writel(BFI_IOC_FAIL, ioc->ioc_regs.ioc_fwstate);
 230 }
 231
 232 static bfa_boolean_t
 233 bfa_ioc_cb_sync_complete(struct bfa_ioc_s *ioc)
 234 {
 235         uint32_t fwstate, alt_fwstate;
 236         fwstate = readl(ioc->ioc_regs.ioc_fwstate);
 237
 238         /*
 239          * At this point, this IOC is hoding the hw sem in the
 240          * start path (fwcheck) OR in the disable/enable path
 241          * OR to check if the other IOC has acknowledged failure.
 242          *
 243          * So, this IOC can be in UNINIT, INITING, DISABLED, FAIL
 244          * or in MEMTEST states. In a normal scenario, this IOC
 245          * can not be in OP state when this function is called.
 246          *
 247          * However, this IOC could still be in OP state when
 248          * the OS driver is starting up, if the OptROM code has
 249          * left it in that state.
 250          *
 251          * If we had marked this IOC's fwstate as BFI_IOC_FAIL
 252          * in the failure case and now, if the fwstate is not
 253          * BFI_IOC_FAIL it implies that the other PCI fn have
 254          * reinitialized the ASIC or this IOC got disabled, so
 255          * return TRUE.
 256          */
 257         if (fwstate == BFI_IOC_UNINIT ||
 258                 fwstate == BFI_IOC_INITING ||
 259                 fwstate == BFI_IOC_DISABLED ||
 260                 fwstate == BFI_IOC_MEMTEST ||
 261                 fwstate == BFI_IOC_OP)
 262                 return BFA_TRUE;
 263         else {
 264                 alt_fwstate = readl(ioc->ioc_regs.alt_ioc_fwstate);
 265                 if (alt_fwstate == BFI_IOC_FAIL ||
 266                         alt_fwstate == BFI_IOC_DISABLED ||
 267                         alt_fwstate == BFI_IOC_UNINIT ||
 268                         alt_fwstate == BFI_IOC_INITING ||
 269                         alt_fwstate == BFI_IOC_MEMTEST)
 270                         return BFA_TRUE;
 271                 else
 272                         return BFA_FALSE;
 273         }
 274 }
 275
 276 bfa_status_t
 277 bfa_ioc_cb_pll_init(void __iomem *rb, bfa_boolean_t fcmode)
 278 {
 279         u32     pll_sclk, pll_fclk;
 280
 281         pll_sclk = __APP_PLL_212_ENABLE | __APP_PLL_212_LRESETN |
 282                 __APP_PLL_212_P0_1(3U) |
 283                 __APP_PLL_212_JITLMT0_1(3U) |
 284                 __APP_PLL_212_CNTLMT0_1(3U);
 285         pll_fclk = __APP_PLL_400_ENABLE | __APP_PLL_400_LRESETN |
 286                 __APP_PLL_400_RSEL200500 | __APP_PLL_400_P0_1(3U) |
 287                 __APP_PLL_400_JITLMT0_1(3U) |
 288                 __APP_PLL_400_CNTLMT0_1(3U);
 289         writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG));
 290         writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG));
 291         writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
 292         writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
 293         writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
 294         writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
 295         writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
 296         writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
 297         writel(__APP_PLL_212_LOGIC_SOFT_RESET, rb + APP_PLL_212_CTL_REG);
 298         writel(__APP_PLL_212_BYPASS | __APP_PLL_212_LOGIC_SOFT_RESET,
 299                         rb + APP_PLL_212_CTL_REG);
 300         writel(__APP_PLL_400_LOGIC_SOFT_RESET, rb + APP_PLL_400_CTL_REG);
 301         writel(__APP_PLL_400_BYPASS | __APP_PLL_400_LOGIC_SOFT_RESET,
 302                         rb + APP_PLL_400_CTL_REG);
 303         udelay(2);
 304         writel(__APP_PLL_212_LOGIC_SOFT_RESET, rb + APP_PLL_212_CTL_REG);
 305         writel(__APP_PLL_400_LOGIC_SOFT_RESET, rb + APP_PLL_400_CTL_REG);
 306         writel(pll_sclk | __APP_PLL_212_LOGIC_SOFT_RESET,
 307                         rb + APP_PLL_212_CTL_REG);
 308         writel(pll_fclk | __APP_PLL_400_LOGIC_SOFT_RESET,
 309                         rb + APP_PLL_400_CTL_REG);
 310         udelay(2000);
 311         writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
 312         writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
 313         writel(pll_sclk, (rb + APP_PLL_212_CTL_REG));
 314         writel(pll_fclk, (rb + APP_PLL_400_CTL_REG));
 315
 316         return BFA_STATUS_OK;
 317 }