drivers/scsi/bfa/bfi_cbreg.h

   1
   2 /*
   3  * bfi_cbreg.h crossbow host block register definitions
   4  *
   5  * !!! Do not edit. Auto generated. !!!
   6  */
   7
   8 #ifndef __BFI_CBREG_H__
   9 #define __BFI_CBREG_H__
  10
  11
  12 #define HOSTFN0_INT_STATUS               0x00014000
  13 #define __HOSTFN0_INT_STATUS_LVL_MK      0x00f00000
  14 #define __HOSTFN0_INT_STATUS_LVL_SH      20
  15 #define __HOSTFN0_INT_STATUS_LVL(_v)     ((_v) << __HOSTFN0_INT_STATUS_LVL_SH)
  16 #define __HOSTFN0_INT_STATUS_P           0x000fffff
  17 #define HOSTFN0_INT_MSK                  0x00014004
  18 #define HOST_PAGE_NUM_FN0                0x00014008
  19 #define __HOST_PAGE_NUM_FN               0x000001ff
  20 #define HOSTFN1_INT_STATUS               0x00014100
  21 #define __HOSTFN1_INT_STAT_LVL_MK        0x00f00000
  22 #define __HOSTFN1_INT_STAT_LVL_SH        20
  23 #define __HOSTFN1_INT_STAT_LVL(_v)       ((_v) << __HOSTFN1_INT_STAT_LVL_SH)
  24 #define __HOSTFN1_INT_STAT_P             0x000fffff
  25 #define HOSTFN1_INT_MSK                  0x00014104
  26 #define HOST_PAGE_NUM_FN1                0x00014108
  27 #define APP_PLL_400_CTL_REG              0x00014204
  28 #define __P_400_PLL_LOCK                 0x80000000
  29 #define __APP_PLL_400_SRAM_USE_100MHZ    0x00100000
  30 #define __APP_PLL_400_RESET_TIMER_MK     0x000e0000
  31 #define __APP_PLL_400_RESET_TIMER_SH     17
  32 #define __APP_PLL_400_RESET_TIMER(_v)    ((_v) << __APP_PLL_400_RESET_TIMER_SH)
  33 #define __APP_PLL_400_LOGIC_SOFT_RESET   0x00010000
  34 #define __APP_PLL_400_CNTLMT0_1_MK       0x0000c000
  35 #define __APP_PLL_400_CNTLMT0_1_SH       14
  36 #define __APP_PLL_400_CNTLMT0_1(_v)      ((_v) << __APP_PLL_400_CNTLMT0_1_SH)
  37 #define __APP_PLL_400_JITLMT0_1_MK       0x00003000
  38 #define __APP_PLL_400_JITLMT0_1_SH       12
  39 #define __APP_PLL_400_JITLMT0_1(_v)      ((_v) << __APP_PLL_400_JITLMT0_1_SH)
  40 #define __APP_PLL_400_HREF               0x00000800
  41 #define __APP_PLL_400_HDIV               0x00000400
  42 #define __APP_PLL_400_P0_1_MK            0x00000300
  43 #define __APP_PLL_400_P0_1_SH            8
  44 #define __APP_PLL_400_P0_1(_v)           ((_v) << __APP_PLL_400_P0_1_SH)
  45 #define __APP_PLL_400_Z0_2_MK            0x000000e0
  46 #define __APP_PLL_400_Z0_2_SH            5
  47 #define __APP_PLL_400_Z0_2(_v)           ((_v) << __APP_PLL_400_Z0_2_SH)
  48 #define __APP_PLL_400_RSEL200500         0x00000010
  49 #define __APP_PLL_400_ENARST             0x00000008
  50 #define __APP_PLL_400_BYPASS             0x00000004
  51 #define __APP_PLL_400_LRESETN            0x00000002
  52 #define __APP_PLL_400_ENABLE             0x00000001
  53 #define APP_PLL_212_CTL_REG              0x00014208
  54 #define __P_212_PLL_LOCK                 0x80000000
  55 #define __APP_PLL_212_RESET_TIMER_MK     0x000e0000
  56 #define __APP_PLL_212_RESET_TIMER_SH     17
  57 #define __APP_PLL_212_RESET_TIMER(_v)    ((_v) << __APP_PLL_212_RESET_TIMER_SH)
  58 #define __APP_PLL_212_LOGIC_SOFT_RESET   0x00010000
  59 #define __APP_PLL_212_CNTLMT0_1_MK       0x0000c000
  60 #define __APP_PLL_212_CNTLMT0_1_SH       14
  61 #define __APP_PLL_212_CNTLMT0_1(_v)      ((_v) << __APP_PLL_212_CNTLMT0_1_SH)
  62 #define __APP_PLL_212_JITLMT0_1_MK       0x00003000
  63 #define __APP_PLL_212_JITLMT0_1_SH       12
  64 #define __APP_PLL_212_JITLMT0_1(_v)      ((_v) << __APP_PLL_212_JITLMT0_1_SH)
  65 #define __APP_PLL_212_HREF               0x00000800
  66 #define __APP_PLL_212_HDIV               0x00000400
  67 #define __APP_PLL_212_P0_1_MK            0x00000300
  68 #define __APP_PLL_212_P0_1_SH            8
  69 #define __APP_PLL_212_P0_1(_v)           ((_v) << __APP_PLL_212_P0_1_SH)
  70 #define __APP_PLL_212_Z0_2_MK            0x000000e0
  71 #define __APP_PLL_212_Z0_2_SH            5
  72 #define __APP_PLL_212_Z0_2(_v)           ((_v) << __APP_PLL_212_Z0_2_SH)
  73 #define __APP_PLL_212_RSEL200500         0x00000010
  74 #define __APP_PLL_212_ENARST             0x00000008
  75 #define __APP_PLL_212_BYPASS             0x00000004
  76 #define __APP_PLL_212_LRESETN            0x00000002
  77 #define __APP_PLL_212_ENABLE             0x00000001
  78 #define HOST_SEM0_REG                    0x00014230
  79 #define __HOST_SEMAPHORE                 0x00000001
  80 #define HOST_SEM1_REG                    0x00014234
  81 #define HOST_SEM2_REG                    0x00014238
  82 #define HOST_SEM3_REG                    0x0001423c
  83 #define HOST_SEM0_INFO_REG               0x00014240
  84 #define HOST_SEM1_INFO_REG               0x00014244
  85 #define HOST_SEM2_INFO_REG               0x00014248
  86 #define HOST_SEM3_INFO_REG               0x0001424c
  87 #define HOSTFN0_LPU0_CMD_STAT            0x00019000
  88 #define __HOSTFN0_LPU0_MBOX_INFO_MK      0xfffffffe
  89 #define __HOSTFN0_LPU0_MBOX_INFO_SH      1
  90 #define __HOSTFN0_LPU0_MBOX_INFO(_v)     ((_v) << __HOSTFN0_LPU0_MBOX_INFO_SH)
  91 #define __HOSTFN0_LPU0_MBOX_CMD_STATUS   0x00000001
  92 #define LPU0_HOSTFN0_CMD_STAT            0x00019008
  93 #define __LPU0_HOSTFN0_MBOX_INFO_MK      0xfffffffe
  94 #define __LPU0_HOSTFN0_MBOX_INFO_SH      1
  95 #define __LPU0_HOSTFN0_MBOX_INFO(_v)     ((_v) << __LPU0_HOSTFN0_MBOX_INFO_SH)
  96 #define __LPU0_HOSTFN0_MBOX_CMD_STATUS   0x00000001
  97 #define HOSTFN1_LPU1_CMD_STAT            0x00019014
  98 #define __HOSTFN1_LPU1_MBOX_INFO_MK      0xfffffffe
  99 #define __HOSTFN1_LPU1_MBOX_INFO_SH      1
 100 #define __HOSTFN1_LPU1_MBOX_INFO(_v)     ((_v) << __HOSTFN1_LPU1_MBOX_INFO_SH)
 101 #define __HOSTFN1_LPU1_MBOX_CMD_STATUS   0x00000001
 102 #define LPU1_HOSTFN1_CMD_STAT            0x0001901c
 103 #define __LPU1_HOSTFN1_MBOX_INFO_MK      0xfffffffe
 104 #define __LPU1_HOSTFN1_MBOX_INFO_SH      1
 105 #define __LPU1_HOSTFN1_MBOX_INFO(_v)     ((_v) << __LPU1_HOSTFN1_MBOX_INFO_SH)
 106 #define __LPU1_HOSTFN1_MBOX_CMD_STATUS   0x00000001
 107 #define CPE_Q0_DEPTH                     0x00010014
 108 #define CPE_Q0_PI                        0x0001001c
 109 #define CPE_Q0_CI                        0x00010020
 110 #define CPE_Q1_DEPTH                     0x00010034
 111 #define CPE_Q1_PI                        0x0001003c
 112 #define CPE_Q1_CI                        0x00010040
 113 #define CPE_Q2_DEPTH                     0x00010054
 114 #define CPE_Q2_PI                        0x0001005c
 115 #define CPE_Q2_CI                        0x00010060
 116 #define CPE_Q3_DEPTH                     0x00010074
 117 #define CPE_Q3_PI                        0x0001007c
 118 #define CPE_Q3_CI                        0x00010080
 119 #define CPE_Q4_DEPTH                     0x00010094
 120 #define CPE_Q4_PI                        0x0001009c
 121 #define CPE_Q4_CI                        0x000100a0
 122 #define CPE_Q5_DEPTH                     0x000100b4
 123 #define CPE_Q5_PI                        0x000100bc
 124 #define CPE_Q5_CI                        0x000100c0
 125 #define CPE_Q6_DEPTH                     0x000100d4
 126 #define CPE_Q6_PI                        0x000100dc
 127 #define CPE_Q6_CI                        0x000100e0
 128 #define CPE_Q7_DEPTH                     0x000100f4
 129 #define CPE_Q7_PI                        0x000100fc
 130 #define CPE_Q7_CI                        0x00010100
 131 #define RME_Q0_DEPTH                     0x00011014
 132 #define RME_Q0_PI                        0x0001101c
 133 #define RME_Q0_CI                        0x00011020
 134 #define RME_Q1_DEPTH                     0x00011034
 135 #define RME_Q1_PI                        0x0001103c
 136 #define RME_Q1_CI                        0x00011040
 137 #define RME_Q2_DEPTH                     0x00011054
 138 #define RME_Q2_PI                        0x0001105c
 139 #define RME_Q2_CI                        0x00011060
 140 #define RME_Q3_DEPTH                     0x00011074
 141 #define RME_Q3_PI                        0x0001107c
 142 #define RME_Q3_CI                        0x00011080
 143 #define RME_Q4_DEPTH                     0x00011094
 144 #define RME_Q4_PI                        0x0001109c
 145 #define RME_Q4_CI                        0x000110a0
 146 #define RME_Q5_DEPTH                     0x000110b4
 147 #define RME_Q5_PI                        0x000110bc
 148 #define RME_Q5_CI                        0x000110c0
 149 #define RME_Q6_DEPTH                     0x000110d4
 150 #define RME_Q6_PI                        0x000110dc
 151 #define RME_Q6_CI                        0x000110e0
 152 #define RME_Q7_DEPTH                     0x000110f4
 153 #define RME_Q7_PI                        0x000110fc
 154 #define RME_Q7_CI                        0x00011100
 155 #define PSS_CTL_REG                      0x00018800
 156 #define __PSS_I2C_CLK_DIV_MK             0x00030000
 157 #define __PSS_I2C_CLK_DIV_SH             16
 158 #define __PSS_I2C_CLK_DIV(_v)            ((_v) << __PSS_I2C_CLK_DIV_SH)
 159 #define __PSS_LMEM_INIT_DONE             0x00001000
 160 #define __PSS_LMEM_RESET                 0x00000200
 161 #define __PSS_LMEM_INIT_EN               0x00000100
 162 #define __PSS_LPU1_RESET                 0x00000002
 163 #define __PSS_LPU0_RESET                 0x00000001
 164 #define PSS_ERR_STATUS_REG               0x00018810
 165 #define __PSS_LMEM1_CORR_ERR             0x00000800
 166 #define __PSS_LMEM0_CORR_ERR             0x00000400
 167 #define __PSS_LMEM1_UNCORR_ERR           0x00000200
 168 #define __PSS_LMEM0_UNCORR_ERR           0x00000100
 169 #define __PSS_BAL_PERR                   0x00000080
 170 #define __PSS_DIP_IF_ERR                 0x00000040
 171 #define __PSS_IOH_IF_ERR                 0x00000020
 172 #define __PSS_TDS_IF_ERR                 0x00000010
 173 #define __PSS_RDS_IF_ERR                 0x00000008
 174 #define __PSS_SGM_IF_ERR                 0x00000004
 175 #define __PSS_LPU1_RAM_ERR               0x00000002
 176 #define __PSS_LPU0_RAM_ERR               0x00000001
 177 #define ERR_SET_REG                      0x00018818
 178 #define __PSS_ERR_STATUS_SET             0x00000fff
 179
 180
 181 /*
 182  * These definitions are either in error/missing in spec. Its auto-generated
 183  * from hard coded values in regparse.pl.
 184  */
 185 #define __EMPHPOST_AT_4G_MK_FIX          0x0000001c
 186 #define __EMPHPOST_AT_4G_SH_FIX          0x00000002
 187 #define __EMPHPRE_AT_4G_FIX              0x00000003
 188 #define __SFP_TXRATE_EN_FIX              0x00000100
 189 #define __SFP_RXRATE_EN_FIX              0x00000080
 190
 191
 192 /*
 193  * These register definitions are auto-generated from hard coded values
 194  * in regparse.pl.
 195  */
 196 #define HOSTFN0_LPU_MBOX0_0              0x00019200
 197 #define HOSTFN1_LPU_MBOX0_8              0x00019260
 198 #define LPU_HOSTFN0_MBOX0_0              0x00019280
 199 #define LPU_HOSTFN1_MBOX0_8              0x000192e0
 200
 201
 202 /*
 203  * These register mapping definitions are auto-generated from mapping tables
 204  * in regparse.pl.
 205  */
 206 #define BFA_IOC0_HBEAT_REG               HOST_SEM0_INFO_REG
 207 #define BFA_IOC0_STATE_REG               HOST_SEM1_INFO_REG
 208 #define BFA_IOC1_HBEAT_REG               HOST_SEM2_INFO_REG
 209 #define BFA_IOC1_STATE_REG               HOST_SEM3_INFO_REG
 210 #define BFA_FW_USE_COUNT                 HOST_SEM4_INFO_REG
 211 #define BFA_IOC_FAIL_SYNC                HOST_SEM5_INFO_REG
 212
 213 #define CPE_Q_DEPTH(__n) \
 214         (CPE_Q0_DEPTH + (__n) * (CPE_Q1_DEPTH - CPE_Q0_DEPTH))
 215 #define CPE_Q_PI(__n) \
 216         (CPE_Q0_PI + (__n) * (CPE_Q1_PI - CPE_Q0_PI))
 217 #define CPE_Q_CI(__n) \
 218         (CPE_Q0_CI + (__n) * (CPE_Q1_CI - CPE_Q0_CI))
 219 #define RME_Q_DEPTH(__n) \
 220         (RME_Q0_DEPTH + (__n) * (RME_Q1_DEPTH - RME_Q0_DEPTH))
 221 #define RME_Q_PI(__n) \
 222         (RME_Q0_PI + (__n) * (RME_Q1_PI - RME_Q0_PI))
 223 #define RME_Q_CI(__n) \
 224         (RME_Q0_CI + (__n) * (RME_Q1_CI - RME_Q0_CI))
 225
 226 #define CPE_Q_NUM(__fn, __q)  (((__fn) << 2) + (__q))
 227 #define RME_Q_NUM(__fn, __q)  (((__fn) << 2) + (__q))
 228 #define CPE_Q_MASK(__q)  ((__q) & 0x3)
 229 #define RME_Q_MASK(__q)  ((__q) & 0x3)
 230
 231
 232 /*
 233  * PCI MSI-X vector defines
 234  */
 235 enum {
 236     BFA_MSIX_CPE_Q0 = 0,
 237     BFA_MSIX_CPE_Q1 = 1,
 238     BFA_MSIX_CPE_Q2 = 2,
 239     BFA_MSIX_CPE_Q3 = 3,
 240     BFA_MSIX_CPE_Q4 = 4,
 241     BFA_MSIX_CPE_Q5 = 5,
 242     BFA_MSIX_CPE_Q6 = 6,
 243     BFA_MSIX_CPE_Q7 = 7,
 244     BFA_MSIX_RME_Q0 = 8,
 245     BFA_MSIX_RME_Q1 = 9,
 246     BFA_MSIX_RME_Q2 = 10,
 247     BFA_MSIX_RME_Q3 = 11,
 248     BFA_MSIX_RME_Q4 = 12,
 249     BFA_MSIX_RME_Q5 = 13,
 250     BFA_MSIX_RME_Q6 = 14,
 251     BFA_MSIX_RME_Q7 = 15,
 252     BFA_MSIX_ERR_EMC = 16,
 253     BFA_MSIX_ERR_LPU0 = 17,
 254     BFA_MSIX_ERR_LPU1 = 18,
 255     BFA_MSIX_ERR_PSS = 19,
 256     BFA_MSIX_MBOX_LPU0 = 20,
 257     BFA_MSIX_MBOX_LPU1 = 21,
 258     BFA_MSIX_CB_MAX = 22,
 259 };
 260
 261 /*
 262  * And corresponding host interrupt status bit field defines
 263  */
 264 #define __HFN_INT_CPE_Q0                   0x00000001U
 265 #define __HFN_INT_CPE_Q1                   0x00000002U
 266 #define __HFN_INT_CPE_Q2                   0x00000004U
 267 #define __HFN_INT_CPE_Q3                   0x00000008U
 268 #define __HFN_INT_CPE_Q4                   0x00000010U
 269 #define __HFN_INT_CPE_Q5                   0x00000020U
 270 #define __HFN_INT_CPE_Q6                   0x00000040U
 271 #define __HFN_INT_CPE_Q7                   0x00000080U
 272 #define __HFN_INT_RME_Q0                   0x00000100U
 273 #define __HFN_INT_RME_Q1                   0x00000200U
 274 #define __HFN_INT_RME_Q2                   0x00000400U
 275 #define __HFN_INT_RME_Q3                   0x00000800U
 276 #define __HFN_INT_RME_Q4                   0x00001000U
 277 #define __HFN_INT_RME_Q5                   0x00002000U
 278 #define __HFN_INT_RME_Q6                   0x00004000U
 279 #define __HFN_INT_RME_Q7                   0x00008000U
 280 #define __HFN_INT_ERR_EMC                  0x00010000U
 281 #define __HFN_INT_ERR_LPU0                 0x00020000U
 282 #define __HFN_INT_ERR_LPU1                 0x00040000U
 283 #define __HFN_INT_ERR_PSS                  0x00080000U
 284 #define __HFN_INT_MBOX_LPU0                0x00100000U
 285 #define __HFN_INT_MBOX_LPU1                0x00200000U
 286 #define __HFN_INT_MBOX1_LPU0               0x00400000U
 287 #define __HFN_INT_MBOX1_LPU1               0x00800000U
 288 #define __HFN_INT_CPE_MASK                 0x000000ffU
 289 #define __HFN_INT_RME_MASK                 0x0000ff00U
 290
 291
 292 /*
 293  * crossbow memory map.
 294  */
 295 #define PSS_SMEM_PAGE_START     0x8000
 296 #define PSS_SMEM_PGNUM(_pg0, _ma)       ((_pg0) + ((_ma) >> 15))
 297 #define PSS_SMEM_PGOFF(_ma)     ((_ma) & 0x7fff)
 298
 299 /*
 300  * End of crossbow memory map
 301  */
 302
 303
 304 #endif /* __BFI_CBREG_H__ */
 305