Blackfin: bf548-ezkit/bf561-ezkit: update nor flash layout
[zen-stable.git] / drivers / scsi / sym53c8xx_2 / sym_glue.h
blobb80bf709f104ade623662ea8c646dea308a67818
1 /*
2 * Device driver for the SYMBIOS/LSILOGIC 53C8XX and 53C1010 family
3 * of PCI-SCSI IO processors.
5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
7 * This driver is derived from the Linux sym53c8xx driver.
8 * Copyright (C) 1998-2000 Gerard Roudier
10 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been
11 * a port of the FreeBSD ncr driver to Linux-1.2.13.
13 * The original ncr driver has been written for 386bsd and FreeBSD by
14 * Wolfgang Stanglmeier <wolf@cologne.de>
15 * Stefan Esser <se@mi.Uni-Koeln.de>
16 * Copyright (C) 1994 Wolfgang Stanglmeier
18 * Other major contributions:
20 * NVRAM detection and reading.
21 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
23 *-----------------------------------------------------------------------------
25 * This program is free software; you can redistribute it and/or modify
26 * it under the terms of the GNU General Public License as published by
27 * the Free Software Foundation; either version 2 of the License, or
28 * (at your option) any later version.
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, write to the Free Software
37 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
40 #ifndef SYM_GLUE_H
41 #define SYM_GLUE_H
43 #include <linux/completion.h>
44 #include <linux/delay.h>
45 #include <linux/interrupt.h>
46 #include <linux/ioport.h>
47 #include <linux/pci.h>
48 #include <linux/string.h>
49 #include <linux/timer.h>
50 #include <linux/types.h>
52 #include <asm/io.h>
53 #ifdef __sparc__
54 # include <asm/irq.h>
55 #endif
57 #include <scsi/scsi.h>
58 #include <scsi/scsi_cmnd.h>
59 #include <scsi/scsi_device.h>
60 #include <scsi/scsi_transport_spi.h>
61 #include <scsi/scsi_host.h>
63 #include "sym53c8xx.h"
64 #include "sym_defs.h"
65 #include "sym_misc.h"
68 * Configuration addendum for Linux.
70 #define SYM_CONF_TIMER_INTERVAL ((HZ+1)/2)
72 #undef SYM_OPT_HANDLE_DEVICE_QUEUEING
73 #define SYM_OPT_LIMIT_COMMAND_REORDERING
76 * Print a message with severity.
78 #define printf_emerg(args...) printk(KERN_EMERG args)
79 #define printf_alert(args...) printk(KERN_ALERT args)
80 #define printf_crit(args...) printk(KERN_CRIT args)
81 #define printf_err(args...) printk(KERN_ERR args)
82 #define printf_warning(args...) printk(KERN_WARNING args)
83 #define printf_notice(args...) printk(KERN_NOTICE args)
84 #define printf_info(args...) printk(KERN_INFO args)
85 #define printf_debug(args...) printk(KERN_DEBUG args)
86 #define printf(args...) printk(args)
89 * A 'read barrier' flushes any data that have been prefetched
90 * by the processor due to out of order execution. Such a barrier
91 * must notably be inserted prior to looking at data that have
92 * been DMAed, assuming that program does memory READs in proper
93 * order and that the device ensured proper ordering of WRITEs.
95 * A 'write barrier' prevents any previous WRITEs to pass further
96 * WRITEs. Such barriers must be inserted each time another agent
97 * relies on ordering of WRITEs.
99 * Note that, due to posting of PCI memory writes, we also must
100 * insert dummy PCI read transactions when some ordering involving
101 * both directions over the PCI does matter. PCI transactions are
102 * fully ordered in each direction.
105 #define MEMORY_READ_BARRIER() rmb()
106 #define MEMORY_WRITE_BARRIER() wmb()
109 * IO functions definition for big/little endian CPU support.
110 * For now, PCI chips are only supported in little endian addressing mode,
113 #ifdef __BIG_ENDIAN
115 #define readw_l2b readw
116 #define readl_l2b readl
117 #define writew_b2l writew
118 #define writel_b2l writel
120 #else /* little endian */
122 #define readw_raw readw
123 #define readl_raw readl
124 #define writew_raw writew
125 #define writel_raw writel
127 #endif /* endian */
129 #ifdef SYM_CONF_CHIP_BIG_ENDIAN
130 #error "Chips in BIG ENDIAN addressing mode are not (yet) supported"
131 #endif
134 * If the CPU and the chip use same endian-ness addressing,
135 * no byte reordering is needed for script patching.
136 * Macro cpu_to_scr() is to be used for script patching.
137 * Macro scr_to_cpu() is to be used for getting a DWORD
138 * from the script.
141 #define cpu_to_scr(dw) cpu_to_le32(dw)
142 #define scr_to_cpu(dw) le32_to_cpu(dw)
145 * These ones are used as return code from
146 * error recovery handlers under Linux.
148 #define SCSI_SUCCESS SUCCESS
149 #define SCSI_FAILED FAILED
152 * System specific target data structure.
153 * None for now, under Linux.
155 /* #define SYM_HAVE_STCB */
158 * System specific lun data structure.
160 #define SYM_HAVE_SLCB
161 struct sym_slcb {
162 u_short reqtags; /* Number of tags requested by user */
163 u_short scdev_depth; /* Queue depth set in select_queue_depth() */
167 * System specific command data structure.
168 * Not needed under Linux.
170 /* struct sym_sccb */
173 * System specific host data structure.
175 struct sym_shcb {
177 * Chip and controller indentification.
179 int unit;
180 char inst_name[16];
181 char chip_name[8];
183 struct Scsi_Host *host;
185 void __iomem * ioaddr; /* MMIO kernel io address */
186 void __iomem * ramaddr; /* RAM kernel io address */
188 struct timer_list timer; /* Timer handler link header */
189 u_long lasttime;
190 u_long settle_time; /* Resetting the SCSI BUS */
191 u_char settle_time_valid;
195 * Return the name of the controller.
197 #define sym_name(np) (np)->s.inst_name
199 struct sym_nvram;
202 * The IO macros require a struct called 's' and are abused in sym_nvram.c
204 struct sym_device {
205 struct pci_dev *pdev;
206 unsigned long mmio_base;
207 unsigned long ram_base;
208 struct {
209 void __iomem *ioaddr;
210 void __iomem *ramaddr;
211 } s;
212 struct sym_chip chip;
213 struct sym_nvram *nvram;
214 u_char host_id;
218 * Driver host data structure.
220 struct sym_data {
221 struct sym_hcb *ncb;
222 struct completion *io_reset; /* PCI error handling */
223 struct pci_dev *pdev;
226 static inline struct sym_hcb * sym_get_hcb(struct Scsi_Host *host)
228 return ((struct sym_data *)host->hostdata)->ncb;
231 #include "sym_fw.h"
232 #include "sym_hipd.h"
235 * Set the status field of a CAM CCB.
237 static inline void
238 sym_set_cam_status(struct scsi_cmnd *cmd, int status)
240 cmd->result &= ~(0xff << 16);
241 cmd->result |= (status << 16);
245 * Get the status field of a CAM CCB.
247 static inline int
248 sym_get_cam_status(struct scsi_cmnd *cmd)
250 return host_byte(cmd->result);
254 * Build CAM result for a successful IO and for a failed IO.
256 static inline void sym_set_cam_result_ok(struct sym_ccb *cp, struct scsi_cmnd *cmd, int resid)
258 scsi_set_resid(cmd, resid);
259 cmd->result = (((DID_OK) << 16) + ((cp->ssss_status) & 0x7f));
261 void sym_set_cam_result_error(struct sym_hcb *np, struct sym_ccb *cp, int resid);
263 void sym_xpt_done(struct sym_hcb *np, struct scsi_cmnd *ccb);
264 #define sym_print_addr(cmd, arg...) dev_info(&cmd->device->sdev_gendev , ## arg)
265 void sym_xpt_async_bus_reset(struct sym_hcb *np);
266 int sym_setup_data_and_start (struct sym_hcb *np, struct scsi_cmnd *csio, struct sym_ccb *cp);
267 void sym_log_bus_error(struct Scsi_Host *);
268 void sym_dump_registers(struct Scsi_Host *);
270 #endif /* SYM_GLUE_H */