Blackfin: bf548-ezkit/bf561-ezkit: update nor flash layout
[zen-stable.git] / drivers / target / target_core_rd.h
blob3ea19e29d8ece0fbcad14301aeef15b0b8413d75
1 #ifndef TARGET_CORE_RD_H
2 #define TARGET_CORE_RD_H
4 #define RD_HBA_VERSION "v4.0"
5 #define RD_DR_VERSION "4.0"
6 #define RD_MCP_VERSION "4.0"
8 /* Largest piece of memory kmalloc can allocate */
9 #define RD_MAX_ALLOCATION_SIZE 65536
10 /* Maximum queuedepth for the Ramdisk HBA */
11 #define RD_HBA_QUEUE_DEPTH 256
12 #define RD_DEVICE_QUEUE_DEPTH 32
13 #define RD_MAX_DEVICE_QUEUE_DEPTH 128
14 #define RD_BLOCKSIZE 512
15 #define RD_MAX_SECTORS 1024
17 /* Used in target_core_init_configfs() for virtual LUN 0 access */
18 int __init rd_module_init(void);
19 void rd_module_exit(void);
21 #define RRF_EMULATE_CDB 0x01
22 #define RRF_GOT_LBA 0x02
24 struct rd_request {
25 struct se_task rd_task;
27 /* SCSI CDB from iSCSI Command PDU */
28 unsigned char rd_scsi_cdb[TCM_MAX_COMMAND_SIZE];
29 /* Offset from start of page */
30 u32 rd_offset;
31 /* Starting page in Ramdisk for request */
32 u32 rd_page;
33 /* Total number of pages needed for request */
34 u32 rd_page_count;
35 /* Scatterlist count */
36 u32 rd_size;
37 /* Ramdisk device */
38 struct rd_dev *rd_dev;
39 } ____cacheline_aligned;
41 struct rd_dev_sg_table {
42 u32 page_start_offset;
43 u32 page_end_offset;
44 u32 rd_sg_count;
45 struct scatterlist *sg_table;
46 } ____cacheline_aligned;
48 #define RDF_HAS_PAGE_COUNT 0x01
50 struct rd_dev {
51 int rd_direct;
52 u32 rd_flags;
53 /* Unique Ramdisk Device ID in Ramdisk HBA */
54 u32 rd_dev_id;
55 /* Total page count for ramdisk device */
56 u32 rd_page_count;
57 /* Number of SG tables in sg_table_array */
58 u32 sg_table_count;
59 u32 rd_queue_depth;
60 /* Array of rd_dev_sg_table_t containing scatterlists */
61 struct rd_dev_sg_table *sg_table_array;
62 /* Ramdisk HBA device is connected to */
63 struct rd_host *rd_host;
64 } ____cacheline_aligned;
66 struct rd_host {
67 u32 rd_host_dev_id_count;
68 u32 rd_host_id; /* Unique Ramdisk Host ID */
69 } ____cacheline_aligned;
71 #endif /* TARGET_CORE_RD_H */