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tty/serial: atmel_serial: whitespace and braces modifications
[zen-stable.git] / drivers / dma / coh901318.c
blob4234f416ef115055cb425822a2c411a73dd41590
1 /*
2 * driver/dma/coh901318.c
3 *
4 * Copyright (C) 2007-2009 ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 * DMA driver for COH 901 318
7 * Author: Per Friden <per.friden@stericsson.com>
8 */
9
10 #include <linux/init.h>
11 #include <linux/module.h>
12 #include <linux/kernel.h> /* printk() */
13 #include <linux/fs.h> /* everything... */
14 #include <linux/scatterlist.h>
15 #include <linux/slab.h> /* kmalloc() */
16 #include <linux/dmaengine.h>
17 #include <linux/platform_device.h>
18 #include <linux/device.h>
19 #include <linux/irqreturn.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/uaccess.h>
23 #include <linux/debugfs.h>
24 #include <mach/coh901318.h>
25
26 #include "coh901318_lli.h"
27
28 #define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
29
30 #ifdef VERBOSE_DEBUG
31 #define COH_DBG(x) ({ if (1) x; 0; })
32 #else
33 #define COH_DBG(x) ({ if (0) x; 0; })
34 #endif
35
36 struct coh901318_desc {
37 struct dma_async_tx_descriptor desc;
38 struct list_head node;
39 struct scatterlist *sg;
40 unsigned int sg_len;
41 struct coh901318_lli *lli;
42 enum dma_data_direction dir;
43 unsigned long flags;
44 u32 head_config;
45 u32 head_ctrl;
46 };
47
48 struct coh901318_base {
49 struct device *dev;
50 void __iomem *virtbase;
51 struct coh901318_pool pool;
52 struct powersave pm;
53 struct dma_device dma_slave;
54 struct dma_device dma_memcpy;
55 struct coh901318_chan *chans;
56 struct coh901318_platform *platform;
57 };
58
59 struct coh901318_chan {
60 spinlock_t lock;
61 int allocated;
62 int completed;
63 int id;
64 int stopped;
65
66 struct work_struct free_work;
67 struct dma_chan chan;
68
69 struct tasklet_struct tasklet;
70
71 struct list_head active;
72 struct list_head queue;
73 struct list_head free;
74
75 unsigned long nbr_active_done;
76 unsigned long busy;
77
78 u32 runtime_addr;
79 u32 runtime_ctrl;
80
81 struct coh901318_base *base;
82 };
83
84 static void coh901318_list_print(struct coh901318_chan *cohc,
85 struct coh901318_lli *lli)
86 {
87 struct coh901318_lli *l = lli;
88 int i = 0;
89
90 while (l) {
91 dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%x"
92 ", dst 0x%x, link 0x%x virt_link_addr 0x%p\n",
93 i, l, l->control, l->src_addr, l->dst_addr,
94 l->link_addr, l->virt_link_addr);
95 i++;
96 l = l->virt_link_addr;
97 }
98 }
99
100 #ifdef CONFIG_DEBUG_FS
101
102 #define COH901318_DEBUGFS_ASSIGN(x, y) (x = y)
103
104 static struct coh901318_base *debugfs_dma_base;
105 static struct dentry *dma_dentry;
106
107 static int coh901318_debugfs_open(struct inode *inode, struct file *file)
108 {
109
110 file->private_data = inode->i_private;
111 return 0;
112 }
113
114 static int coh901318_debugfs_read(struct file *file, char __user *buf,
115 size_t count, loff_t *f_pos)
116 {
117 u64 started_channels = debugfs_dma_base->pm.started_channels;
118 int pool_count = debugfs_dma_base->pool.debugfs_pool_counter;
119 int i;
120 int ret = 0;
121 char *dev_buf;
122 char *tmp;
123 int dev_size;
124
125 dev_buf = kmalloc(4*1024, GFP_KERNEL);
126 if (dev_buf == NULL)
127 goto err_kmalloc;
128 tmp = dev_buf;
129
130 tmp += sprintf(tmp, "DMA -- enabled dma channels\n");
131
132 for (i = 0; i < debugfs_dma_base->platform->max_channels; i++)
133 if (started_channels & (1 << i))
134 tmp += sprintf(tmp, "channel %d\n", i);
135
136 tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count);
137 dev_size = tmp - dev_buf;
138
139 /* No more to read if offset != 0 */
140 if (*f_pos > dev_size)
141 goto out;
142
143 if (count > dev_size - *f_pos)
144 count = dev_size - *f_pos;
145
146 if (copy_to_user(buf, dev_buf + *f_pos, count))
147 ret = -EINVAL;
148 ret = count;
149 *f_pos += count;
150
151 out:
152 kfree(dev_buf);
153 return ret;
154
155 err_kmalloc:
156 return 0;
157 }
158
159 static const struct file_operations coh901318_debugfs_status_operations = {
160 .owner = THIS_MODULE,
161 .open = coh901318_debugfs_open,
162 .read = coh901318_debugfs_read,
163 .llseek = default_llseek,
164 };
165
166
167 static int __init init_coh901318_debugfs(void)
168 {
169
170 dma_dentry = debugfs_create_dir("dma", NULL);
171
172 (void) debugfs_create_file("status",
173 S_IFREG | S_IRUGO,
174 dma_dentry, NULL,
175 &coh901318_debugfs_status_operations);
176 return 0;
177 }
178
179 static void __exit exit_coh901318_debugfs(void)
180 {
181 debugfs_remove_recursive(dma_dentry);
182 }
183
184 module_init(init_coh901318_debugfs);
185 module_exit(exit_coh901318_debugfs);
186 #else
187
188 #define COH901318_DEBUGFS_ASSIGN(x, y)
189
190 #endif /* CONFIG_DEBUG_FS */
191
192 static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
193 {
194 return container_of(chan, struct coh901318_chan, chan);
195 }
196
197 static inline dma_addr_t
198 cohc_dev_addr(struct coh901318_chan *cohc)
199 {
200 /* Runtime supplied address will take precedence */
201 if (cohc->runtime_addr)
202 return cohc->runtime_addr;
203 return cohc->base->platform->chan_conf[cohc->id].dev_addr;
204 }
205
206 static inline const struct coh901318_params *
207 cohc_chan_param(struct coh901318_chan *cohc)
208 {
209 return &cohc->base->platform->chan_conf[cohc->id].param;
210 }
211
212 static inline const struct coh_dma_channel *
213 cohc_chan_conf(struct coh901318_chan *cohc)
214 {
215 return &cohc->base->platform->chan_conf[cohc->id];
216 }
217
218 static void enable_powersave(struct coh901318_chan *cohc)
219 {
220 unsigned long flags;
221 struct powersave *pm = &cohc->base->pm;
222
223 spin_lock_irqsave(&pm->lock, flags);
224
225 pm->started_channels &= ~(1ULL << cohc->id);
226
227 if (!pm->started_channels) {
228 /* DMA no longer intends to access memory */
229 cohc->base->platform->access_memory_state(cohc->base->dev,
230 false);
231 }
232
233 spin_unlock_irqrestore(&pm->lock, flags);
234 }
235 static void disable_powersave(struct coh901318_chan *cohc)
236 {
237 unsigned long flags;
238 struct powersave *pm = &cohc->base->pm;
239
240 spin_lock_irqsave(&pm->lock, flags);
241
242 if (!pm->started_channels) {
243 /* DMA intends to access memory */
244 cohc->base->platform->access_memory_state(cohc->base->dev,
245 true);
246 }
247
248 pm->started_channels |= (1ULL << cohc->id);
249
250 spin_unlock_irqrestore(&pm->lock, flags);
251 }
252
253 static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control)
254 {
255 int channel = cohc->id;
256 void __iomem *virtbase = cohc->base->virtbase;
257
258 writel(control,
259 virtbase + COH901318_CX_CTRL +
260 COH901318_CX_CTRL_SPACING * channel);
261 return 0;
262 }
263
264 static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf)
265 {
266 int channel = cohc->id;
267 void __iomem *virtbase = cohc->base->virtbase;
268
269 writel(conf,
270 virtbase + COH901318_CX_CFG +
271 COH901318_CX_CFG_SPACING*channel);
272 return 0;
273 }
274
275
276 static int coh901318_start(struct coh901318_chan *cohc)
277 {
278 u32 val;
279 int channel = cohc->id;
280 void __iomem *virtbase = cohc->base->virtbase;
281
282 disable_powersave(cohc);
283
284 val = readl(virtbase + COH901318_CX_CFG +
285 COH901318_CX_CFG_SPACING * channel);
286
287 /* Enable channel */
288 val |= COH901318_CX_CFG_CH_ENABLE;
289 writel(val, virtbase + COH901318_CX_CFG +
290 COH901318_CX_CFG_SPACING * channel);
291
292 return 0;
293 }
294
295 static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
296 struct coh901318_lli *lli)
297 {
298 int channel = cohc->id;
299 void __iomem *virtbase = cohc->base->virtbase;
300
301 BUG_ON(readl(virtbase + COH901318_CX_STAT +
302 COH901318_CX_STAT_SPACING*channel) &
303 COH901318_CX_STAT_ACTIVE);
304
305 writel(lli->src_addr,
306 virtbase + COH901318_CX_SRC_ADDR +
307 COH901318_CX_SRC_ADDR_SPACING * channel);
308
309 writel(lli->dst_addr, virtbase +
310 COH901318_CX_DST_ADDR +
311 COH901318_CX_DST_ADDR_SPACING * channel);
312
313 writel(lli->link_addr, virtbase + COH901318_CX_LNK_ADDR +
314 COH901318_CX_LNK_ADDR_SPACING * channel);
315
316 writel(lli->control, virtbase + COH901318_CX_CTRL +
317 COH901318_CX_CTRL_SPACING * channel);
318
319 return 0;
320 }
321 static dma_cookie_t
322 coh901318_assign_cookie(struct coh901318_chan *cohc,
323 struct coh901318_desc *cohd)
324 {
325 dma_cookie_t cookie = cohc->chan.cookie;
326
327 if (++cookie < 0)
328 cookie = 1;
329
330 cohc->chan.cookie = cookie;
331 cohd->desc.cookie = cookie;
332
333 return cookie;
334 }
335
336 static struct coh901318_desc *
337 coh901318_desc_get(struct coh901318_chan *cohc)
338 {
339 struct coh901318_desc *desc;
340
341 if (list_empty(&cohc->free)) {
342 /* alloc new desc because we're out of used ones
343 * TODO: alloc a pile of descs instead of just one,
344 * avoid many small allocations.
345 */
346 desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT);
347 if (desc == NULL)
348 goto out;
349 INIT_LIST_HEAD(&desc->node);
350 dma_async_tx_descriptor_init(&desc->desc, &cohc->chan);
351 } else {
352 /* Reuse an old desc. */
353 desc = list_first_entry(&cohc->free,
354 struct coh901318_desc,
355 node);
356 list_del(&desc->node);
357 /* Initialize it a bit so it's not insane */
358 desc->sg = NULL;
359 desc->sg_len = 0;
360 desc->desc.callback = NULL;
361 desc->desc.callback_param = NULL;
362 }
363
364 out:
365 return desc;
366 }
367
368 static void
369 coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd)
370 {
371 list_add_tail(&cohd->node, &cohc->free);
372 }
373
374 /* call with irq lock held */
375 static void
376 coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc)
377 {
378 list_add_tail(&desc->node, &cohc->active);
379 }
380
381 static struct coh901318_desc *
382 coh901318_first_active_get(struct coh901318_chan *cohc)
383 {
384 struct coh901318_desc *d;
385
386 if (list_empty(&cohc->active))
387 return NULL;
388
389 d = list_first_entry(&cohc->active,
390 struct coh901318_desc,
391 node);
392 return d;
393 }
394
395 static void
396 coh901318_desc_remove(struct coh901318_desc *cohd)
397 {
398 list_del(&cohd->node);
399 }
400
401 static void
402 coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc)
403 {
404 list_add_tail(&desc->node, &cohc->queue);
405 }
406
407 static struct coh901318_desc *
408 coh901318_first_queued(struct coh901318_chan *cohc)
409 {
410 struct coh901318_desc *d;
411
412 if (list_empty(&cohc->queue))
413 return NULL;
414
415 d = list_first_entry(&cohc->queue,
416 struct coh901318_desc,
417 node);
418 return d;
419 }
420
421 static inline u32 coh901318_get_bytes_in_lli(struct coh901318_lli *in_lli)
422 {
423 struct coh901318_lli *lli = in_lli;
424 u32 bytes = 0;
425
426 while (lli) {
427 bytes += lli->control & COH901318_CX_CTRL_TC_VALUE_MASK;
428 lli = lli->virt_link_addr;
429 }
430 return bytes;
431 }
432
433 /*
434 * Get the number of bytes left to transfer on this channel,
435 * it is unwise to call this before stopping the channel for
436 * absolute measures, but for a rough guess you can still call
437 * it.
438 */
439 static u32 coh901318_get_bytes_left(struct dma_chan *chan)
440 {
441 struct coh901318_chan *cohc = to_coh901318_chan(chan);
442 struct coh901318_desc *cohd;
443 struct list_head *pos;
444 unsigned long flags;
445 u32 left = 0;
446 int i = 0;
447
448 spin_lock_irqsave(&cohc->lock, flags);
449
450 /*
451 * If there are many queued jobs, we iterate and add the
452 * size of them all. We take a special look on the first
453 * job though, since it is probably active.
454 */
455 list_for_each(pos, &cohc->active) {
456 /*
457 * The first job in the list will be working on the
458 * hardware. The job can be stopped but still active,
459 * so that the transfer counter is somewhere inside
460 * the buffer.
461 */
462 cohd = list_entry(pos, struct coh901318_desc, node);
463
464 if (i == 0) {
465 struct coh901318_lli *lli;
466 dma_addr_t ladd;
467
468 /* Read current transfer count value */
469 left = readl(cohc->base->virtbase +
470 COH901318_CX_CTRL +
471 COH901318_CX_CTRL_SPACING * cohc->id) &
472 COH901318_CX_CTRL_TC_VALUE_MASK;
473
474 /* See if the transfer is linked... */
475 ladd = readl(cohc->base->virtbase +
476 COH901318_CX_LNK_ADDR +
477 COH901318_CX_LNK_ADDR_SPACING *
478 cohc->id) &
479 ~COH901318_CX_LNK_LINK_IMMEDIATE;
480 /* Single transaction */
481 if (!ladd)
482 continue;
483
484 /*
485 * Linked transaction, follow the lli, find the
486 * currently processing lli, and proceed to the next
487 */
488 lli = cohd->lli;
489 while (lli && lli->link_addr != ladd)
490 lli = lli->virt_link_addr;
491
492 if (lli)
493 lli = lli->virt_link_addr;
494
495 /*
496 * Follow remaining lli links around to count the total
497 * number of bytes left
498 */
499 left += coh901318_get_bytes_in_lli(lli);
500 } else {
501 left += coh901318_get_bytes_in_lli(cohd->lli);
502 }
503 i++;
504 }
505
506 /* Also count bytes in the queued jobs */
507 list_for_each(pos, &cohc->queue) {
508 cohd = list_entry(pos, struct coh901318_desc, node);
509 left += coh901318_get_bytes_in_lli(cohd->lli);
510 }
511
512 spin_unlock_irqrestore(&cohc->lock, flags);
513
514 return left;
515 }
516
517 /*
518 * Pauses a transfer without losing data. Enables power save.
519 * Use this function in conjunction with coh901318_resume.
520 */
521 static void coh901318_pause(struct dma_chan *chan)
522 {
523 u32 val;
524 unsigned long flags;
525 struct coh901318_chan *cohc = to_coh901318_chan(chan);
526 int channel = cohc->id;
527 void __iomem *virtbase = cohc->base->virtbase;
528
529 spin_lock_irqsave(&cohc->lock, flags);
530
531 /* Disable channel in HW */
532 val = readl(virtbase + COH901318_CX_CFG +
533 COH901318_CX_CFG_SPACING * channel);
534
535 /* Stopping infinite transfer */
536 if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 &&
537 (val & COH901318_CX_CFG_CH_ENABLE))
538 cohc->stopped = 1;
539
540
541 val &= ~COH901318_CX_CFG_CH_ENABLE;
542 /* Enable twice, HW bug work around */
543 writel(val, virtbase + COH901318_CX_CFG +
544 COH901318_CX_CFG_SPACING * channel);
545 writel(val, virtbase + COH901318_CX_CFG +
546 COH901318_CX_CFG_SPACING * channel);
547
548 /* Spin-wait for it to actually go inactive */
549 while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING *
550 channel) & COH901318_CX_STAT_ACTIVE)
551 cpu_relax();
552
553 /* Check if we stopped an active job */
554 if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
555 channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0)
556 cohc->stopped = 1;
557
558 enable_powersave(cohc);
559
560 spin_unlock_irqrestore(&cohc->lock, flags);
561 }
562
563 /* Resumes a transfer that has been stopped via 300_dma_stop(..).
564 Power save is handled.
565 */
566 static void coh901318_resume(struct dma_chan *chan)
567 {
568 u32 val;
569 unsigned long flags;
570 struct coh901318_chan *cohc = to_coh901318_chan(chan);
571 int channel = cohc->id;
572
573 spin_lock_irqsave(&cohc->lock, flags);
574
575 disable_powersave(cohc);
576
577 if (cohc->stopped) {
578 /* Enable channel in HW */
579 val = readl(cohc->base->virtbase + COH901318_CX_CFG +
580 COH901318_CX_CFG_SPACING * channel);
581
582 val |= COH901318_CX_CFG_CH_ENABLE;
583
584 writel(val, cohc->base->virtbase + COH901318_CX_CFG +
585 COH901318_CX_CFG_SPACING*channel);
586
587 cohc->stopped = 0;
588 }
589
590 spin_unlock_irqrestore(&cohc->lock, flags);
591 }
592
593 bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
594 {
595 unsigned int ch_nr = (unsigned int) chan_id;
596
597 if (ch_nr == to_coh901318_chan(chan)->id)
598 return true;
599
600 return false;
601 }
602 EXPORT_SYMBOL(coh901318_filter_id);
603
604 /*
605 * DMA channel allocation
606 */
607 static int coh901318_config(struct coh901318_chan *cohc,
608 struct coh901318_params *param)
609 {
610 unsigned long flags;
611 const struct coh901318_params *p;
612 int channel = cohc->id;
613 void __iomem *virtbase = cohc->base->virtbase;
614
615 spin_lock_irqsave(&cohc->lock, flags);
616
617 if (param)
618 p = param;
619 else
620 p = &cohc->base->platform->chan_conf[channel].param;
621
622 /* Clear any pending BE or TC interrupt */
623 if (channel < 32) {
624 writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1);
625 writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1);
626 } else {
627 writel(1 << (channel - 32), virtbase +
628 COH901318_BE_INT_CLEAR2);
629 writel(1 << (channel - 32), virtbase +
630 COH901318_TC_INT_CLEAR2);
631 }
632
633 coh901318_set_conf(cohc, p->config);
634 coh901318_set_ctrl(cohc, p->ctrl_lli_last);
635
636 spin_unlock_irqrestore(&cohc->lock, flags);
637
638 return 0;
639 }
640
641 /* must lock when calling this function
642 * start queued jobs, if any
643 * TODO: start all queued jobs in one go
644 *
645 * Returns descriptor if queued job is started otherwise NULL.
646 * If the queue is empty NULL is returned.
647 */
648 static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc)
649 {
650 struct coh901318_desc *cohd;
651
652 /*
653 * start queued jobs, if any
654 * TODO: transmit all queued jobs in one go
655 */
656 cohd = coh901318_first_queued(cohc);
657
658 if (cohd != NULL) {
659 /* Remove from queue */
660 coh901318_desc_remove(cohd);
661 /* initiate DMA job */
662 cohc->busy = 1;
663
664 coh901318_desc_submit(cohc, cohd);
665
666 /* Program the transaction head */
667 coh901318_set_conf(cohc, cohd->head_config);
668 coh901318_set_ctrl(cohc, cohd->head_ctrl);
669 coh901318_prep_linked_list(cohc, cohd->lli);
670
671 /* start dma job on this channel */
672 coh901318_start(cohc);
673
674 }
675
676 return cohd;
677 }
678
679 /*
680 * This tasklet is called from the interrupt handler to
681 * handle each descriptor (DMA job) that is sent to a channel.
682 */
683 static void dma_tasklet(unsigned long data)
684 {
685 struct coh901318_chan *cohc = (struct coh901318_chan *) data;
686 struct coh901318_desc *cohd_fin;
687 unsigned long flags;
688 dma_async_tx_callback callback;
689 void *callback_param;
690
691 dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d"
692 " nbr_active_done %ld\n", __func__,
693 cohc->id, cohc->nbr_active_done);
694
695 spin_lock_irqsave(&cohc->lock, flags);
696
697 /* get first active descriptor entry from list */
698 cohd_fin = coh901318_first_active_get(cohc);
699
700 if (cohd_fin == NULL)
701 goto err;
702
703 /* locate callback to client */
704 callback = cohd_fin->desc.callback;
705 callback_param = cohd_fin->desc.callback_param;
706
707 /* sign this job as completed on the channel */
708 cohc->completed = cohd_fin->desc.cookie;
709
710 /* release the lli allocation and remove the descriptor */
711 coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
712
713 /* return desc to free-list */
714 coh901318_desc_remove(cohd_fin);
715 coh901318_desc_free(cohc, cohd_fin);
716
717 spin_unlock_irqrestore(&cohc->lock, flags);
718
719 /* Call the callback when we're done */
720 if (callback)
721 callback(callback_param);
722
723 spin_lock_irqsave(&cohc->lock, flags);
724
725 /*
726 * If another interrupt fired while the tasklet was scheduling,
727 * we don't get called twice, so we have this number of active
728 * counter that keep track of the number of IRQs expected to
729 * be handled for this channel. If there happen to be more than
730 * one IRQ to be ack:ed, we simply schedule this tasklet again.
731 */
732 cohc->nbr_active_done--;
733 if (cohc->nbr_active_done) {
734 dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs "
735 "came in while we were scheduling this tasklet\n");
736 if (cohc_chan_conf(cohc)->priority_high)
737 tasklet_hi_schedule(&cohc->tasklet);
738 else
739 tasklet_schedule(&cohc->tasklet);
740 }
741
742 spin_unlock_irqrestore(&cohc->lock, flags);
743
744 return;
745
746 err:
747 spin_unlock_irqrestore(&cohc->lock, flags);
748 dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__);
749 }
750
751
752 /* called from interrupt context */
753 static void dma_tc_handle(struct coh901318_chan *cohc)
754 {
755 /*
756 * If the channel is not allocated, then we shouldn't have
757 * any TC interrupts on it.
758 */
759 if (!cohc->allocated) {
760 dev_err(COHC_2_DEV(cohc), "spurious interrupt from "
761 "unallocated channel\n");
762 return;
763 }
764
765 spin_lock(&cohc->lock);
766
767 /*
768 * When we reach this point, at least one queue item
769 * should have been moved over from cohc->queue to
770 * cohc->active and run to completion, that is why we're
771 * getting a terminal count interrupt is it not?
772 * If you get this BUG() the most probable cause is that
773 * the individual nodes in the lli chain have IRQ enabled,
774 * so check your platform config for lli chain ctrl.
775 */
776 BUG_ON(list_empty(&cohc->active));
777
778 cohc->nbr_active_done++;
779
780 /*
781 * This attempt to take a job from cohc->queue, put it
782 * into cohc->active and start it.
783 */
784 if (coh901318_queue_start(cohc) == NULL)
785 cohc->busy = 0;
786
787 spin_unlock(&cohc->lock);
788
789 /*
790 * This tasklet will remove items from cohc->active
791 * and thus terminates them.
792 */
793 if (cohc_chan_conf(cohc)->priority_high)
794 tasklet_hi_schedule(&cohc->tasklet);
795 else
796 tasklet_schedule(&cohc->tasklet);
797 }
798
799
800 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
801 {
802 u32 status1;
803 u32 status2;
804 int i;
805 int ch;
806 struct coh901318_base *base = dev_id;
807 struct coh901318_chan *cohc;
808 void __iomem *virtbase = base->virtbase;
809
810 status1 = readl(virtbase + COH901318_INT_STATUS1);
811 status2 = readl(virtbase + COH901318_INT_STATUS2);
812
813 if (unlikely(status1 == 0 && status2 == 0)) {
814 dev_warn(base->dev, "spurious DMA IRQ from no channel!\n");
815 return IRQ_HANDLED;
816 }
817
818 /* TODO: consider handle IRQ in tasklet here to
819 * minimize interrupt latency */
820
821 /* Check the first 32 DMA channels for IRQ */
822 while (status1) {
823 /* Find first bit set, return as a number. */
824 i = ffs(status1) - 1;
825 ch = i;
826
827 cohc = &base->chans[ch];
828 spin_lock(&cohc->lock);
829
830 /* Mask off this bit */
831 status1 &= ~(1 << i);
832 /* Check the individual channel bits */
833 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) {
834 dev_crit(COHC_2_DEV(cohc),
835 "DMA bus error on channel %d!\n", ch);
836 BUG_ON(1);
837 /* Clear BE interrupt */
838 __set_bit(i, virtbase + COH901318_BE_INT_CLEAR1);
839 } else {
840 /* Caused by TC, really? */
841 if (unlikely(!test_bit(i, virtbase +
842 COH901318_TC_INT_STATUS1))) {
843 dev_warn(COHC_2_DEV(cohc),
844 "ignoring interrupt not caused by terminal count on channel %d\n", ch);
845 /* Clear TC interrupt */
846 BUG_ON(1);
847 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
848 } else {
849 /* Enable powersave if transfer has finished */
850 if (!(readl(virtbase + COH901318_CX_STAT +
851 COH901318_CX_STAT_SPACING*ch) &
852 COH901318_CX_STAT_ENABLED)) {
853 enable_powersave(cohc);
854 }
855
856 /* Must clear TC interrupt before calling
857 * dma_tc_handle
858 * in case tc_handle initiate a new dma job
859 */
860 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
861
862 dma_tc_handle(cohc);
863 }
864 }
865 spin_unlock(&cohc->lock);
866 }
867
868 /* Check the remaining 32 DMA channels for IRQ */
869 while (status2) {
870 /* Find first bit set, return as a number. */
871 i = ffs(status2) - 1;
872 ch = i + 32;
873 cohc = &base->chans[ch];
874 spin_lock(&cohc->lock);
875
876 /* Mask off this bit */
877 status2 &= ~(1 << i);
878 /* Check the individual channel bits */
879 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) {
880 dev_crit(COHC_2_DEV(cohc),
881 "DMA bus error on channel %d!\n", ch);
882 /* Clear BE interrupt */
883 BUG_ON(1);
884 __set_bit(i, virtbase + COH901318_BE_INT_CLEAR2);
885 } else {
886 /* Caused by TC, really? */
887 if (unlikely(!test_bit(i, virtbase +
888 COH901318_TC_INT_STATUS2))) {
889 dev_warn(COHC_2_DEV(cohc),
890 "ignoring interrupt not caused by terminal count on channel %d\n", ch);
891 /* Clear TC interrupt */
892 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
893 BUG_ON(1);
894 } else {
895 /* Enable powersave if transfer has finished */
896 if (!(readl(virtbase + COH901318_CX_STAT +
897 COH901318_CX_STAT_SPACING*ch) &
898 COH901318_CX_STAT_ENABLED)) {
899 enable_powersave(cohc);
900 }
901 /* Must clear TC interrupt before calling
902 * dma_tc_handle
903 * in case tc_handle initiate a new dma job
904 */
905 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
906
907 dma_tc_handle(cohc);
908 }
909 }
910 spin_unlock(&cohc->lock);
911 }
912
913 return IRQ_HANDLED;
914 }
915
916 static int coh901318_alloc_chan_resources(struct dma_chan *chan)
917 {
918 struct coh901318_chan *cohc = to_coh901318_chan(chan);
919 unsigned long flags;
920
921 dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n",
922 __func__, cohc->id);
923
924 if (chan->client_count > 1)
925 return -EBUSY;
926
927 spin_lock_irqsave(&cohc->lock, flags);
928
929 coh901318_config(cohc, NULL);
930
931 cohc->allocated = 1;
932 cohc->completed = chan->cookie = 1;
933
934 spin_unlock_irqrestore(&cohc->lock, flags);
935
936 return 1;
937 }
938
939 static void
940 coh901318_free_chan_resources(struct dma_chan *chan)
941 {
942 struct coh901318_chan *cohc = to_coh901318_chan(chan);
943 int channel = cohc->id;
944 unsigned long flags;
945
946 spin_lock_irqsave(&cohc->lock, flags);
947
948 /* Disable HW */
949 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG +
950 COH901318_CX_CFG_SPACING*channel);
951 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL +
952 COH901318_CX_CTRL_SPACING*channel);
953
954 cohc->allocated = 0;
955
956 spin_unlock_irqrestore(&cohc->lock, flags);
957
958 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
959 }
960
961
962 static dma_cookie_t
963 coh901318_tx_submit(struct dma_async_tx_descriptor *tx)
964 {
965 struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc,
966 desc);
967 struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
968 unsigned long flags;
969
970 spin_lock_irqsave(&cohc->lock, flags);
971
972 tx->cookie = coh901318_assign_cookie(cohc, cohd);
973
974 coh901318_desc_queue(cohc, cohd);
975
976 spin_unlock_irqrestore(&cohc->lock, flags);
977
978 return tx->cookie;
979 }
980
981 static struct dma_async_tx_descriptor *
982 coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
983 size_t size, unsigned long flags)
984 {
985 struct coh901318_lli *lli;
986 struct coh901318_desc *cohd;
987 unsigned long flg;
988 struct coh901318_chan *cohc = to_coh901318_chan(chan);
989 int lli_len;
990 u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
991 int ret;
992
993 spin_lock_irqsave(&cohc->lock, flg);
994
995 dev_vdbg(COHC_2_DEV(cohc),
996 "[%s] channel %d src 0x%x dest 0x%x size %d\n",
997 __func__, cohc->id, src, dest, size);
998
999 if (flags & DMA_PREP_INTERRUPT)
1000 /* Trigger interrupt after last lli */
1001 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
1002
1003 lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT;
1004 if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size)
1005 lli_len++;
1006
1007 lli = coh901318_lli_alloc(&cohc->base->pool, lli_len);
1008
1009 if (lli == NULL)
1010 goto err;
1011
1012 ret = coh901318_lli_fill_memcpy(
1013 &cohc->base->pool, lli, src, size, dest,
1014 cohc_chan_param(cohc)->ctrl_lli_chained,
1015 ctrl_last);
1016 if (ret)
1017 goto err;
1018
1019 COH_DBG(coh901318_list_print(cohc, lli));
1020
1021 /* Pick a descriptor to handle this transfer */
1022 cohd = coh901318_desc_get(cohc);
1023 cohd->lli = lli;
1024 cohd->flags = flags;
1025 cohd->desc.tx_submit = coh901318_tx_submit;
1026
1027 spin_unlock_irqrestore(&cohc->lock, flg);
1028
1029 return &cohd->desc;
1030 err:
1031 spin_unlock_irqrestore(&cohc->lock, flg);
1032 return NULL;
1033 }
1034
1035 static struct dma_async_tx_descriptor *
1036 coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1037 unsigned int sg_len, enum dma_data_direction direction,
1038 unsigned long flags)
1039 {
1040 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1041 struct coh901318_lli *lli;
1042 struct coh901318_desc *cohd;
1043 const struct coh901318_params *params;
1044 struct scatterlist *sg;
1045 int len = 0;
1046 int size;
1047 int i;
1048 u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained;
1049 u32 ctrl = cohc_chan_param(cohc)->ctrl_lli;
1050 u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
1051 u32 config;
1052 unsigned long flg;
1053 int ret;
1054
1055 if (!sgl)
1056 goto out;
1057 if (sgl->length == 0)
1058 goto out;
1059
1060 spin_lock_irqsave(&cohc->lock, flg);
1061
1062 dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n",
1063 __func__, sg_len, direction);
1064
1065 if (flags & DMA_PREP_INTERRUPT)
1066 /* Trigger interrupt after last lli */
1067 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
1068
1069 params = cohc_chan_param(cohc);
1070 config = params->config;
1071 /*
1072 * Add runtime-specific control on top, make
1073 * sure the bits you set per peripheral channel are
1074 * cleared in the default config from the platform.
1075 */
1076 ctrl_chained |= cohc->runtime_ctrl;
1077 ctrl_last |= cohc->runtime_ctrl;
1078 ctrl |= cohc->runtime_ctrl;
1079
1080 if (direction == DMA_TO_DEVICE) {
1081 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
1082 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
1083
1084 config |= COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY;
1085 ctrl_chained |= tx_flags;
1086 ctrl_last |= tx_flags;
1087 ctrl |= tx_flags;
1088 } else if (direction == DMA_FROM_DEVICE) {
1089 u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST |
1090 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE;
1091
1092 config |= COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY;
1093 ctrl_chained |= rx_flags;
1094 ctrl_last |= rx_flags;
1095 ctrl |= rx_flags;
1096 } else
1097 goto err_direction;
1098
1099 /* The dma only supports transmitting packages up to
1100 * MAX_DMA_PACKET_SIZE. Calculate to total number of
1101 * dma elemts required to send the entire sg list
1102 */
1103 for_each_sg(sgl, sg, sg_len, i) {
1104 unsigned int factor;
1105 size = sg_dma_len(sg);
1106
1107 if (size <= MAX_DMA_PACKET_SIZE) {
1108 len++;
1109 continue;
1110 }
1111
1112 factor = size >> MAX_DMA_PACKET_SIZE_SHIFT;
1113 if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size)
1114 factor++;
1115
1116 len += factor;
1117 }
1118
1119 pr_debug("Allocate %d lli:s for this transfer\n", len);
1120 lli = coh901318_lli_alloc(&cohc->base->pool, len);
1121
1122 if (lli == NULL)
1123 goto err_dma_alloc;
1124
1125 /* initiate allocated lli list */
1126 ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len,
1127 cohc_dev_addr(cohc),
1128 ctrl_chained,
1129 ctrl,
1130 ctrl_last,
1131 direction, COH901318_CX_CTRL_TC_IRQ_ENABLE);
1132 if (ret)
1133 goto err_lli_fill;
1134
1135
1136 COH_DBG(coh901318_list_print(cohc, lli));
1137
1138 /* Pick a descriptor to handle this transfer */
1139 cohd = coh901318_desc_get(cohc);
1140 cohd->head_config = config;
1141 /*
1142 * Set the default head ctrl for the channel to the one from the
1143 * lli, things may have changed due to odd buffer alignment
1144 * etc.
1145 */
1146 cohd->head_ctrl = lli->control;
1147 cohd->dir = direction;
1148 cohd->flags = flags;
1149 cohd->desc.tx_submit = coh901318_tx_submit;
1150 cohd->lli = lli;
1151
1152 spin_unlock_irqrestore(&cohc->lock, flg);
1153
1154 return &cohd->desc;
1155 err_lli_fill:
1156 err_dma_alloc:
1157 err_direction:
1158 spin_unlock_irqrestore(&cohc->lock, flg);
1159 out:
1160 return NULL;
1161 }
1162
1163 static enum dma_status
1164 coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
1165 struct dma_tx_state *txstate)
1166 {
1167 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1168 dma_cookie_t last_used;
1169 dma_cookie_t last_complete;
1170 int ret;
1171
1172 last_complete = cohc->completed;
1173 last_used = chan->cookie;
1174
1175 ret = dma_async_is_complete(cookie, last_complete, last_used);
1176
1177 dma_set_tx_state(txstate, last_complete, last_used,
1178 coh901318_get_bytes_left(chan));
1179 if (ret == DMA_IN_PROGRESS && cohc->stopped)
1180 ret = DMA_PAUSED;
1181
1182 return ret;
1183 }
1184
1185 static void
1186 coh901318_issue_pending(struct dma_chan *chan)
1187 {
1188 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1189 unsigned long flags;
1190
1191 spin_lock_irqsave(&cohc->lock, flags);
1192
1193 /*
1194 * Busy means that pending jobs are already being processed,
1195 * and then there is no point in starting the queue: the
1196 * terminal count interrupt on the channel will take the next
1197 * job on the queue and execute it anyway.
1198 */
1199 if (!cohc->busy)
1200 coh901318_queue_start(cohc);
1201
1202 spin_unlock_irqrestore(&cohc->lock, flags);
1203 }
1204
1205 /*
1206 * Here we wrap in the runtime dma control interface
1207 */
1208 struct burst_table {
1209 int burst_8bit;
1210 int burst_16bit;
1211 int burst_32bit;
1212 u32 reg;
1213 };
1214
1215 static const struct burst_table burst_sizes[] = {
1216 {
1217 .burst_8bit = 64,
1218 .burst_16bit = 32,
1219 .burst_32bit = 16,
1220 .reg = COH901318_CX_CTRL_BURST_COUNT_64_BYTES,
1221 },
1222 {
1223 .burst_8bit = 48,
1224 .burst_16bit = 24,
1225 .burst_32bit = 12,
1226 .reg = COH901318_CX_CTRL_BURST_COUNT_48_BYTES,
1227 },
1228 {
1229 .burst_8bit = 32,
1230 .burst_16bit = 16,
1231 .burst_32bit = 8,
1232 .reg = COH901318_CX_CTRL_BURST_COUNT_32_BYTES,
1233 },
1234 {
1235 .burst_8bit = 16,
1236 .burst_16bit = 8,
1237 .burst_32bit = 4,
1238 .reg = COH901318_CX_CTRL_BURST_COUNT_16_BYTES,
1239 },
1240 {
1241 .burst_8bit = 8,
1242 .burst_16bit = 4,
1243 .burst_32bit = 2,
1244 .reg = COH901318_CX_CTRL_BURST_COUNT_8_BYTES,
1245 },
1246 {
1247 .burst_8bit = 4,
1248 .burst_16bit = 2,
1249 .burst_32bit = 1,
1250 .reg = COH901318_CX_CTRL_BURST_COUNT_4_BYTES,
1251 },
1252 {
1253 .burst_8bit = 2,
1254 .burst_16bit = 1,
1255 .burst_32bit = 0,
1256 .reg = COH901318_CX_CTRL_BURST_COUNT_2_BYTES,
1257 },
1258 {
1259 .burst_8bit = 1,
1260 .burst_16bit = 0,
1261 .burst_32bit = 0,
1262 .reg = COH901318_CX_CTRL_BURST_COUNT_1_BYTE,
1263 },
1264 };
1265
1266 static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
1267 struct dma_slave_config *config)
1268 {
1269 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1270 dma_addr_t addr;
1271 enum dma_slave_buswidth addr_width;
1272 u32 maxburst;
1273 u32 runtime_ctrl = 0;
1274 int i = 0;
1275
1276 /* We only support mem to per or per to mem transfers */
1277 if (config->direction == DMA_FROM_DEVICE) {
1278 addr = config->src_addr;
1279 addr_width = config->src_addr_width;
1280 maxburst = config->src_maxburst;
1281 } else if (config->direction == DMA_TO_DEVICE) {
1282 addr = config->dst_addr;
1283 addr_width = config->dst_addr_width;
1284 maxburst = config->dst_maxburst;
1285 } else {
1286 dev_err(COHC_2_DEV(cohc), "illegal channel mode\n");
1287 return;
1288 }
1289
1290 dev_dbg(COHC_2_DEV(cohc), "configure channel for %d byte transfers\n",
1291 addr_width);
1292 switch (addr_width) {
1293 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1294 runtime_ctrl |=
1295 COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS |
1296 COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS;
1297
1298 while (i < ARRAY_SIZE(burst_sizes)) {
1299 if (burst_sizes[i].burst_8bit <= maxburst)
1300 break;
1301 i++;
1302 }
1303
1304 break;
1305 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1306 runtime_ctrl |=
1307 COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS |
1308 COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS;
1309
1310 while (i < ARRAY_SIZE(burst_sizes)) {
1311 if (burst_sizes[i].burst_16bit <= maxburst)
1312 break;
1313 i++;
1314 }
1315
1316 break;
1317 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1318 /* Direction doesn't matter here, it's 32/32 bits */
1319 runtime_ctrl |=
1320 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1321 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS;
1322
1323 while (i < ARRAY_SIZE(burst_sizes)) {
1324 if (burst_sizes[i].burst_32bit <= maxburst)
1325 break;
1326 i++;
1327 }
1328
1329 break;
1330 default:
1331 dev_err(COHC_2_DEV(cohc),
1332 "bad runtimeconfig: alien address width\n");
1333 return;
1334 }
1335
1336 runtime_ctrl |= burst_sizes[i].reg;
1337 dev_dbg(COHC_2_DEV(cohc),
1338 "selected burst size %d bytes for address width %d bytes, maxburst %d\n",
1339 burst_sizes[i].burst_8bit, addr_width, maxburst);
1340
1341 cohc->runtime_addr = addr;
1342 cohc->runtime_ctrl = runtime_ctrl;
1343 }
1344
1345 static int
1346 coh901318_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1347 unsigned long arg)
1348 {
1349 unsigned long flags;
1350 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1351 struct coh901318_desc *cohd;
1352 void __iomem *virtbase = cohc->base->virtbase;
1353
1354 if (cmd == DMA_SLAVE_CONFIG) {
1355 struct dma_slave_config *config =
1356 (struct dma_slave_config *) arg;
1357
1358 coh901318_dma_set_runtimeconfig(chan, config);
1359 return 0;
1360 }
1361
1362 if (cmd == DMA_PAUSE) {
1363 coh901318_pause(chan);
1364 return 0;
1365 }
1366
1367 if (cmd == DMA_RESUME) {
1368 coh901318_resume(chan);
1369 return 0;
1370 }
1371
1372 if (cmd != DMA_TERMINATE_ALL)
1373 return -ENXIO;
1374
1375 /* The remainder of this function terminates the transfer */
1376 coh901318_pause(chan);
1377 spin_lock_irqsave(&cohc->lock, flags);
1378
1379 /* Clear any pending BE or TC interrupt */
1380 if (cohc->id < 32) {
1381 writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
1382 writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
1383 } else {
1384 writel(1 << (cohc->id - 32), virtbase +
1385 COH901318_BE_INT_CLEAR2);
1386 writel(1 << (cohc->id - 32), virtbase +
1387 COH901318_TC_INT_CLEAR2);
1388 }
1389
1390 enable_powersave(cohc);
1391
1392 while ((cohd = coh901318_first_active_get(cohc))) {
1393 /* release the lli allocation*/
1394 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
1395
1396 /* return desc to free-list */
1397 coh901318_desc_remove(cohd);
1398 coh901318_desc_free(cohc, cohd);
1399 }
1400
1401 while ((cohd = coh901318_first_queued(cohc))) {
1402 /* release the lli allocation*/
1403 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
1404
1405 /* return desc to free-list */
1406 coh901318_desc_remove(cohd);
1407 coh901318_desc_free(cohc, cohd);
1408 }
1409
1410
1411 cohc->nbr_active_done = 0;
1412 cohc->busy = 0;
1413
1414 spin_unlock_irqrestore(&cohc->lock, flags);
1415
1416 return 0;
1417 }
1418
1419 void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
1420 struct coh901318_base *base)
1421 {
1422 int chans_i;
1423 int i = 0;
1424 struct coh901318_chan *cohc;
1425
1426 INIT_LIST_HEAD(&dma->channels);
1427
1428 for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) {
1429 for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) {
1430 cohc = &base->chans[i];
1431
1432 cohc->base = base;
1433 cohc->chan.device = dma;
1434 cohc->id = i;
1435
1436 /* TODO: do we really need this lock if only one
1437 * client is connected to each channel?
1438 */
1439
1440 spin_lock_init(&cohc->lock);
1441
1442 cohc->nbr_active_done = 0;
1443 cohc->busy = 0;
1444 INIT_LIST_HEAD(&cohc->free);
1445 INIT_LIST_HEAD(&cohc->active);
1446 INIT_LIST_HEAD(&cohc->queue);
1447
1448 tasklet_init(&cohc->tasklet, dma_tasklet,
1449 (unsigned long) cohc);
1450
1451 list_add_tail(&cohc->chan.device_node,
1452 &dma->channels);
1453 }
1454 }
1455 }
1456
1457 static int __init coh901318_probe(struct platform_device *pdev)
1458 {
1459 int err = 0;
1460 struct coh901318_platform *pdata;
1461 struct coh901318_base *base;
1462 int irq;
1463 struct resource *io;
1464
1465 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1466 if (!io)
1467 goto err_get_resource;
1468
1469 /* Map DMA controller registers to virtual memory */
1470 if (request_mem_region(io->start,
1471 resource_size(io),
1472 pdev->dev.driver->name) == NULL) {
1473 err = -EBUSY;
1474 goto err_request_mem;
1475 }
1476
1477 pdata = pdev->dev.platform_data;
1478 if (!pdata)
1479 goto err_no_platformdata;
1480
1481 base = kmalloc(ALIGN(sizeof(struct coh901318_base), 4) +
1482 pdata->max_channels *
1483 sizeof(struct coh901318_chan),
1484 GFP_KERNEL);
1485 if (!base)
1486 goto err_alloc_coh_dma_channels;
1487
1488 base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4);
1489
1490 base->virtbase = ioremap(io->start, resource_size(io));
1491 if (!base->virtbase) {
1492 err = -ENOMEM;
1493 goto err_no_ioremap;
1494 }
1495
1496 base->dev = &pdev->dev;
1497 base->platform = pdata;
1498 spin_lock_init(&base->pm.lock);
1499 base->pm.started_channels = 0;
1500
1501 COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base);
1502
1503 platform_set_drvdata(pdev, base);
1504
1505 irq = platform_get_irq(pdev, 0);
1506 if (irq < 0)
1507 goto err_no_irq;
1508
1509 err = request_irq(irq, dma_irq_handler, IRQF_DISABLED,
1510 "coh901318", base);
1511 if (err) {
1512 dev_crit(&pdev->dev,
1513 "Cannot allocate IRQ for DMA controller!\n");
1514 goto err_request_irq;
1515 }
1516
1517 err = coh901318_pool_create(&base->pool, &pdev->dev,
1518 sizeof(struct coh901318_lli),
1519 32);
1520 if (err)
1521 goto err_pool_create;
1522
1523 /* init channels for device transfers */
1524 coh901318_base_init(&base->dma_slave, base->platform->chans_slave,
1525 base);
1526
1527 dma_cap_zero(base->dma_slave.cap_mask);
1528 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
1529
1530 base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources;
1531 base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources;
1532 base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg;
1533 base->dma_slave.device_tx_status = coh901318_tx_status;
1534 base->dma_slave.device_issue_pending = coh901318_issue_pending;
1535 base->dma_slave.device_control = coh901318_control;
1536 base->dma_slave.dev = &pdev->dev;
1537
1538 err = dma_async_device_register(&base->dma_slave);
1539
1540 if (err)
1541 goto err_register_slave;
1542
1543 /* init channels for memcpy */
1544 coh901318_base_init(&base->dma_memcpy, base->platform->chans_memcpy,
1545 base);
1546
1547 dma_cap_zero(base->dma_memcpy.cap_mask);
1548 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
1549
1550 base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources;
1551 base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources;
1552 base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy;
1553 base->dma_memcpy.device_tx_status = coh901318_tx_status;
1554 base->dma_memcpy.device_issue_pending = coh901318_issue_pending;
1555 base->dma_memcpy.device_control = coh901318_control;
1556 base->dma_memcpy.dev = &pdev->dev;
1557 /*
1558 * This controller can only access address at even 32bit boundaries,
1559 * i.e. 2^2
1560 */
1561 base->dma_memcpy.copy_align = 2;
1562 err = dma_async_device_register(&base->dma_memcpy);
1563
1564 if (err)
1565 goto err_register_memcpy;
1566
1567 dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n",
1568 (u32) base->virtbase);
1569
1570 return err;
1571
1572 err_register_memcpy:
1573 dma_async_device_unregister(&base->dma_slave);
1574 err_register_slave:
1575 coh901318_pool_destroy(&base->pool);
1576 err_pool_create:
1577 free_irq(platform_get_irq(pdev, 0), base);
1578 err_request_irq:
1579 err_no_irq:
1580 iounmap(base->virtbase);
1581 err_no_ioremap:
1582 kfree(base);
1583 err_alloc_coh_dma_channels:
1584 err_no_platformdata:
1585 release_mem_region(pdev->resource->start,
1586 resource_size(pdev->resource));
1587 err_request_mem:
1588 err_get_resource:
1589 return err;
1590 }
1591
1592 static int __exit coh901318_remove(struct platform_device *pdev)
1593 {
1594 struct coh901318_base *base = platform_get_drvdata(pdev);
1595
1596 dma_async_device_unregister(&base->dma_memcpy);
1597 dma_async_device_unregister(&base->dma_slave);
1598 coh901318_pool_destroy(&base->pool);
1599 free_irq(platform_get_irq(pdev, 0), base);
1600 iounmap(base->virtbase);
1601 kfree(base);
1602 release_mem_region(pdev->resource->start,
1603 resource_size(pdev->resource));
1604 return 0;
1605 }
1606
1607
1608 static struct platform_driver coh901318_driver = {
1609 .remove = __exit_p(coh901318_remove),
1610 .driver = {
1611 .name = "coh901318",
1612 },
1613 };
1614
1615 int __init coh901318_init(void)
1616 {
1617 return platform_driver_probe(&coh901318_driver, coh901318_probe);
1618 }
1619 subsys_initcall(coh901318_init);
1620
1621 void __exit coh901318_exit(void)
1622 {
1623 platform_driver_unregister(&coh901318_driver);
1624 }
1625 module_exit(coh901318_exit);
1626
1627 MODULE_LICENSE("GPL");
1628 MODULE_AUTHOR("Per Friden");