?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
tty/serial: atmel_serial: whitespace and braces modifications
[zen-stable.git] / drivers / scsi / be2iscsi / be_main.h
blob5ce5170254caaabd2ce81d0438e5523c001ffaca
1 /**
2 * Copyright (C) 2005 - 2011 Emulex
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
11 *
12 * Contact Information:
13 * linux-drivers@emulex.com
14 *
15 * Emulex
16 * 3333 Susan Street
17 * Costa Mesa, CA 92626
18 */
19
20 #ifndef _BEISCSI_MAIN_
21 #define _BEISCSI_MAIN_
22
23 #include <linux/kernel.h>
24 #include <linux/pci.h>
25 #include <linux/if_ether.h>
26 #include <linux/in.h>
27 #include <scsi/scsi.h>
28 #include <scsi/scsi_cmnd.h>
29 #include <scsi/scsi_device.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/iscsi_proto.h>
32 #include <scsi/libiscsi.h>
33 #include <scsi/scsi_transport_iscsi.h>
34
35 #include "be.h"
36 #define DRV_NAME "be2iscsi"
37 #define BUILD_STR "2.103.298.0"
38 #define BE_NAME "ServerEngines BladeEngine2" \
39 "Linux iSCSI Driver version" BUILD_STR
40 #define DRV_DESC BE_NAME " " "Driver"
41
42 #define BE_VENDOR_ID 0x19A2
43 /* DEVICE ID's for BE2 */
44 #define BE_DEVICE_ID1 0x212
45 #define OC_DEVICE_ID1 0x702
46 #define OC_DEVICE_ID2 0x703
47
48 /* DEVICE ID's for BE3 */
49 #define BE_DEVICE_ID2 0x222
50 #define OC_DEVICE_ID3 0x712
51
52 #define BE2_IO_DEPTH 1024
53 #define BE2_MAX_SESSIONS 256
54 #define BE2_CMDS_PER_CXN 128
55 #define BE2_TMFS 16
56 #define BE2_NOPOUT_REQ 16
57 #define BE2_SGE 32
58 #define BE2_DEFPDU_HDR_SZ 64
59 #define BE2_DEFPDU_DATA_SZ 8192
60
61 #define MAX_CPUS 31
62 #define BEISCSI_SGLIST_ELEMENTS 30
63
64 #define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */
65 #define BEISCSI_MAX_SECTORS 2048 /* scsi_host->max_sectors */
66
67 #define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */
68 #define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */
69 #define BEISCSI_NUM_DEVICES_SUPPORTED 0x01
70 #define BEISCSI_MAX_FRAGS_INIT 192
71 #define BE_NUM_MSIX_ENTRIES 1
72
73 #define MPU_EP_CONTROL 0
74 #define MPU_EP_SEMAPHORE 0xac
75 #define BE2_SOFT_RESET 0x5c
76 #define BE2_PCI_ONLINE0 0xb0
77 #define BE2_PCI_ONLINE1 0xb4
78 #define BE2_SET_RESET 0x80
79 #define BE2_MPU_IRAM_ONLINE 0x00000080
80
81 #define BE_SENSE_INFO_SIZE 258
82 #define BE_ISCSI_PDU_HEADER_SIZE 64
83 #define BE_MIN_MEM_SIZE 16384
84 #define MAX_CMD_SZ 65536
85 #define IIOC_SCSI_DATA 0x05 /* Write Operation */
86
87 #define DBG_LVL 0x00000001
88 #define DBG_LVL_1 0x00000001
89 #define DBG_LVL_2 0x00000002
90 #define DBG_LVL_3 0x00000004
91 #define DBG_LVL_4 0x00000008
92 #define DBG_LVL_5 0x00000010
93 #define DBG_LVL_6 0x00000020
94 #define DBG_LVL_7 0x00000040
95 #define DBG_LVL_8 0x00000080
96
97 #define SE_DEBUG(debug_mask, fmt, args...) \
98 do { \
99 if (debug_mask & DBG_LVL) { \
100 printk(KERN_ERR "(%s():%d):", __func__, __LINE__);\
101 printk(fmt, ##args); \
102 } \
103 } while (0);
104
105 #define BE_ADAPTER_UP 0x00000000
106 #define BE_ADAPTER_LINK_DOWN 0x00000001
107 /**
108 * hardware needs the async PDU buffers to be posted in multiples of 8
109 * So have atleast 8 of them by default
110 */
111
112 #define HWI_GET_ASYNC_PDU_CTX(phwi) (phwi->phwi_ctxt->pasync_ctx)
113
114 /********* Memory BAR register ************/
115 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
116 /**
117 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
118 * Disable" may still globally block interrupts in addition to individual
119 * interrupt masks; a mechanism for the device driver to block all interrupts
120 * atomically without having to arbitrate for the PCI Interrupt Disable bit
121 * with the OS.
122 */
123 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
124
125 /********* ISR0 Register offset **********/
126 #define CEV_ISR0_OFFSET 0xC18
127 #define CEV_ISR_SIZE 4
128
129 /**
130 * Macros for reading/writing a protection domain or CSR registers
131 * in BladeEngine.
132 */
133
134 #define DB_TXULP0_OFFSET 0x40
135 #define DB_RXULP0_OFFSET 0xA0
136 /********* Event Q door bell *************/
137 #define DB_EQ_OFFSET DB_CQ_OFFSET
138 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
139 /* Clear the interrupt for this eq */
140 #define DB_EQ_CLR_SHIFT (9) /* bit 9 */
141 /* Must be 1 */
142 #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
143 /* Number of event entries processed */
144 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
145 /* Rearm bit */
146 #define DB_EQ_REARM_SHIFT (29) /* bit 29 */
147
148 /********* Compl Q door bell *************/
149 #define DB_CQ_OFFSET 0x120
150 #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
151 /* Number of event entries processed */
152 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
153 /* Rearm bit */
154 #define DB_CQ_REARM_SHIFT (29) /* bit 29 */
155
156 #define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr)
157 #define HWI_GET_DEF_BUFQ_ID(pc) (((struct hwi_controller *)\
158 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data.id)
159 #define HWI_GET_DEF_HDRQ_ID(pc) (((struct hwi_controller *)\
160 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr.id)
161
162 #define PAGES_REQUIRED(x) \
163 ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE))
164
165 enum be_mem_enum {
166 HWI_MEM_ADDN_CONTEXT,
167 HWI_MEM_WRB,
168 HWI_MEM_WRBH,
169 HWI_MEM_SGLH,
170 HWI_MEM_SGE,
171 HWI_MEM_ASYNC_HEADER_BUF, /* 5 */
172 HWI_MEM_ASYNC_DATA_BUF,
173 HWI_MEM_ASYNC_HEADER_RING,
174 HWI_MEM_ASYNC_DATA_RING,
175 HWI_MEM_ASYNC_HEADER_HANDLE,
176 HWI_MEM_ASYNC_DATA_HANDLE, /* 10 */
177 HWI_MEM_ASYNC_PDU_CONTEXT,
178 ISCSI_MEM_GLOBAL_HEADER,
179 SE_MEM_MAX
180 };
181
182 struct be_bus_address32 {
183 unsigned int address_lo;
184 unsigned int address_hi;
185 };
186
187 struct be_bus_address64 {
188 unsigned long long address;
189 };
190
191 struct be_bus_address {
192 union {
193 struct be_bus_address32 a32;
194 struct be_bus_address64 a64;
195 } u;
196 };
197
198 struct mem_array {
199 struct be_bus_address bus_address; /* Bus address of location */
200 void *virtual_address; /* virtual address to the location */
201 unsigned int size; /* Size required by memory block */
202 };
203
204 struct be_mem_descriptor {
205 unsigned int index; /* Index of this memory parameter */
206 unsigned int category; /* type indicates cached/non-cached */
207 unsigned int num_elements; /* number of elements in this
208 * descriptor
209 */
210 unsigned int alignment_mask; /* Alignment mask for this block */
211 unsigned int size_in_bytes; /* Size required by memory block */
212 struct mem_array *mem_array;
213 };
214
215 struct sgl_handle {
216 unsigned int sgl_index;
217 unsigned int type;
218 unsigned int cid;
219 struct iscsi_task *task;
220 struct iscsi_sge *pfrag;
221 };
222
223 struct hba_parameters {
224 unsigned int ios_per_ctrl;
225 unsigned int cxns_per_ctrl;
226 unsigned int asyncpdus_per_ctrl;
227 unsigned int icds_per_ctrl;
228 unsigned int num_sge_per_io;
229 unsigned int defpdu_hdr_sz;
230 unsigned int defpdu_data_sz;
231 unsigned int num_cq_entries;
232 unsigned int num_eq_entries;
233 unsigned int wrbs_per_cxn;
234 unsigned int crashmode;
235 unsigned int hba_num;
236
237 unsigned int mgmt_ws_sz;
238 unsigned int hwi_ws_sz;
239
240 unsigned int eto;
241 unsigned int ldto;
242
243 unsigned int dbg_flags;
244 unsigned int num_cxn;
245
246 unsigned int eq_timer;
247 /**
248 * These are calculated from other params. They're here
249 * for debug purposes
250 */
251 unsigned int num_mcc_pages;
252 unsigned int num_mcc_cq_pages;
253 unsigned int num_cq_pages;
254 unsigned int num_eq_pages;
255
256 unsigned int num_async_pdu_buf_pages;
257 unsigned int num_async_pdu_buf_sgl_pages;
258 unsigned int num_async_pdu_buf_cq_pages;
259
260 unsigned int num_async_pdu_hdr_pages;
261 unsigned int num_async_pdu_hdr_sgl_pages;
262 unsigned int num_async_pdu_hdr_cq_pages;
263
264 unsigned int num_sge;
265 };
266
267 struct invalidate_command_table {
268 unsigned short icd;
269 unsigned short cid;
270 } __packed;
271
272 struct beiscsi_hba {
273 struct hba_parameters params;
274 struct hwi_controller *phwi_ctrlr;
275 unsigned int mem_req[SE_MEM_MAX];
276 /* PCI BAR mapped addresses */
277 u8 __iomem *csr_va; /* CSR */
278 u8 __iomem *db_va; /* Door Bell */
279 u8 __iomem *pci_va; /* PCI Config */
280 struct be_bus_address csr_pa; /* CSR */
281 struct be_bus_address db_pa; /* CSR */
282 struct be_bus_address pci_pa; /* CSR */
283 /* PCI representation of our HBA */
284 struct pci_dev *pcidev;
285 unsigned int state;
286 unsigned short asic_revision;
287 unsigned int num_cpus;
288 unsigned int nxt_cqid;
289 struct msix_entry msix_entries[MAX_CPUS + 1];
290 bool msix_enabled;
291 struct be_mem_descriptor *init_mem;
292
293 unsigned short io_sgl_alloc_index;
294 unsigned short io_sgl_free_index;
295 unsigned short io_sgl_hndl_avbl;
296 struct sgl_handle **io_sgl_hndl_base;
297 struct sgl_handle **sgl_hndl_array;
298
299 unsigned short eh_sgl_alloc_index;
300 unsigned short eh_sgl_free_index;
301 unsigned short eh_sgl_hndl_avbl;
302 struct sgl_handle **eh_sgl_hndl_base;
303 spinlock_t io_sgl_lock;
304 spinlock_t mgmt_sgl_lock;
305 spinlock_t isr_lock;
306 unsigned int age;
307 unsigned short avlbl_cids;
308 unsigned short cid_alloc;
309 unsigned short cid_free;
310 struct beiscsi_conn *conn_table[BE2_MAX_SESSIONS * 2];
311 struct list_head hba_queue;
312 unsigned short *cid_array;
313 struct iscsi_endpoint **ep_array;
314 struct iscsi_boot_kset *boot_kset;
315 struct Scsi_Host *shost;
316 struct {
317 /**
318 * group together since they are used most frequently
319 * for cid to cri conversion
320 */
321 unsigned int iscsi_cid_start;
322 unsigned int phys_port;
323
324 unsigned int isr_offset;
325 unsigned int iscsi_icd_start;
326 unsigned int iscsi_cid_count;
327 unsigned int iscsi_icd_count;
328 unsigned int pci_function;
329
330 unsigned short cid_alloc;
331 unsigned short cid_free;
332 unsigned short avlbl_cids;
333 unsigned short iscsi_features;
334 spinlock_t cid_lock;
335 } fw_config;
336
337 u8 mac_address[ETH_ALEN];
338 unsigned short todo_cq;
339 unsigned short todo_mcc_cq;
340 char wq_name[20];
341 struct workqueue_struct *wq; /* The actuak work queue */
342 struct work_struct work_cqs; /* The work being queued */
343 struct be_ctrl_info ctrl;
344 unsigned int generation;
345 unsigned int read_mac_address;
346 struct mgmt_session_info boot_sess;
347 struct invalidate_command_table inv_tbl[128];
348
349 };
350
351 struct beiscsi_session {
352 struct pci_pool *bhs_pool;
353 };
354
355 /**
356 * struct beiscsi_conn - iscsi connection structure
357 */
358 struct beiscsi_conn {
359 struct iscsi_conn *conn;
360 struct beiscsi_hba *phba;
361 u32 exp_statsn;
362 u32 beiscsi_conn_cid;
363 struct beiscsi_endpoint *ep;
364 unsigned short login_in_progress;
365 struct wrb_handle *plogin_wrb_handle;
366 struct sgl_handle *plogin_sgl_handle;
367 struct beiscsi_session *beiscsi_sess;
368 struct iscsi_task *task;
369 };
370
371 /* This structure is used by the chip */
372 struct pdu_data_out {
373 u32 dw[12];
374 };
375 /**
376 * Pseudo amap definition in which each bit of the actual structure is defined
377 * as a byte: used to calculate offset/shift/mask of each field
378 */
379 struct amap_pdu_data_out {
380 u8 opcode[6]; /* opcode */
381 u8 rsvd0[2]; /* should be 0 */
382 u8 rsvd1[7];
383 u8 final_bit; /* F bit */
384 u8 rsvd2[16];
385 u8 ahs_length[8]; /* no AHS */
386 u8 data_len_hi[8];
387 u8 data_len_lo[16]; /* DataSegmentLength */
388 u8 lun[64];
389 u8 itt[32]; /* ITT; initiator task tag */
390 u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */
391 u8 rsvd3[32];
392 u8 exp_stat_sn[32];
393 u8 rsvd4[32];
394 u8 data_sn[32];
395 u8 buffer_offset[32];
396 u8 rsvd5[32];
397 };
398
399 struct be_cmd_bhs {
400 struct iscsi_scsi_req iscsi_hdr;
401 unsigned char pad1[16];
402 struct pdu_data_out iscsi_data_pdu;
403 unsigned char pad2[BE_SENSE_INFO_SIZE -
404 sizeof(struct pdu_data_out)];
405 };
406
407 struct beiscsi_io_task {
408 struct wrb_handle *pwrb_handle;
409 struct sgl_handle *psgl_handle;
410 struct beiscsi_conn *conn;
411 struct scsi_cmnd *scsi_cmnd;
412 unsigned int cmd_sn;
413 unsigned int flags;
414 unsigned short cid;
415 unsigned short header_len;
416 itt_t libiscsi_itt;
417 struct be_cmd_bhs *cmd_bhs;
418 struct be_bus_address bhs_pa;
419 unsigned short bhs_len;
420 };
421
422 struct be_nonio_bhs {
423 struct iscsi_hdr iscsi_hdr;
424 unsigned char pad1[16];
425 struct pdu_data_out iscsi_data_pdu;
426 unsigned char pad2[BE_SENSE_INFO_SIZE -
427 sizeof(struct pdu_data_out)];
428 };
429
430 struct be_status_bhs {
431 struct iscsi_scsi_req iscsi_hdr;
432 unsigned char pad1[16];
433 /**
434 * The plus 2 below is to hold the sense info length that gets
435 * DMA'ed by RxULP
436 */
437 unsigned char sense_info[BE_SENSE_INFO_SIZE];
438 };
439
440 struct iscsi_sge {
441 u32 dw[4];
442 };
443
444 /**
445 * Pseudo amap definition in which each bit of the actual structure is defined
446 * as a byte: used to calculate offset/shift/mask of each field
447 */
448 struct amap_iscsi_sge {
449 u8 addr_hi[32];
450 u8 addr_lo[32];
451 u8 sge_offset[22]; /* DWORD 2 */
452 u8 rsvd0[9]; /* DWORD 2 */
453 u8 last_sge; /* DWORD 2 */
454 u8 len[17]; /* DWORD 3 */
455 u8 rsvd1[15]; /* DWORD 3 */
456 };
457
458 struct beiscsi_offload_params {
459 u32 dw[5];
460 };
461
462 #define OFFLD_PARAMS_ERL 0x00000003
463 #define OFFLD_PARAMS_DDE 0x00000004
464 #define OFFLD_PARAMS_HDE 0x00000008
465 #define OFFLD_PARAMS_IR2T 0x00000010
466 #define OFFLD_PARAMS_IMD 0x00000020
467
468 /**
469 * Pseudo amap definition in which each bit of the actual structure is defined
470 * as a byte: used to calculate offset/shift/mask of each field
471 */
472 struct amap_beiscsi_offload_params {
473 u8 max_burst_length[32];
474 u8 max_send_data_segment_length[32];
475 u8 first_burst_length[32];
476 u8 erl[2];
477 u8 dde[1];
478 u8 hde[1];
479 u8 ir2t[1];
480 u8 imd[1];
481 u8 pad[26];
482 u8 exp_statsn[32];
483 };
484
485 /* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
486 struct beiscsi_hba *phba, struct sol_cqe *psol);*/
487
488 struct async_pdu_handle {
489 struct list_head link;
490 struct be_bus_address pa;
491 void *pbuffer;
492 unsigned int consumed;
493 unsigned char index;
494 unsigned char is_header;
495 unsigned short cri;
496 unsigned long buffer_len;
497 };
498
499 struct hwi_async_entry {
500 struct {
501 unsigned char hdr_received;
502 unsigned char hdr_len;
503 unsigned short bytes_received;
504 unsigned int bytes_needed;
505 struct list_head list;
506 } wait_queue;
507
508 struct list_head header_busy_list;
509 struct list_head data_busy_list;
510 };
511
512 struct hwi_async_pdu_context {
513 struct {
514 struct be_bus_address pa_base;
515 void *va_base;
516 void *ring_base;
517 struct async_pdu_handle *handle_base;
518
519 unsigned int host_write_ptr;
520 unsigned int ep_read_ptr;
521 unsigned int writables;
522
523 unsigned int free_entries;
524 unsigned int busy_entries;
525 unsigned int buffer_size;
526 unsigned int num_entries;
527
528 struct list_head free_list;
529 } async_header;
530
531 struct {
532 struct be_bus_address pa_base;
533 void *va_base;
534 void *ring_base;
535 struct async_pdu_handle *handle_base;
536
537 unsigned int host_write_ptr;
538 unsigned int ep_read_ptr;
539 unsigned int writables;
540
541 unsigned int free_entries;
542 unsigned int busy_entries;
543 unsigned int buffer_size;
544 struct list_head free_list;
545 unsigned int num_entries;
546 } async_data;
547
548 /**
549 * This is a varying size list! Do not add anything
550 * after this entry!!
551 */
552 struct hwi_async_entry async_entry[BE2_MAX_SESSIONS * 2];
553 };
554
555 #define PDUCQE_CODE_MASK 0x0000003F
556 #define PDUCQE_DPL_MASK 0xFFFF0000
557 #define PDUCQE_INDEX_MASK 0x0000FFFF
558
559 struct i_t_dpdu_cqe {
560 u32 dw[4];
561 } __packed;
562
563 /**
564 * Pseudo amap definition in which each bit of the actual structure is defined
565 * as a byte: used to calculate offset/shift/mask of each field
566 */
567 struct amap_i_t_dpdu_cqe {
568 u8 db_addr_hi[32];
569 u8 db_addr_lo[32];
570 u8 code[6];
571 u8 cid[10];
572 u8 dpl[16];
573 u8 index[16];
574 u8 num_cons[10];
575 u8 rsvd0[4];
576 u8 final;
577 u8 valid;
578 } __packed;
579
580 #define CQE_VALID_MASK 0x80000000
581 #define CQE_CODE_MASK 0x0000003F
582 #define CQE_CID_MASK 0x0000FFC0
583
584 #define EQE_VALID_MASK 0x00000001
585 #define EQE_MAJORCODE_MASK 0x0000000E
586 #define EQE_RESID_MASK 0xFFFF0000
587
588 struct be_eq_entry {
589 u32 dw[1];
590 } __packed;
591
592 /**
593 * Pseudo amap definition in which each bit of the actual structure is defined
594 * as a byte: used to calculate offset/shift/mask of each field
595 */
596 struct amap_eq_entry {
597 u8 valid; /* DWORD 0 */
598 u8 major_code[3]; /* DWORD 0 */
599 u8 minor_code[12]; /* DWORD 0 */
600 u8 resource_id[16]; /* DWORD 0 */
601
602 } __packed;
603
604 struct cq_db {
605 u32 dw[1];
606 } __packed;
607
608 /**
609 * Pseudo amap definition in which each bit of the actual structure is defined
610 * as a byte: used to calculate offset/shift/mask of each field
611 */
612 struct amap_cq_db {
613 u8 qid[10];
614 u8 event[1];
615 u8 rsvd0[5];
616 u8 num_popped[13];
617 u8 rearm[1];
618 u8 rsvd1[2];
619 } __packed;
620
621 void beiscsi_process_eq(struct beiscsi_hba *phba);
622
623 struct iscsi_wrb {
624 u32 dw[16];
625 } __packed;
626
627 #define WRB_TYPE_MASK 0xF0000000
628
629 /**
630 * Pseudo amap definition in which each bit of the actual structure is defined
631 * as a byte: used to calculate offset/shift/mask of each field
632 */
633 struct amap_iscsi_wrb {
634 u8 lun[14]; /* DWORD 0 */
635 u8 lt; /* DWORD 0 */
636 u8 invld; /* DWORD 0 */
637 u8 wrb_idx[8]; /* DWORD 0 */
638 u8 dsp; /* DWORD 0 */
639 u8 dmsg; /* DWORD 0 */
640 u8 undr_run; /* DWORD 0 */
641 u8 over_run; /* DWORD 0 */
642 u8 type[4]; /* DWORD 0 */
643 u8 ptr2nextwrb[8]; /* DWORD 1 */
644 u8 r2t_exp_dtl[24]; /* DWORD 1 */
645 u8 sgl_icd_idx[12]; /* DWORD 2 */
646 u8 rsvd0[20]; /* DWORD 2 */
647 u8 exp_data_sn[32]; /* DWORD 3 */
648 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
649 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
650 u8 cmdsn_itt[32]; /* DWORD 6 */
651 u8 dif_ref_tag[32]; /* DWORD 7 */
652 u8 sge0_addr_hi[32]; /* DWORD 8 */
653 u8 sge0_addr_lo[32]; /* DWORD 9 */
654 u8 sge0_offset[22]; /* DWORD 10 */
655 u8 pbs; /* DWORD 10 */
656 u8 dif_mode[2]; /* DWORD 10 */
657 u8 rsvd1[6]; /* DWORD 10 */
658 u8 sge0_last; /* DWORD 10 */
659 u8 sge0_len[17]; /* DWORD 11 */
660 u8 dif_meta_tag[14]; /* DWORD 11 */
661 u8 sge0_in_ddr; /* DWORD 11 */
662 u8 sge1_addr_hi[32]; /* DWORD 12 */
663 u8 sge1_addr_lo[32]; /* DWORD 13 */
664 u8 sge1_r2t_offset[22]; /* DWORD 14 */
665 u8 rsvd2[9]; /* DWORD 14 */
666 u8 sge1_last; /* DWORD 14 */
667 u8 sge1_len[17]; /* DWORD 15 */
668 u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
669 u8 rsvd3[2]; /* DWORD 15 */
670 u8 sge1_in_ddr; /* DWORD 15 */
671
672 } __packed;
673
674 struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid);
675 void
676 free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
677
678 void beiscsi_process_all_cqs(struct work_struct *work);
679
680 struct pdu_nop_out {
681 u32 dw[12];
682 };
683
684 /**
685 * Pseudo amap definition in which each bit of the actual structure is defined
686 * as a byte: used to calculate offset/shift/mask of each field
687 */
688 struct amap_pdu_nop_out {
689 u8 opcode[6]; /* opcode 0x00 */
690 u8 i_bit; /* I Bit */
691 u8 x_bit; /* reserved; should be 0 */
692 u8 fp_bit_filler1[7];
693 u8 f_bit; /* always 1 */
694 u8 reserved1[16];
695 u8 ahs_length[8]; /* no AHS */
696 u8 data_len_hi[8];
697 u8 data_len_lo[16]; /* DataSegmentLength */
698 u8 lun[64];
699 u8 itt[32]; /* initiator id for ping or 0xffffffff */
700 u8 ttt[32]; /* target id for ping or 0xffffffff */
701 u8 cmd_sn[32];
702 u8 exp_stat_sn[32];
703 u8 reserved5[128];
704 };
705
706 #define PDUBASE_OPCODE_MASK 0x0000003F
707 #define PDUBASE_DATALENHI_MASK 0x0000FF00
708 #define PDUBASE_DATALENLO_MASK 0xFFFF0000
709
710 struct pdu_base {
711 u32 dw[16];
712 } __packed;
713
714 /**
715 * Pseudo amap definition in which each bit of the actual structure is defined
716 * as a byte: used to calculate offset/shift/mask of each field
717 */
718 struct amap_pdu_base {
719 u8 opcode[6];
720 u8 i_bit; /* immediate bit */
721 u8 x_bit; /* reserved, always 0 */
722 u8 reserved1[24]; /* opcode-specific fields */
723 u8 ahs_length[8]; /* length units is 4 byte words */
724 u8 data_len_hi[8];
725 u8 data_len_lo[16]; /* DatasegmentLength */
726 u8 lun[64]; /* lun or opcode-specific fields */
727 u8 itt[32]; /* initiator task tag */
728 u8 reserved4[224];
729 };
730
731 struct iscsi_target_context_update_wrb {
732 u32 dw[16];
733 } __packed;
734
735 /**
736 * Pseudo amap definition in which each bit of the actual structure is defined
737 * as a byte: used to calculate offset/shift/mask of each field
738 */
739 struct amap_iscsi_target_context_update_wrb {
740 u8 lun[14]; /* DWORD 0 */
741 u8 lt; /* DWORD 0 */
742 u8 invld; /* DWORD 0 */
743 u8 wrb_idx[8]; /* DWORD 0 */
744 u8 dsp; /* DWORD 0 */
745 u8 dmsg; /* DWORD 0 */
746 u8 undr_run; /* DWORD 0 */
747 u8 over_run; /* DWORD 0 */
748 u8 type[4]; /* DWORD 0 */
749 u8 ptr2nextwrb[8]; /* DWORD 1 */
750 u8 max_burst_length[19]; /* DWORD 1 */
751 u8 rsvd0[5]; /* DWORD 1 */
752 u8 rsvd1[15]; /* DWORD 2 */
753 u8 max_send_data_segment_length[17]; /* DWORD 2 */
754 u8 first_burst_length[14]; /* DWORD 3 */
755 u8 rsvd2[2]; /* DWORD 3 */
756 u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */
757 u8 rsvd3[5]; /* DWORD 3 */
758 u8 session_state[3]; /* DWORD 3 */
759 u8 rsvd4[16]; /* DWORD 4 */
760 u8 tx_jumbo; /* DWORD 4 */
761 u8 hde; /* DWORD 4 */
762 u8 dde; /* DWORD 4 */
763 u8 erl[2]; /* DWORD 4 */
764 u8 domain_id[5]; /* DWORD 4 */
765 u8 mode; /* DWORD 4 */
766 u8 imd; /* DWORD 4 */
767 u8 ir2t; /* DWORD 4 */
768 u8 notpredblq[2]; /* DWORD 4 */
769 u8 compltonack; /* DWORD 4 */
770 u8 stat_sn[32]; /* DWORD 5 */
771 u8 pad_buffer_addr_hi[32]; /* DWORD 6 */
772 u8 pad_buffer_addr_lo[32]; /* DWORD 7 */
773 u8 pad_addr_hi[32]; /* DWORD 8 */
774 u8 pad_addr_lo[32]; /* DWORD 9 */
775 u8 rsvd5[32]; /* DWORD 10 */
776 u8 rsvd6[32]; /* DWORD 11 */
777 u8 rsvd7[32]; /* DWORD 12 */
778 u8 rsvd8[32]; /* DWORD 13 */
779 u8 rsvd9[32]; /* DWORD 14 */
780 u8 rsvd10[32]; /* DWORD 15 */
781
782 } __packed;
783
784 struct be_ring {
785 u32 pages; /* queue size in pages */
786 u32 id; /* queue id assigned by beklib */
787 u32 num; /* number of elements in queue */
788 u32 cidx; /* consumer index */
789 u32 pidx; /* producer index -- not used by most rings */
790 u32 item_size; /* size in bytes of one object */
791
792 void *va; /* The virtual address of the ring. This
793 * should be last to allow 32 & 64 bit debugger
794 * extensions to work.
795 */
796 };
797
798 struct hwi_wrb_context {
799 struct list_head wrb_handle_list;
800 struct list_head wrb_handle_drvr_list;
801 struct wrb_handle **pwrb_handle_base;
802 struct wrb_handle **pwrb_handle_basestd;
803 struct iscsi_wrb *plast_wrb;
804 unsigned short alloc_index;
805 unsigned short free_index;
806 unsigned short wrb_handles_available;
807 unsigned short cid;
808 };
809
810 struct hwi_controller {
811 struct list_head io_sgl_list;
812 struct list_head eh_sgl_list;
813 struct sgl_handle *psgl_handle_base;
814 unsigned int wrb_mem_index;
815
816 struct hwi_wrb_context wrb_context[BE2_MAX_SESSIONS * 2];
817 struct mcc_wrb *pmcc_wrb_base;
818 struct be_ring default_pdu_hdr;
819 struct be_ring default_pdu_data;
820 struct hwi_context_memory *phwi_ctxt;
821 };
822
823 enum hwh_type_enum {
824 HWH_TYPE_IO = 1,
825 HWH_TYPE_LOGOUT = 2,
826 HWH_TYPE_TMF = 3,
827 HWH_TYPE_NOP = 4,
828 HWH_TYPE_IO_RD = 5,
829 HWH_TYPE_LOGIN = 11,
830 HWH_TYPE_INVALID = 0xFFFFFFFF
831 };
832
833 struct wrb_handle {
834 enum hwh_type_enum type;
835 unsigned short wrb_index;
836 unsigned short nxt_wrb_index;
837
838 struct iscsi_task *pio_handle;
839 struct iscsi_wrb *pwrb;
840 };
841
842 struct hwi_context_memory {
843 /* Adaptive interrupt coalescing (AIC) info */
844 u16 min_eqd; /* in usecs */
845 u16 max_eqd; /* in usecs */
846 u16 cur_eqd; /* in usecs */
847 struct be_eq_obj be_eq[MAX_CPUS];
848 struct be_queue_info be_cq[MAX_CPUS];
849
850 struct be_queue_info be_def_hdrq;
851 struct be_queue_info be_def_dataq;
852
853 struct be_queue_info be_wrbq[BE2_MAX_SESSIONS];
854 struct be_mcc_wrb_context *pbe_mcc_context;
855
856 struct hwi_async_pdu_context *pasync_ctx;
857 };
858
859 #endif