serial: Add driver for the Altera JTAG UART
[zen-stable.git] / include / linux / serial_core.h
blobade1536e1a483c53d1a65e0d7e2594cbab06624f
1 /*
2 * linux/drivers/char/serial_core.h
4 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #ifndef LINUX_SERIAL_CORE_H
21 #define LINUX_SERIAL_CORE_H
23 #include <linux/serial.h>
26 * The type definitions. These are from Ted Ts'o's serial.h
28 #define PORT_UNKNOWN 0
29 #define PORT_8250 1
30 #define PORT_16450 2
31 #define PORT_16550 3
32 #define PORT_16550A 4
33 #define PORT_CIRRUS 5
34 #define PORT_16650 6
35 #define PORT_16650V2 7
36 #define PORT_16750 8
37 #define PORT_STARTECH 9
38 #define PORT_16C950 10
39 #define PORT_16654 11
40 #define PORT_16850 12
41 #define PORT_RSA 13
42 #define PORT_NS16550A 14
43 #define PORT_XSCALE 15
44 #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
45 #define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
46 #define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
47 #define PORT_MAX_8250 18 /* max port ID */
50 * ARM specific type numbers. These are not currently guaranteed
51 * to be implemented, and will change in the future. These are
52 * separate so any additions to the old serial.c that occur before
53 * we are merged can be easily merged here.
55 #define PORT_PXA 31
56 #define PORT_AMBA 32
57 #define PORT_CLPS711X 33
58 #define PORT_SA1100 34
59 #define PORT_UART00 35
60 #define PORT_21285 37
62 /* Sparc type numbers. */
63 #define PORT_SUNZILOG 38
64 #define PORT_SUNSAB 39
66 /* DEC */
67 #define PORT_DZ 46
68 #define PORT_ZS 47
70 /* Parisc type numbers. */
71 #define PORT_MUX 48
73 /* Atmel AT91 / AT32 SoC */
74 #define PORT_ATMEL 49
76 /* Macintosh Zilog type numbers */
77 #define PORT_MAC_ZILOG 50 /* m68k : not yet implemented */
78 #define PORT_PMAC_ZILOG 51
80 /* SH-SCI */
81 #define PORT_SCI 52
82 #define PORT_SCIF 53
83 #define PORT_IRDA 54
85 /* Samsung S3C2410 SoC and derivatives thereof */
86 #define PORT_S3C2410 55
88 /* SGI IP22 aka Indy / Challenge S / Indigo 2 */
89 #define PORT_IP22ZILOG 56
91 /* Sharp LH7a40x -- an ARM9 SoC series */
92 #define PORT_LH7A40X 57
94 /* PPC CPM type number */
95 #define PORT_CPM 58
97 /* MPC52xx type numbers */
98 #define PORT_MPC52xx 59
100 /* IBM icom */
101 #define PORT_ICOM 60
103 /* Samsung S3C2440 SoC */
104 #define PORT_S3C2440 61
106 /* Motorola i.MX SoC */
107 #define PORT_IMX 62
109 /* Marvell MPSC */
110 #define PORT_MPSC 63
112 /* TXX9 type number */
113 #define PORT_TXX9 64
115 /* NEC VR4100 series SIU/DSIU */
116 #define PORT_VR41XX_SIU 65
117 #define PORT_VR41XX_DSIU 66
119 /* Samsung S3C2400 SoC */
120 #define PORT_S3C2400 67
122 /* M32R SIO */
123 #define PORT_M32R_SIO 68
125 /*Digi jsm */
126 #define PORT_JSM 69
128 #define PORT_PNX8XXX 70
130 /* Hilscher netx */
131 #define PORT_NETX 71
133 /* SUN4V Hypervisor Console */
134 #define PORT_SUNHV 72
136 #define PORT_S3C2412 73
138 /* Xilinx uartlite */
139 #define PORT_UARTLITE 74
141 /* Blackfin bf5xx */
142 #define PORT_BFIN 75
144 /* Micrel KS8695 */
145 #define PORT_KS8695 76
147 /* Broadcom SB1250, etc. SOC */
148 #define PORT_SB1250_DUART 77
150 /* Freescale ColdFire */
151 #define PORT_MCF 78
153 /* Blackfin SPORT */
154 #define PORT_BFIN_SPORT 79
156 /* MN10300 on-chip UART numbers */
157 #define PORT_MN10300 80
158 #define PORT_MN10300_CTS 81
160 #define PORT_SC26XX 82
162 /* SH-SCI */
163 #define PORT_SCIFA 83
165 #define PORT_S3C6400 84
167 /* NWPSERIAL */
168 #define PORT_NWPSERIAL 85
170 /* MAX3100 */
171 #define PORT_MAX3100 86
173 /* Timberdale UART */
174 #define PORT_TIMBUART 87
176 /* Qualcomm MSM SoCs */
177 #define PORT_MSM 88
179 /* BCM63xx family SoCs */
180 #define PORT_BCM63XX 89
182 /* Aeroflex Gaisler GRLIB APBUART */
183 #define PORT_APBUART 90
185 /* Altera UARTs */
186 #define PORT_ALTERA_JTAGUART 91
188 #ifdef __KERNEL__
190 #include <linux/compiler.h>
191 #include <linux/interrupt.h>
192 #include <linux/circ_buf.h>
193 #include <linux/spinlock.h>
194 #include <linux/sched.h>
195 #include <linux/tty.h>
196 #include <linux/mutex.h>
197 #include <linux/sysrq.h>
199 struct uart_port;
200 struct serial_struct;
201 struct device;
204 * This structure describes all the operations that can be
205 * done on the physical hardware.
207 struct uart_ops {
208 unsigned int (*tx_empty)(struct uart_port *);
209 void (*set_mctrl)(struct uart_port *, unsigned int mctrl);
210 unsigned int (*get_mctrl)(struct uart_port *);
211 void (*stop_tx)(struct uart_port *);
212 void (*start_tx)(struct uart_port *);
213 void (*send_xchar)(struct uart_port *, char ch);
214 void (*stop_rx)(struct uart_port *);
215 void (*enable_ms)(struct uart_port *);
216 void (*break_ctl)(struct uart_port *, int ctl);
217 int (*startup)(struct uart_port *);
218 void (*shutdown)(struct uart_port *);
219 void (*flush_buffer)(struct uart_port *);
220 void (*set_termios)(struct uart_port *, struct ktermios *new,
221 struct ktermios *old);
222 void (*set_ldisc)(struct uart_port *);
223 void (*pm)(struct uart_port *, unsigned int state,
224 unsigned int oldstate);
225 int (*set_wake)(struct uart_port *, unsigned int state);
228 * Return a string describing the type of the port
230 const char *(*type)(struct uart_port *);
233 * Release IO and memory resources used by the port.
234 * This includes iounmap if necessary.
236 void (*release_port)(struct uart_port *);
239 * Request IO and memory resources used by the port.
240 * This includes iomapping the port if necessary.
242 int (*request_port)(struct uart_port *);
243 void (*config_port)(struct uart_port *, int);
244 int (*verify_port)(struct uart_port *, struct serial_struct *);
245 int (*ioctl)(struct uart_port *, unsigned int, unsigned long);
246 #ifdef CONFIG_CONSOLE_POLL
247 void (*poll_put_char)(struct uart_port *, unsigned char);
248 int (*poll_get_char)(struct uart_port *);
249 #endif
252 #define UART_CONFIG_TYPE (1 << 0)
253 #define UART_CONFIG_IRQ (1 << 1)
255 struct uart_icount {
256 __u32 cts;
257 __u32 dsr;
258 __u32 rng;
259 __u32 dcd;
260 __u32 rx;
261 __u32 tx;
262 __u32 frame;
263 __u32 overrun;
264 __u32 parity;
265 __u32 brk;
266 __u32 buf_overrun;
269 typedef unsigned int __bitwise__ upf_t;
271 struct uart_port {
272 spinlock_t lock; /* port lock */
273 unsigned long iobase; /* in/out[bwl] */
274 unsigned char __iomem *membase; /* read/write[bwl] */
275 unsigned int (*serial_in)(struct uart_port *, int);
276 void (*serial_out)(struct uart_port *, int, int);
277 unsigned int irq; /* irq number */
278 unsigned long irqflags; /* irq flags */
279 unsigned int uartclk; /* base uart clock */
280 unsigned int fifosize; /* tx fifo size */
281 unsigned char x_char; /* xon/xoff char */
282 unsigned char regshift; /* reg offset shift */
283 unsigned char iotype; /* io access style */
284 unsigned char unused1;
286 #define UPIO_PORT (0)
287 #define UPIO_HUB6 (1)
288 #define UPIO_MEM (2)
289 #define UPIO_MEM32 (3)
290 #define UPIO_AU (4) /* Au1x00 type IO */
291 #define UPIO_TSI (5) /* Tsi108/109 type IO */
292 #define UPIO_DWAPB (6) /* DesignWare APB UART */
293 #define UPIO_RM9000 (7) /* RM9000 type IO */
295 unsigned int read_status_mask; /* driver specific */
296 unsigned int ignore_status_mask; /* driver specific */
297 struct uart_state *state; /* pointer to parent state */
298 struct uart_icount icount; /* statistics */
300 struct console *cons; /* struct console, if any */
301 #if defined(CONFIG_SERIAL_CORE_CONSOLE) || defined(SUPPORT_SYSRQ)
302 unsigned long sysrq; /* sysrq timeout */
303 #endif
305 upf_t flags;
307 #define UPF_FOURPORT ((__force upf_t) (1 << 1))
308 #define UPF_SAK ((__force upf_t) (1 << 2))
309 #define UPF_SPD_MASK ((__force upf_t) (0x1030))
310 #define UPF_SPD_HI ((__force upf_t) (0x0010))
311 #define UPF_SPD_VHI ((__force upf_t) (0x0020))
312 #define UPF_SPD_CUST ((__force upf_t) (0x0030))
313 #define UPF_SPD_SHI ((__force upf_t) (0x1000))
314 #define UPF_SPD_WARP ((__force upf_t) (0x1010))
315 #define UPF_SKIP_TEST ((__force upf_t) (1 << 6))
316 #define UPF_AUTO_IRQ ((__force upf_t) (1 << 7))
317 #define UPF_HARDPPS_CD ((__force upf_t) (1 << 11))
318 #define UPF_LOW_LATENCY ((__force upf_t) (1 << 13))
319 #define UPF_BUGGY_UART ((__force upf_t) (1 << 14))
320 #define UPF_NO_TXEN_TEST ((__force upf_t) (1 << 15))
321 #define UPF_MAGIC_MULTIPLIER ((__force upf_t) (1 << 16))
322 #define UPF_CONS_FLOW ((__force upf_t) (1 << 23))
323 #define UPF_SHARE_IRQ ((__force upf_t) (1 << 24))
324 /* The exact UART type is known and should not be probed. */
325 #define UPF_FIXED_TYPE ((__force upf_t) (1 << 27))
326 #define UPF_BOOT_AUTOCONF ((__force upf_t) (1 << 28))
327 #define UPF_FIXED_PORT ((__force upf_t) (1 << 29))
328 #define UPF_DEAD ((__force upf_t) (1 << 30))
329 #define UPF_IOREMAP ((__force upf_t) (1 << 31))
331 #define UPF_CHANGE_MASK ((__force upf_t) (0x17fff))
332 #define UPF_USR_MASK ((__force upf_t) (UPF_SPD_MASK|UPF_LOW_LATENCY))
334 unsigned int mctrl; /* current modem ctrl settings */
335 unsigned int timeout; /* character-based timeout */
336 unsigned int type; /* port type */
337 const struct uart_ops *ops;
338 unsigned int custom_divisor;
339 unsigned int line; /* port index */
340 resource_size_t mapbase; /* for ioremap */
341 struct device *dev; /* parent device */
342 unsigned char hub6; /* this should be in the 8250 driver */
343 unsigned char suspended;
344 unsigned char unused[2];
345 void *private_data; /* generic platform data pointer */
349 * This is the state information which is persistent across opens.
351 struct uart_state {
352 struct tty_port port;
354 int pm_state;
355 struct circ_buf xmit;
357 struct tasklet_struct tlet;
358 struct uart_port *uart_port;
361 #define UART_XMIT_SIZE PAGE_SIZE
364 /* number of characters left in xmit buffer before we ask for more */
365 #define WAKEUP_CHARS 256
367 struct module;
368 struct tty_driver;
370 struct uart_driver {
371 struct module *owner;
372 const char *driver_name;
373 const char *dev_name;
374 int major;
375 int minor;
376 int nr;
377 struct console *cons;
380 * these are private; the low level driver should not
381 * touch these; they should be initialised to NULL
383 struct uart_state *state;
384 struct tty_driver *tty_driver;
387 void uart_write_wakeup(struct uart_port *port);
390 * Baud rate helpers.
392 void uart_update_timeout(struct uart_port *port, unsigned int cflag,
393 unsigned int baud);
394 unsigned int uart_get_baud_rate(struct uart_port *port, struct ktermios *termios,
395 struct ktermios *old, unsigned int min,
396 unsigned int max);
397 unsigned int uart_get_divisor(struct uart_port *port, unsigned int baud);
400 * Console helpers.
402 struct uart_port *uart_get_console(struct uart_port *ports, int nr,
403 struct console *c);
404 void uart_parse_options(char *options, int *baud, int *parity, int *bits,
405 int *flow);
406 int uart_set_options(struct uart_port *port, struct console *co, int baud,
407 int parity, int bits, int flow);
408 struct tty_driver *uart_console_device(struct console *co, int *index);
409 void uart_console_write(struct uart_port *port, const char *s,
410 unsigned int count,
411 void (*putchar)(struct uart_port *, int));
414 * Port/driver registration/removal
416 int uart_register_driver(struct uart_driver *uart);
417 void uart_unregister_driver(struct uart_driver *uart);
418 int uart_add_one_port(struct uart_driver *reg, struct uart_port *port);
419 int uart_remove_one_port(struct uart_driver *reg, struct uart_port *port);
420 int uart_match_port(struct uart_port *port1, struct uart_port *port2);
423 * Power Management
425 int uart_suspend_port(struct uart_driver *reg, struct uart_port *port);
426 int uart_resume_port(struct uart_driver *reg, struct uart_port *port);
428 #define uart_circ_empty(circ) ((circ)->head == (circ)->tail)
429 #define uart_circ_clear(circ) ((circ)->head = (circ)->tail = 0)
431 #define uart_circ_chars_pending(circ) \
432 (CIRC_CNT((circ)->head, (circ)->tail, UART_XMIT_SIZE))
434 #define uart_circ_chars_free(circ) \
435 (CIRC_SPACE((circ)->head, (circ)->tail, UART_XMIT_SIZE))
437 static inline int uart_tx_stopped(struct uart_port *port)
439 struct tty_struct *tty = port->state->port.tty;
440 if(tty->stopped || tty->hw_stopped)
441 return 1;
442 return 0;
446 * The following are helper functions for the low level drivers.
448 static inline int
449 uart_handle_sysrq_char(struct uart_port *port, unsigned int ch)
451 #ifdef SUPPORT_SYSRQ
452 if (port->sysrq) {
453 if (ch && time_before(jiffies, port->sysrq)) {
454 handle_sysrq(ch, port->state->port.tty);
455 port->sysrq = 0;
456 return 1;
458 port->sysrq = 0;
460 #endif
461 return 0;
463 #ifndef SUPPORT_SYSRQ
464 #define uart_handle_sysrq_char(port,ch) uart_handle_sysrq_char(port, 0)
465 #endif
468 * We do the SysRQ and SAK checking like this...
470 static inline int uart_handle_break(struct uart_port *port)
472 struct uart_state *state = port->state;
473 #ifdef SUPPORT_SYSRQ
474 if (port->cons && port->cons->index == port->line) {
475 if (!port->sysrq) {
476 port->sysrq = jiffies + HZ*5;
477 return 1;
479 port->sysrq = 0;
481 #endif
482 if (port->flags & UPF_SAK)
483 do_SAK(state->port.tty);
484 return 0;
488 * uart_handle_dcd_change - handle a change of carrier detect state
489 * @uport: uart_port structure for the open port
490 * @status: new carrier detect status, nonzero if active
492 static inline void
493 uart_handle_dcd_change(struct uart_port *uport, unsigned int status)
495 struct uart_state *state = uport->state;
496 struct tty_port *port = &state->port;
497 struct tty_ldisc *ld = tty_ldisc_ref(port->tty);
498 struct timespec ts;
500 if (ld && ld->ops->dcd_change)
501 getnstimeofday(&ts);
503 uport->icount.dcd++;
504 #ifdef CONFIG_HARD_PPS
505 if ((uport->flags & UPF_HARDPPS_CD) && status)
506 hardpps();
507 #endif
509 if (port->flags & ASYNC_CHECK_CD) {
510 if (status)
511 wake_up_interruptible(&port->open_wait);
512 else if (port->tty)
513 tty_hangup(port->tty);
516 if (ld && ld->ops->dcd_change)
517 ld->ops->dcd_change(port->tty, status, &ts);
518 if (ld)
519 tty_ldisc_deref(ld);
523 * uart_handle_cts_change - handle a change of clear-to-send state
524 * @uport: uart_port structure for the open port
525 * @status: new clear to send status, nonzero if active
527 static inline void
528 uart_handle_cts_change(struct uart_port *uport, unsigned int status)
530 struct tty_port *port = &uport->state->port;
531 struct tty_struct *tty = port->tty;
533 uport->icount.cts++;
535 if (port->flags & ASYNC_CTS_FLOW) {
536 if (tty->hw_stopped) {
537 if (status) {
538 tty->hw_stopped = 0;
539 uport->ops->start_tx(uport);
540 uart_write_wakeup(uport);
542 } else {
543 if (!status) {
544 tty->hw_stopped = 1;
545 uport->ops->stop_tx(uport);
551 #include <linux/tty_flip.h>
553 static inline void
554 uart_insert_char(struct uart_port *port, unsigned int status,
555 unsigned int overrun, unsigned int ch, unsigned int flag)
557 struct tty_struct *tty = port->state->port.tty;
559 if ((status & port->ignore_status_mask & ~overrun) == 0)
560 tty_insert_flip_char(tty, ch, flag);
563 * Overrun is special. Since it's reported immediately,
564 * it doesn't affect the current character.
566 if (status & ~port->ignore_status_mask & overrun)
567 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
571 * UART_ENABLE_MS - determine if port should enable modem status irqs
573 #define UART_ENABLE_MS(port,cflag) ((port)->flags & UPF_HARDPPS_CD || \
574 (cflag) & CRTSCTS || \
575 !((cflag) & CLOCAL))
577 #endif
579 #endif /* LINUX_SERIAL_CORE_H */