arch/x86/include/asm/uv/uv_hub.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV architectural definitions
   7  *
   8  * Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved.
   9  */
  10
  11 #ifndef _ASM_X86_UV_UV_HUB_H
  12 #define _ASM_X86_UV_UV_HUB_H
  13
  14 #ifdef CONFIG_X86_64
  15 #include <linux/numa.h>
  16 #include <linux/percpu.h>
  17 #include <linux/timer.h>
  18 #include <linux/io.h>
  19 #include <asm/types.h>
  20 #include <asm/percpu.h>
  21 #include <asm/uv/uv_mmrs.h>
  22 #include <asm/irq_vectors.h>
  23 #include <asm/io_apic.h>
  24
  25
  26 /*
  27  * Addressing Terminology
  28  *
  29  *      M       - The low M bits of a physical address represent the offset
  30  *                into the blade local memory. RAM memory on a blade is physically
  31  *                contiguous (although various IO spaces may punch holes in
  32  *                it)..
  33  *
  34  *      N       - Number of bits in the node portion of a socket physical
  35  *                address.
  36  *
  37  *      NASID   - network ID of a router, Mbrick or Cbrick. Nasid values of
  38  *                routers always have low bit of 1, C/MBricks have low bit
  39  *                equal to 0. Most addressing macros that target UV hub chips
  40  *                right shift the NASID by 1 to exclude the always-zero bit.
  41  *                NASIDs contain up to 15 bits.
  42  *
  43  *      GNODE   - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
  44  *                of nasids.
  45  *
  46  *      PNODE   - the low N bits of the GNODE. The PNODE is the most useful variant
  47  *                of the nasid for socket usage.
  48  *
  49  *      GPA     - (global physical address) a socket physical address converted
  50  *                so that it can be used by the GRU as a global address. Socket
  51  *                physical addresses 1) need additional NASID (node) bits added
  52  *                to the high end of the address, and 2) unaliased if the
  53  *                partition does not have a physical address 0. In addition, on
  54  *                UV2 rev 1, GPAs need the gnode left shifted to bits 39 or 40.
  55  *
  56  *
  57  *  NumaLink Global Physical Address Format:
  58  *  +--------------------------------+---------------------+
  59  *  |00..000|      GNODE             |      NodeOffset     |
  60  *  +--------------------------------+---------------------+
  61  *          |<-------53 - M bits --->|<--------M bits ----->
  62  *
  63  *      M - number of node offset bits (35 .. 40)
  64  *
  65  *
  66  *  Memory/UV-HUB Processor Socket Address Format:
  67  *  +----------------+---------------+---------------------+
  68  *  |00..000000000000|   PNODE       |      NodeOffset     |
  69  *  +----------------+---------------+---------------------+
  70  *                   <--- N bits --->|<--------M bits ----->
  71  *
  72  *      M - number of node offset bits (35 .. 40)
  73  *      N - number of PNODE bits (0 .. 10)
  74  *
  75  *              Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
  76  *              The actual values are configuration dependent and are set at
  77  *              boot time. M & N values are set by the hardware/BIOS at boot.
  78  *
  79  *
  80  * APICID format
  81  *      NOTE!!!!!! This is the current format of the APICID. However, code
  82  *      should assume that this will change in the future. Use functions
  83  *      in this file for all APICID bit manipulations and conversion.
  84  *
  85  *              1111110000000000
  86  *              5432109876543210
  87  *              pppppppppplc0cch        Nehalem-EX (12 bits in hdw reg)
  88  *              ppppppppplcc0cch        Westmere-EX (12 bits in hdw reg)
  89  *              pppppppppppcccch        SandyBridge (15 bits in hdw reg)
  90  *              sssssssssss
  91  *
  92  *                      p  = pnode bits
  93  *                      l =  socket number on board
  94  *                      c  = core
  95  *                      h  = hyperthread
  96  *                      s  = bits that are in the SOCKET_ID CSR
  97  *
  98  *      Note: Processor may support fewer bits in the APICID register. The ACPI
  99  *            tables hold all 16 bits. Software needs to be aware of this.
 100  *
 101  *            Unless otherwise specified, all references to APICID refer to
 102  *            the FULL value contained in ACPI tables, not the subset in the
 103  *            processor APICID register.
 104  */
 105
 106
 107 /*
 108  * Maximum number of bricks in all partitions and in all coherency domains.
 109  * This is the total number of bricks accessible in the numalink fabric. It
 110  * includes all C & M bricks. Routers are NOT included.
 111  *
 112  * This value is also the value of the maximum number of non-router NASIDs
 113  * in the numalink fabric.
 114  *
 115  * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
 116  */
 117 #define UV_MAX_NUMALINK_BLADES  16384
 118
 119 /*
 120  * Maximum number of C/Mbricks within a software SSI (hardware may support
 121  * more).
 122  */
 123 #define UV_MAX_SSI_BLADES       256
 124
 125 /*
 126  * The largest possible NASID of a C or M brick (+ 2)
 127  */
 128 #define UV_MAX_NASID_VALUE      (UV_MAX_NUMALINK_BLADES * 2)
 129
 130 struct uv_scir_s {
 131         struct timer_list timer;
 132         unsigned long   offset;
 133         unsigned long   last;
 134         unsigned long   idle_on;
 135         unsigned long   idle_off;
 136         unsigned char   state;
 137         unsigned char   enabled;
 138 };
 139
 140 /*
 141  * The following defines attributes of the HUB chip. These attributes are
 142  * frequently referenced and are kept in the per-cpu data areas of each cpu.
 143  * They are kept together in a struct to minimize cache misses.
 144  */
 145 struct uv_hub_info_s {
 146         unsigned long           global_mmr_base;
 147         unsigned long           gpa_mask;
 148         unsigned int            gnode_extra;
 149         unsigned char           hub_revision;
 150         unsigned char           apic_pnode_shift;
 151         unsigned char           m_shift;
 152         unsigned char           n_lshift;
 153         unsigned long           gnode_upper;
 154         unsigned long           lowmem_remap_top;
 155         unsigned long           lowmem_remap_base;
 156         unsigned short          pnode;
 157         unsigned short          pnode_mask;
 158         unsigned short          coherency_domain_number;
 159         unsigned short          numa_blade_id;
 160         unsigned char           blade_processor_id;
 161         unsigned char           m_val;
 162         unsigned char           n_val;
 163         struct uv_scir_s        scir;
 164 };
 165
 166 DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
 167 #define uv_hub_info             (&__get_cpu_var(__uv_hub_info))
 168 #define uv_cpu_hub_info(cpu)    (&per_cpu(__uv_hub_info, cpu))
 169
 170 /*
 171  * Hub revisions less than UV2_HUB_REVISION_BASE are UV1 hubs. All UV2
 172  * hubs have revision numbers greater than or equal to UV2_HUB_REVISION_BASE.
 173  * This is a software convention - NOT the hardware revision numbers in
 174  * the hub chip.
 175  */
 176 #define UV1_HUB_REVISION_BASE           1
 177 #define UV2_HUB_REVISION_BASE           3
 178
 179 static inline int is_uv1_hub(void)
 180 {
 181         return uv_hub_info->hub_revision < UV2_HUB_REVISION_BASE;
 182 }
 183
 184 static inline int is_uv2_hub(void)
 185 {
 186         return uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE;
 187 }
 188
 189 static inline int is_uv2_1_hub(void)
 190 {
 191         return uv_hub_info->hub_revision == UV2_HUB_REVISION_BASE;
 192 }
 193
 194 static inline int is_uv2_2_hub(void)
 195 {
 196         return uv_hub_info->hub_revision == UV2_HUB_REVISION_BASE + 1;
 197 }
 198
 199 union uvh_apicid {
 200     unsigned long       v;
 201     struct uvh_apicid_s {
 202         unsigned long   local_apic_mask  : 24;
 203         unsigned long   local_apic_shift :  5;
 204         unsigned long   unused1          :  3;
 205         unsigned long   pnode_mask       : 24;
 206         unsigned long   pnode_shift      :  5;
 207         unsigned long   unused2          :  3;
 208     } s;
 209 };
 210
 211 /*
 212  * Local & Global MMR space macros.
 213  *      Note: macros are intended to be used ONLY by inline functions
 214  *      in this file - not by other kernel code.
 215  *              n -  NASID (full 15-bit global nasid)
 216  *              g -  GNODE (full 15-bit global nasid, right shifted 1)
 217  *              p -  PNODE (local part of nsids, right shifted 1)
 218  */
 219 #define UV_NASID_TO_PNODE(n)            (((n) >> 1) & uv_hub_info->pnode_mask)
 220 #define UV_PNODE_TO_GNODE(p)            ((p) |uv_hub_info->gnode_extra)
 221 #define UV_PNODE_TO_NASID(p)            (UV_PNODE_TO_GNODE(p) << 1)
 222
 223 #define UV1_LOCAL_MMR_BASE              0xf4000000UL
 224 #define UV1_GLOBAL_MMR32_BASE           0xf8000000UL
 225 #define UV1_LOCAL_MMR_SIZE              (64UL * 1024 * 1024)
 226 #define UV1_GLOBAL_MMR32_SIZE           (64UL * 1024 * 1024)
 227
 228 #define UV2_LOCAL_MMR_BASE              0xfa000000UL
 229 #define UV2_GLOBAL_MMR32_BASE           0xfc000000UL
 230 #define UV2_LOCAL_MMR_SIZE              (32UL * 1024 * 1024)
 231 #define UV2_GLOBAL_MMR32_SIZE           (32UL * 1024 * 1024)
 232
 233 #define UV_LOCAL_MMR_BASE               (is_uv1_hub() ? UV1_LOCAL_MMR_BASE     \
 234                                                 : UV2_LOCAL_MMR_BASE)
 235 #define UV_GLOBAL_MMR32_BASE            (is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE  \
 236                                                 : UV2_GLOBAL_MMR32_BASE)
 237 #define UV_LOCAL_MMR_SIZE               (is_uv1_hub() ? UV1_LOCAL_MMR_SIZE :   \
 238                                                 UV2_LOCAL_MMR_SIZE)
 239 #define UV_GLOBAL_MMR32_SIZE            (is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE :\
 240                                                 UV2_GLOBAL_MMR32_SIZE)
 241 #define UV_GLOBAL_MMR64_BASE            (uv_hub_info->global_mmr_base)
 242
 243 #define UV_GLOBAL_GRU_MMR_BASE          0x4000000
 244
 245 #define UV_GLOBAL_MMR32_PNODE_SHIFT     15
 246 #define UV_GLOBAL_MMR64_PNODE_SHIFT     26
 247
 248 #define UV_GLOBAL_MMR32_PNODE_BITS(p)   ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
 249
 250 #define UV_GLOBAL_MMR64_PNODE_BITS(p)                                   \
 251         (((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT)
 252
 253 #define UVH_APICID              0x002D0E00L
 254 #define UV_APIC_PNODE_SHIFT     6
 255
 256 #define UV_APICID_HIBIT_MASK    0xffff0000
 257
 258 /* Local Bus from cpu's perspective */
 259 #define LOCAL_BUS_BASE          0x1c00000
 260 #define LOCAL_BUS_SIZE          (4 * 1024 * 1024)
 261
 262 /*
 263  * System Controller Interface Reg
 264  *
 265  * Note there are NO leds on a UV system.  This register is only
 266  * used by the system controller to monitor system-wide operation.
 267  * There are 64 regs per node.  With Nahelem cpus (2 cores per node,
 268  * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on
 269  * a node.
 270  *
 271  * The window is located at top of ACPI MMR space
 272  */
 273 #define SCIR_WINDOW_COUNT       64
 274 #define SCIR_LOCAL_MMR_BASE     (LOCAL_BUS_BASE + \
 275                                  LOCAL_BUS_SIZE - \
 276                                  SCIR_WINDOW_COUNT)
 277
 278 #define SCIR_CPU_HEARTBEAT      0x01    /* timer interrupt */
 279 #define SCIR_CPU_ACTIVITY       0x02    /* not idle */
 280 #define SCIR_CPU_HB_INTERVAL    (HZ)    /* once per second */
 281
 282 /* Loop through all installed blades */
 283 #define for_each_possible_blade(bid)            \
 284         for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++)
 285
 286 /*
 287  * Macros for converting between kernel virtual addresses, socket local physical
 288  * addresses, and UV global physical addresses.
 289  *      Note: use the standard __pa() & __va() macros for converting
 290  *            between socket virtual and socket physical addresses.
 291  */
 292
 293 /* socket phys RAM --> UV global physical address */
 294 static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
 295 {
 296         if (paddr < uv_hub_info->lowmem_remap_top)
 297                 paddr |= uv_hub_info->lowmem_remap_base;
 298         paddr |= uv_hub_info->gnode_upper;
 299         paddr = ((paddr << uv_hub_info->m_shift) >> uv_hub_info->m_shift) |
 300                 ((paddr >> uv_hub_info->m_val) << uv_hub_info->n_lshift);
 301         return paddr;
 302 }
 303
 304
 305 /* socket virtual --> UV global physical address */
 306 static inline unsigned long uv_gpa(void *v)
 307 {
 308         return uv_soc_phys_ram_to_gpa(__pa(v));
 309 }
 310
 311 /* Top two bits indicate the requested address is in MMR space.  */
 312 static inline int
 313 uv_gpa_in_mmr_space(unsigned long gpa)
 314 {
 315         return (gpa >> 62) == 0x3UL;
 316 }
 317
 318 /* UV global physical address --> socket phys RAM */
 319 static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa)
 320 {
 321         unsigned long paddr;
 322         unsigned long remap_base = uv_hub_info->lowmem_remap_base;
 323         unsigned long remap_top =  uv_hub_info->lowmem_remap_top;
 324
 325         gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) |
 326                 ((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val);
 327         paddr = gpa & uv_hub_info->gpa_mask;
 328         if (paddr >= remap_base && paddr < remap_base + remap_top)
 329                 paddr -= remap_base;
 330         return paddr;
 331 }
 332
 333
 334 /* gpa -> pnode */
 335 static inline unsigned long uv_gpa_to_gnode(unsigned long gpa)
 336 {
 337         return gpa >> uv_hub_info->n_lshift;
 338 }
 339
 340 /* gpa -> pnode */
 341 static inline int uv_gpa_to_pnode(unsigned long gpa)
 342 {
 343         unsigned long n_mask = (1UL << uv_hub_info->n_val) - 1;
 344
 345         return uv_gpa_to_gnode(gpa) & n_mask;
 346 }
 347
 348 /* gpa -> node offset*/
 349 static inline unsigned long uv_gpa_to_offset(unsigned long gpa)
 350 {
 351         return (gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift;
 352 }
 353
 354 /* pnode, offset --> socket virtual */
 355 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
 356 {
 357         return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
 358 }
 359
 360
 361 /*
 362  * Extract a PNODE from an APICID (full apicid, not processor subset)
 363  */
 364 static inline int uv_apicid_to_pnode(int apicid)
 365 {
 366         return (apicid >> uv_hub_info->apic_pnode_shift);
 367 }
 368
 369 /*
 370  * Convert an apicid to the socket number on the blade
 371  */
 372 static inline int uv_apicid_to_socket(int apicid)
 373 {
 374         if (is_uv1_hub())
 375                 return (apicid >> (uv_hub_info->apic_pnode_shift - 1)) & 1;
 376         else
 377                 return 0;
 378 }
 379
 380 /*
 381  * Access global MMRs using the low memory MMR32 space. This region supports
 382  * faster MMR access but not all MMRs are accessible in this space.
 383  */
 384 static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset)
 385 {
 386         return __va(UV_GLOBAL_MMR32_BASE |
 387                        UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
 388 }
 389
 390 static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val)
 391 {
 392         writeq(val, uv_global_mmr32_address(pnode, offset));
 393 }
 394
 395 static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset)
 396 {
 397         return readq(uv_global_mmr32_address(pnode, offset));
 398 }
 399
 400 /*
 401  * Access Global MMR space using the MMR space located at the top of physical
 402  * memory.
 403  */
 404 static inline volatile void __iomem *uv_global_mmr64_address(int pnode, unsigned long offset)
 405 {
 406         return __va(UV_GLOBAL_MMR64_BASE |
 407                     UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
 408 }
 409
 410 static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val)
 411 {
 412         writeq(val, uv_global_mmr64_address(pnode, offset));
 413 }
 414
 415 static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset)
 416 {
 417         return readq(uv_global_mmr64_address(pnode, offset));
 418 }
 419
 420 /*
 421  * Global MMR space addresses when referenced by the GRU. (GRU does
 422  * NOT use socket addressing).
 423  */
 424 static inline unsigned long uv_global_gru_mmr_address(int pnode, unsigned long offset)
 425 {
 426         return UV_GLOBAL_GRU_MMR_BASE | offset |
 427                 ((unsigned long)pnode << uv_hub_info->m_val);
 428 }
 429
 430 static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val)
 431 {
 432         writeb(val, uv_global_mmr64_address(pnode, offset));
 433 }
 434
 435 static inline unsigned char uv_read_global_mmr8(int pnode, unsigned long offset)
 436 {
 437         return readb(uv_global_mmr64_address(pnode, offset));
 438 }
 439
 440 /*
 441  * Access hub local MMRs. Faster than using global space but only local MMRs
 442  * are accessible.
 443  */
 444 static inline unsigned long *uv_local_mmr_address(unsigned long offset)
 445 {
 446         return __va(UV_LOCAL_MMR_BASE | offset);
 447 }
 448
 449 static inline unsigned long uv_read_local_mmr(unsigned long offset)
 450 {
 451         return readq(uv_local_mmr_address(offset));
 452 }
 453
 454 static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
 455 {
 456         writeq(val, uv_local_mmr_address(offset));
 457 }
 458
 459 static inline unsigned char uv_read_local_mmr8(unsigned long offset)
 460 {
 461         return readb(uv_local_mmr_address(offset));
 462 }
 463
 464 static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val)
 465 {
 466         writeb(val, uv_local_mmr_address(offset));
 467 }
 468
 469 /*
 470  * Structures and definitions for converting between cpu, node, pnode, and blade
 471  * numbers.
 472  */
 473 struct uv_blade_info {
 474         unsigned short  nr_possible_cpus;
 475         unsigned short  nr_online_cpus;
 476         unsigned short  pnode;
 477         short           memory_nid;
 478         spinlock_t      nmi_lock;
 479         unsigned long   nmi_count;
 480 };
 481 extern struct uv_blade_info *uv_blade_info;
 482 extern short *uv_node_to_blade;
 483 extern short *uv_cpu_to_blade;
 484 extern short uv_possible_blades;
 485
 486 /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
 487 static inline int uv_blade_processor_id(void)
 488 {
 489         return uv_hub_info->blade_processor_id;
 490 }
 491
 492 /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
 493 static inline int uv_numa_blade_id(void)
 494 {
 495         return uv_hub_info->numa_blade_id;
 496 }
 497
 498 /* Convert a cpu number to the the UV blade number */
 499 static inline int uv_cpu_to_blade_id(int cpu)
 500 {
 501         return uv_cpu_to_blade[cpu];
 502 }
 503
 504 /* Convert linux node number to the UV blade number */
 505 static inline int uv_node_to_blade_id(int nid)
 506 {
 507         return uv_node_to_blade[nid];
 508 }
 509
 510 /* Convert a blade id to the PNODE of the blade */
 511 static inline int uv_blade_to_pnode(int bid)
 512 {
 513         return uv_blade_info[bid].pnode;
 514 }
 515
 516 /* Nid of memory node on blade. -1 if no blade-local memory */
 517 static inline int uv_blade_to_memory_nid(int bid)
 518 {
 519         return uv_blade_info[bid].memory_nid;
 520 }
 521
 522 /* Determine the number of possible cpus on a blade */
 523 static inline int uv_blade_nr_possible_cpus(int bid)
 524 {
 525         return uv_blade_info[bid].nr_possible_cpus;
 526 }
 527
 528 /* Determine the number of online cpus on a blade */
 529 static inline int uv_blade_nr_online_cpus(int bid)
 530 {
 531         return uv_blade_info[bid].nr_online_cpus;
 532 }
 533
 534 /* Convert a cpu id to the PNODE of the blade containing the cpu */
 535 static inline int uv_cpu_to_pnode(int cpu)
 536 {
 537         return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode;
 538 }
 539
 540 /* Convert a linux node number to the PNODE of the blade */
 541 static inline int uv_node_to_pnode(int nid)
 542 {
 543         return uv_blade_info[uv_node_to_blade_id(nid)].pnode;
 544 }
 545
 546 /* Maximum possible number of blades */
 547 static inline int uv_num_possible_blades(void)
 548 {
 549         return uv_possible_blades;
 550 }
 551
 552 /* Update SCIR state */
 553 static inline void uv_set_scir_bits(unsigned char value)
 554 {
 555         if (uv_hub_info->scir.state != value) {
 556                 uv_hub_info->scir.state = value;
 557                 uv_write_local_mmr8(uv_hub_info->scir.offset, value);
 558         }
 559 }
 560
 561 static inline unsigned long uv_scir_offset(int apicid)
 562 {
 563         return SCIR_LOCAL_MMR_BASE | (apicid & 0x3f);
 564 }
 565
 566 static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value)
 567 {
 568         if (uv_cpu_hub_info(cpu)->scir.state != value) {
 569                 uv_write_global_mmr8(uv_cpu_to_pnode(cpu),
 570                                 uv_cpu_hub_info(cpu)->scir.offset, value);
 571                 uv_cpu_hub_info(cpu)->scir.state = value;
 572         }
 573 }
 574
 575 extern unsigned int uv_apicid_hibits;
 576 static unsigned long uv_hub_ipi_value(int apicid, int vector, int mode)
 577 {
 578         apicid |= uv_apicid_hibits;
 579         return (1UL << UVH_IPI_INT_SEND_SHFT) |
 580                         ((apicid) << UVH_IPI_INT_APIC_ID_SHFT) |
 581                         (mode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |
 582                         (vector << UVH_IPI_INT_VECTOR_SHFT);
 583 }
 584
 585 static inline void uv_hub_send_ipi(int pnode, int apicid, int vector)
 586 {
 587         unsigned long val;
 588         unsigned long dmode = dest_Fixed;
 589
 590         if (vector == NMI_VECTOR)
 591                 dmode = dest_NMI;
 592
 593         val = uv_hub_ipi_value(apicid, vector, dmode);
 594         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 595 }
 596
 597 /*
 598  * Get the minimum revision number of the hub chips within the partition.
 599  *     1 - UV1 rev 1.0 initial silicon
 600  *     2 - UV1 rev 2.0 production silicon
 601  *     3 - UV2 rev 1.0 initial silicon
 602  */
 603 static inline int uv_get_min_hub_revision_id(void)
 604 {
 605         return uv_hub_info->hub_revision;
 606 }
 607
 608 #endif /* CONFIG_X86_64 */
 609 #endif /* _ASM_X86_UV_UV_HUB_H */