1 * Freescale Serial RapidIO (SRIO) Controller
8 Definition: Must include "fsl,srio" for IP blocks with IP Block
9 Revision Register (SRIO IPBRR1) Major ID equal to 0x01c0.
11 Optionally, a compatiable string of "fsl,srio-vX.Y" where X is Major
12 version in IP Block Revision Register and Y is Minor version. If this
13 compatiable is provided it should be ordered before "fsl,srio".
17 Value type: <prop-encoded-array>
18 Definition: A standard property. Specifies the physical address and
19 length of the SRIO configuration registers. The size should
24 Value type: <prop_encoded-array>
25 Definition: Specifies the interrupts generated by this device. The
26 value of the interrupts property consists of one interrupt
27 specifier. The format of the specifier is defined by the
28 binding document describing the node's interrupt parent.
30 A single IRQ that handles error conditions is specified by this
31 property. (Typically shared with port-write).
33 - fsl,srio-rmu-handle:
34 Usage: required if rmu node is defined
36 Definition: A single <phandle> value that points to the RMU.
37 (See srio-rmu.txt for more details on RMU node binding)
39 Port Child Nodes: There should a port child node for each port that exists in
40 the controller. The ports are numbered starting at one (1) and should have
41 the following properties:
46 Definition: A standard property. Matches the port id.
49 Usage: required if local access windows preset
50 Value type: <prop-encoded-array>
51 Definition: A standard property. Utilized to describe the memory mapped
52 IO space utilized by the controller. This corresponds to the
53 setting of the local access windows that are targeted to this
57 Usage: optional-but-recommended (for devices with PAMU)
58 Value type: <prop-encoded-array>
59 Definition: The logical I/O device number for the PAMU (IOMMU) to be
60 correctly configured for SRIO accesses. The property should
61 not exist on devices that do not support PAMU.
63 For HW (ie, the P4080) that only supports a LIODN for both
64 memory and maintenance transactions then a single LIODN is
65 represented in the property for both transactions.
67 For HW (ie, the P304x/P5020, etc) that supports an LIODN for
68 memory transactions and a unique LIODN for maintenance
69 transactions then a pair of LIODNs are represented in the
70 property. Within the pair, the first element represents the
71 LIODN associated with memory transactions and the second element
72 represents the LIODN associated with maintenance transactions
75 Note: All other standard properties (see ePAPR) are allowed but are optional.
79 rapidio: rapidio@ffe0c0000 {
82 reg = <0xf 0xfe0c0000 0 0x11000>;
83 compatible = "fsl,srio";
84 interrupts = <16 2 1 11>; /* err_irq */
85 fsl,srio-rmu-handle = <&rmu>;
93 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
101 ranges = <0 0 0xc 0x30000000 0 0x10000000>;