spi-topcliff-pch: add recovery processing in case wait-event timeout
[zen-stable.git] / arch / arm / mach-clps711x / include / mach / entry-macro.S
blob90fa2f70489f07d846d77bae32226b4c79bcefbe
1 /*
2  * arch/arm/mach-clps711x/include/mach/entry-macro.S
3  *
4  * Low-level IRQ helper macros for CLPS711X-based platforms
5  *
6  * This file is licensed under  the terms of the GNU General Public
7  * License version 2. This program is licensed "as is" without any
8  * warranty of any kind, whether express or implied.
9  */
10 #include <mach/hardware.h>
11 #include <asm/hardware/clps7111.h>
13                 .macro  disable_fiq
14                 .endm
16                 .macro  get_irqnr_preamble, base, tmp
17                 .endm
19                 .macro  arch_ret_to_user, tmp1, tmp2
20                 .endm
22 #if (INTSR2 - INTSR1) != (INTMR2 - INTMR1)
23 #error INTSR stride != INTMR stride
24 #endif
26                 .macro  get_irqnr_and_base, irqnr, stat, base, mask
27                 mov     \base, #CLPS7111_BASE
28                 ldr     \stat, [\base, #INTSR1]
29                 ldr     \mask, [\base, #INTMR1]
30                 mov     \irqnr, #4
31                 mov     \mask, \mask, lsl #16
32                 and     \stat, \stat, \mask, lsr #16
33                 movs    \stat, \stat, lsr #4
34                 bne     1001f
36                 add     \base, \base, #INTSR2 - INTSR1
37                 ldr     \stat, [\base, #INTSR1]
38                 ldr     \mask, [\base, #INTMR1]
39                 mov     \irqnr, #16
40                 mov     \mask, \mask, lsl #16
41                 and     \stat, \stat, \mask, lsr #16
43 1001:           tst     \stat, #255
44                 addeq   \irqnr, \irqnr, #8
45                 moveq   \stat, \stat, lsr #8
46                 tst     \stat, #15
47                 addeq   \irqnr, \irqnr, #4
48                 moveq   \stat, \stat, lsr #4
49                 tst     \stat, #3
50                 addeq   \irqnr, \irqnr, #2
51                 moveq   \stat, \stat, lsr #2
52                 tst     \stat, #1
53                 addeq   \irqnr, \irqnr, #1
54                 moveq   \stat, \stat, lsr #1
55                 tst     \stat, #1                       @ bit 0 should be set
56                 .endm