arch/arm/mach-mmp/time.c

   1 /*
   2  * linux/arch/arm/mach-mmp/time.c
   3  *
   4  *   Support for clocksource and clockevents
   5  *
   6  * Copyright (C) 2008 Marvell International Ltd.
   7  * All rights reserved.
   8  *
   9  *   2008-04-11: Jason Chagas <Jason.chagas@marvell.com>
  10  *   2008-10-08: Bin Yang <bin.yang@marvell.com>
  11  *
  12  * The timers module actually includes three timers, each timer with up to
  13  * three match comparators. Timer #0 is used here in free-running mode as
  14  * the clock source, and match comparator #1 used as clock event device.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/init.h>
  22 #include <linux/kernel.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/clockchips.h>
  25
  26 #include <linux/io.h>
  27 #include <linux/irq.h>
  28
  29 #include <asm/sched_clock.h>
  30 #include <mach/addr-map.h>
  31 #include <mach/regs-timers.h>
  32 #include <mach/regs-apbc.h>
  33 #include <mach/irqs.h>
  34 #include <mach/cputype.h>
  35 #include <asm/mach/time.h>
  36
  37 #include "clock.h"
  38
  39 #define TIMERS_VIRT_BASE        TIMERS1_VIRT_BASE
  40
  41 #define MAX_DELTA               (0xfffffffe)
  42 #define MIN_DELTA               (16)
  43
  44 /*
  45  * FIXME: the timer needs some delay to stablize the counter capture
  46  */
  47 static inline uint32_t timer_read(void)
  48 {
  49         int delay = 100;
  50
  51         __raw_writel(1, TIMERS_VIRT_BASE + TMR_CVWR(1));
  52
  53         while (delay--)
  54                 cpu_relax();
  55
  56         return __raw_readl(TIMERS_VIRT_BASE + TMR_CVWR(1));
  57 }
  58
  59 static u32 notrace mmp_read_sched_clock(void)
  60 {
  61         return timer_read();
  62 }
  63
  64 static irqreturn_t timer_interrupt(int irq, void *dev_id)
  65 {
  66         struct clock_event_device *c = dev_id;
  67
  68         /*
  69          * Clear pending interrupt status.
  70          */
  71         __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0));
  72
  73         /*
  74          * Disable timer 0.
  75          */
  76         __raw_writel(0x02, TIMERS_VIRT_BASE + TMR_CER);
  77
  78         c->event_handler(c);
  79
  80         return IRQ_HANDLED;
  81 }
  82
  83 static int timer_set_next_event(unsigned long delta,
  84                                 struct clock_event_device *dev)
  85 {
  86         unsigned long flags;
  87
  88         local_irq_save(flags);
  89
  90         /*
  91          * Disable timer 0.
  92          */
  93         __raw_writel(0x02, TIMERS_VIRT_BASE + TMR_CER);
  94
  95         /*
  96          * Clear and enable timer match 0 interrupt.
  97          */
  98         __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0));
  99         __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_IER(0));
 100
 101         /*
 102          * Setup new clockevent timer value.
 103          */
 104         __raw_writel(delta - 1, TIMERS_VIRT_BASE + TMR_TN_MM(0, 0));
 105
 106         /*
 107          * Enable timer 0.
 108          */
 109         __raw_writel(0x03, TIMERS_VIRT_BASE + TMR_CER);
 110
 111         local_irq_restore(flags);
 112
 113         return 0;
 114 }
 115
 116 static void timer_set_mode(enum clock_event_mode mode,
 117                            struct clock_event_device *dev)
 118 {
 119         unsigned long flags;
 120
 121         local_irq_save(flags);
 122         switch (mode) {
 123         case CLOCK_EVT_MODE_ONESHOT:
 124         case CLOCK_EVT_MODE_UNUSED:
 125         case CLOCK_EVT_MODE_SHUTDOWN:
 126                 /* disable the matching interrupt */
 127                 __raw_writel(0x00, TIMERS_VIRT_BASE + TMR_IER(0));
 128                 break;
 129         case CLOCK_EVT_MODE_RESUME:
 130         case CLOCK_EVT_MODE_PERIODIC:
 131                 break;
 132         }
 133         local_irq_restore(flags);
 134 }
 135
 136 static struct clock_event_device ckevt = {
 137         .name           = "clockevent",
 138         .features       = CLOCK_EVT_FEAT_ONESHOT,
 139         .shift          = 32,
 140         .rating         = 200,
 141         .set_next_event = timer_set_next_event,
 142         .set_mode       = timer_set_mode,
 143 };
 144
 145 static cycle_t clksrc_read(struct clocksource *cs)
 146 {
 147         return timer_read();
 148 }
 149
 150 static struct clocksource cksrc = {
 151         .name           = "clocksource",
 152         .rating         = 200,
 153         .read           = clksrc_read,
 154         .mask           = CLOCKSOURCE_MASK(32),
 155         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 156 };
 157
 158 static void __init timer_config(void)
 159 {
 160         uint32_t ccr = __raw_readl(TIMERS_VIRT_BASE + TMR_CCR);
 161
 162         __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_CER); /* disable */
 163
 164         ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
 165                 (TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
 166         __raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR);
 167
 168         /* set timer 0 to periodic mode, and timer 1 to free-running mode */
 169         __raw_writel(0x2, TIMERS_VIRT_BASE + TMR_CMR);
 170
 171         __raw_writel(0x1, TIMERS_VIRT_BASE + TMR_PLCR(0)); /* periodic */
 172         __raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(0));  /* clear status */
 173         __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0));
 174
 175         __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_PLCR(1)); /* free-running */
 176         __raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(1));  /* clear status */
 177         __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(1));
 178
 179         /* enable timer 1 counter */
 180         __raw_writel(0x2, TIMERS_VIRT_BASE + TMR_CER);
 181 }
 182
 183 static struct irqaction timer_irq = {
 184         .name           = "timer",
 185         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 186         .handler        = timer_interrupt,
 187         .dev_id         = &ckevt,
 188 };
 189
 190 void __init timer_init(int irq)
 191 {
 192         timer_config();
 193
 194         setup_sched_clock(mmp_read_sched_clock, 32, CLOCK_TICK_RATE);
 195
 196         ckevt.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt.shift);
 197         ckevt.max_delta_ns = clockevent_delta2ns(MAX_DELTA, &ckevt);
 198         ckevt.min_delta_ns = clockevent_delta2ns(MIN_DELTA, &ckevt);
 199         ckevt.cpumask = cpumask_of(0);
 200
 201         setup_irq(irq, &timer_irq);
 202
 203         clocksource_register_hz(&cksrc, CLOCK_TICK_RATE);
 204         clockevents_register_device(&ckevt);
 205 }