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spi-topcliff-pch: add recovery processing in case wait-event timeout
[zen-stable.git] / arch / arm / mach-mxs / clock-mx28.c
blob5d68e415222026c327dd1cd47d285d74c673fcc9
1 /*
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19 #include <linux/mm.h>
20 #include <linux/delay.h>
21 #include <linux/clk.h>
22 #include <linux/io.h>
23 #include <linux/jiffies.h>
24 #include <linux/clkdev.h>
25 #include <linux/spinlock.h>
26
27 #include <asm/clkdev.h>
28 #include <asm/div64.h>
29
30 #include <mach/mx28.h>
31 #include <mach/common.h>
32 #include <mach/clock.h>
33 #include <mach/digctl.h>
34
35 #include "regs-clkctrl-mx28.h"
36
37 #define CLKCTRL_BASE_ADDR MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR)
38 #define DIGCTRL_BASE_ADDR MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR)
39
40 #define PARENT_RATE_SHIFT 8
41
42 static struct clk pll2_clk;
43 static struct clk cpu_clk;
44 static struct clk emi_clk;
45 static struct clk saif0_clk;
46 static struct clk saif1_clk;
47 static struct clk clk32k_clk;
48 static DEFINE_SPINLOCK(clkmux_lock);
49
50 /*
51 * HW_SAIF_CLKMUX_SEL:
52 * DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1
53 * clock pins selected for SAIF1 input clocks.
54 * CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and
55 * SAIF0 clock inputs selected for SAIF1 input clocks.
56 * EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input
57 * clocks.
58 * EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input
59 * clocks.
60 */
61 int mxs_saif_clkmux_select(unsigned int clkmux)
62 {
63 if (clkmux > 0x3)
64 return -EINVAL;
65
66 spin_lock(&clkmux_lock);
67 __raw_writel(BM_DIGCTL_CTRL_SAIF_CLKMUX,
68 DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL + MXS_CLR_ADDR);
69 __raw_writel(clkmux << BP_DIGCTL_CTRL_SAIF_CLKMUX,
70 DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL + MXS_SET_ADDR);
71 spin_unlock(&clkmux_lock);
72
73 return 0;
74 }
75
76 static int _raw_clk_enable(struct clk *clk)
77 {
78 u32 reg;
79
80 if (clk->enable_reg) {
81 reg = __raw_readl(clk->enable_reg);
82 reg &= ~(1 << clk->enable_shift);
83 __raw_writel(reg, clk->enable_reg);
84 }
85
86 return 0;
87 }
88
89 static void _raw_clk_disable(struct clk *clk)
90 {
91 u32 reg;
92
93 if (clk->enable_reg) {
94 reg = __raw_readl(clk->enable_reg);
95 reg |= 1 << clk->enable_shift;
96 __raw_writel(reg, clk->enable_reg);
97 }
98 }
99
100 /*
101 * ref_xtal_clk
102 */
103 static unsigned long ref_xtal_clk_get_rate(struct clk *clk)
104 {
105 return 24000000;
106 }
107
108 static struct clk ref_xtal_clk = {
109 .get_rate = ref_xtal_clk_get_rate,
110 };
111
112 /*
113 * pll_clk
114 */
115 static unsigned long pll0_clk_get_rate(struct clk *clk)
116 {
117 return 480000000;
118 }
119
120 static unsigned long pll1_clk_get_rate(struct clk *clk)
121 {
122 return 480000000;
123 }
124
125 static unsigned long pll2_clk_get_rate(struct clk *clk)
126 {
127 return 50000000;
128 }
129
130 #define _CLK_ENABLE_PLL(name, r, g) \
131 static int name##_enable(struct clk *clk) \
132 { \
133 __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER, \
134 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
135 udelay(10); \
136 \
137 if (clk == &pll2_clk) \
138 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
139 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
140 else \
141 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
142 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
143 \
144 return 0; \
145 }
146
147 _CLK_ENABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
148 _CLK_ENABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
149 _CLK_ENABLE_PLL(pll2_clk, PLL2, CLKGATE)
150
151 #define _CLK_DISABLE_PLL(name, r, g) \
152 static void name##_disable(struct clk *clk) \
153 { \
154 __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER, \
155 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
156 \
157 if (clk == &pll2_clk) \
158 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
159 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
160 else \
161 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
162 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
163 \
164 }
165
166 _CLK_DISABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
167 _CLK_DISABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
168 _CLK_DISABLE_PLL(pll2_clk, PLL2, CLKGATE)
169
170 #define _DEFINE_CLOCK_PLL(name) \
171 static struct clk name = { \
172 .get_rate = name##_get_rate, \
173 .enable = name##_enable, \
174 .disable = name##_disable, \
175 .parent = &ref_xtal_clk, \
176 }
177
178 _DEFINE_CLOCK_PLL(pll0_clk);
179 _DEFINE_CLOCK_PLL(pll1_clk);
180 _DEFINE_CLOCK_PLL(pll2_clk);
181
182 /*
183 * ref_clk
184 */
185 #define _CLK_GET_RATE_REF(name, sr, ss) \
186 static unsigned long name##_get_rate(struct clk *clk) \
187 { \
188 unsigned long parent_rate; \
189 u32 reg, div; \
190 \
191 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr); \
192 div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f; \
193 parent_rate = clk_get_rate(clk->parent); \
194 \
195 return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18, \
196 div, PARENT_RATE_SHIFT); \
197 }
198
199 _CLK_GET_RATE_REF(ref_cpu_clk, FRAC0, CPU)
200 _CLK_GET_RATE_REF(ref_emi_clk, FRAC0, EMI)
201 _CLK_GET_RATE_REF(ref_io0_clk, FRAC0, IO0)
202 _CLK_GET_RATE_REF(ref_io1_clk, FRAC0, IO1)
203 _CLK_GET_RATE_REF(ref_pix_clk, FRAC1, PIX)
204 _CLK_GET_RATE_REF(ref_gpmi_clk, FRAC1, GPMI)
205
206 #define _DEFINE_CLOCK_REF(name, er, es) \
207 static struct clk name = { \
208 .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
209 .enable_shift = BP_CLKCTRL_##er##_CLKGATE##es, \
210 .get_rate = name##_get_rate, \
211 .enable = _raw_clk_enable, \
212 .disable = _raw_clk_disable, \
213 .parent = &pll0_clk, \
214 }
215
216 _DEFINE_CLOCK_REF(ref_cpu_clk, FRAC0, CPU);
217 _DEFINE_CLOCK_REF(ref_emi_clk, FRAC0, EMI);
218 _DEFINE_CLOCK_REF(ref_io0_clk, FRAC0, IO0);
219 _DEFINE_CLOCK_REF(ref_io1_clk, FRAC0, IO1);
220 _DEFINE_CLOCK_REF(ref_pix_clk, FRAC1, PIX);
221 _DEFINE_CLOCK_REF(ref_gpmi_clk, FRAC1, GPMI);
222
223 /*
224 * General clocks
225 *
226 * clk_get_rate
227 */
228 static unsigned long lradc_clk_get_rate(struct clk *clk)
229 {
230 return clk_get_rate(clk->parent) / 16;
231 }
232
233 static unsigned long rtc_clk_get_rate(struct clk *clk)
234 {
235 /* ref_xtal_clk is implemented as the only parent */
236 return clk_get_rate(clk->parent) / 768;
237 }
238
239 static unsigned long clk32k_clk_get_rate(struct clk *clk)
240 {
241 return clk->parent->get_rate(clk->parent) / 750;
242 }
243
244 static unsigned long spdif_clk_get_rate(struct clk *clk)
245 {
246 return clk_get_rate(clk->parent) / 4;
247 }
248
249 #define _CLK_GET_RATE(name, rs) \
250 static unsigned long name##_get_rate(struct clk *clk) \
251 { \
252 u32 reg, div; \
253 \
254 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
255 \
256 if (clk->parent == &ref_xtal_clk) \
257 div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >> \
258 BP_CLKCTRL_##rs##_DIV_XTAL; \
259 else \
260 div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >> \
261 BP_CLKCTRL_##rs##_DIV_##rs; \
262 \
263 if (!div) \
264 return -EINVAL; \
265 \
266 return clk_get_rate(clk->parent) / div; \
267 }
268
269 _CLK_GET_RATE(cpu_clk, CPU)
270 _CLK_GET_RATE(emi_clk, EMI)
271
272 #define _CLK_GET_RATE1(name, rs) \
273 static unsigned long name##_get_rate(struct clk *clk) \
274 { \
275 u32 reg, div; \
276 \
277 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
278 div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV; \
279 \
280 if (!div) \
281 return -EINVAL; \
282 \
283 if (clk == &saif0_clk || clk == &saif1_clk) \
284 return clk_get_rate(clk->parent) >> 16 * div; \
285 else \
286 return clk_get_rate(clk->parent) / div; \
287 }
288
289 _CLK_GET_RATE1(hbus_clk, HBUS)
290 _CLK_GET_RATE1(xbus_clk, XBUS)
291 _CLK_GET_RATE1(ssp0_clk, SSP0)
292 _CLK_GET_RATE1(ssp1_clk, SSP1)
293 _CLK_GET_RATE1(ssp2_clk, SSP2)
294 _CLK_GET_RATE1(ssp3_clk, SSP3)
295 _CLK_GET_RATE1(gpmi_clk, GPMI)
296 _CLK_GET_RATE1(lcdif_clk, DIS_LCDIF)
297 _CLK_GET_RATE1(saif0_clk, SAIF0)
298 _CLK_GET_RATE1(saif1_clk, SAIF1)
299
300 #define _CLK_GET_RATE_STUB(name) \
301 static unsigned long name##_get_rate(struct clk *clk) \
302 { \
303 return clk_get_rate(clk->parent); \
304 }
305
306 _CLK_GET_RATE_STUB(uart_clk)
307 _CLK_GET_RATE_STUB(pwm_clk)
308 _CLK_GET_RATE_STUB(can0_clk)
309 _CLK_GET_RATE_STUB(can1_clk)
310 _CLK_GET_RATE_STUB(fec_clk)
311
312 /*
313 * clk_set_rate
314 */
315 /* fool compiler */
316 #define BM_CLKCTRL_CPU_DIV 0
317 #define BP_CLKCTRL_CPU_DIV 0
318 #define BM_CLKCTRL_CPU_BUSY 0
319
320 #define _CLK_SET_RATE(name, dr, fr, fs) \
321 static int name##_set_rate(struct clk *clk, unsigned long rate) \
322 { \
323 u32 reg, bm_busy, div_max, d, f, div, frac; \
324 unsigned long diff, parent_rate, calc_rate; \
325 int i; \
326 \
327 div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \
328 bm_busy = BM_CLKCTRL_##dr##_BUSY; \
329 \
330 if (clk->parent == &ref_xtal_clk) { \
331 parent_rate = clk_get_rate(clk->parent); \
332 div = DIV_ROUND_UP(parent_rate, rate); \
333 if (clk == &cpu_clk) { \
334 div_max = BM_CLKCTRL_CPU_DIV_XTAL >> \
335 BP_CLKCTRL_CPU_DIV_XTAL; \
336 bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL; \
337 } \
338 if (div == 0 || div > div_max) \
339 return -EINVAL; \
340 } else { \
341 /* \
342 * hack alert: this block modifies clk->parent, too, \
343 * so the base to use it the grand parent. \
344 */ \
345 parent_rate = clk_get_rate(clk->parent->parent); \
346 rate >>= PARENT_RATE_SHIFT; \
347 parent_rate >>= PARENT_RATE_SHIFT; \
348 diff = parent_rate; \
349 div = frac = 1; \
350 if (clk == &cpu_clk) { \
351 div_max = BM_CLKCTRL_CPU_DIV_CPU >> \
352 BP_CLKCTRL_CPU_DIV_CPU; \
353 bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU; \
354 } \
355 for (d = 1; d <= div_max; d++) { \
356 f = parent_rate * 18 / d / rate; \
357 if ((parent_rate * 18 / d) % rate) \
358 f++; \
359 if (f < 18 || f > 35) \
360 continue; \
361 \
362 calc_rate = parent_rate * 18 / f / d; \
363 if (calc_rate > rate) \
364 continue; \
365 \
366 if (rate - calc_rate < diff) { \
367 frac = f; \
368 div = d; \
369 diff = rate - calc_rate; \
370 } \
371 \
372 if (diff == 0) \
373 break; \
374 } \
375 \
376 if (diff == parent_rate) \
377 return -EINVAL; \
378 \
379 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
380 reg &= ~BM_CLKCTRL_##fr##_##fs##FRAC; \
381 reg |= frac << BP_CLKCTRL_##fr##_##fs##FRAC; \
382 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
383 } \
384 \
385 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
386 if (clk == &cpu_clk) { \
387 reg &= ~BM_CLKCTRL_CPU_DIV_CPU; \
388 reg |= div << BP_CLKCTRL_CPU_DIV_CPU; \
389 } else { \
390 reg &= ~BM_CLKCTRL_##dr##_DIV; \
391 reg |= div << BP_CLKCTRL_##dr##_DIV; \
392 if (reg & (1 << clk->enable_shift)) { \
393 pr_err("%s: clock is gated\n", __func__); \
394 return -EINVAL; \
395 } \
396 } \
397 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
398 \
399 for (i = 10000; i; i--) \
400 if (!(__raw_readl(CLKCTRL_BASE_ADDR + \
401 HW_CLKCTRL_##dr) & bm_busy)) \
402 break; \
403 if (!i) { \
404 pr_err("%s: divider writing timeout\n", __func__); \
405 return -ETIMEDOUT; \
406 } \
407 \
408 return 0; \
409 }
410
411 _CLK_SET_RATE(cpu_clk, CPU, FRAC0, CPU)
412 _CLK_SET_RATE(ssp0_clk, SSP0, FRAC0, IO0)
413 _CLK_SET_RATE(ssp1_clk, SSP1, FRAC0, IO0)
414 _CLK_SET_RATE(ssp2_clk, SSP2, FRAC0, IO1)
415 _CLK_SET_RATE(ssp3_clk, SSP3, FRAC0, IO1)
416 _CLK_SET_RATE(lcdif_clk, DIS_LCDIF, FRAC1, PIX)
417 _CLK_SET_RATE(gpmi_clk, GPMI, FRAC1, GPMI)
418
419 #define _CLK_SET_RATE1(name, dr) \
420 static int name##_set_rate(struct clk *clk, unsigned long rate) \
421 { \
422 u32 reg, div_max, div; \
423 unsigned long parent_rate; \
424 int i; \
425 \
426 parent_rate = clk_get_rate(clk->parent); \
427 div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \
428 \
429 div = DIV_ROUND_UP(parent_rate, rate); \
430 if (div == 0 || div > div_max) \
431 return -EINVAL; \
432 \
433 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
434 reg &= ~BM_CLKCTRL_##dr##_DIV; \
435 reg |= div << BP_CLKCTRL_##dr##_DIV; \
436 if (reg & (1 << clk->enable_shift)) { \
437 pr_err("%s: clock is gated\n", __func__); \
438 return -EINVAL; \
439 } \
440 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
441 \
442 for (i = 10000; i; i--) \
443 if (!(__raw_readl(CLKCTRL_BASE_ADDR + \
444 HW_CLKCTRL_##dr) & BM_CLKCTRL_##dr##_BUSY)) \
445 break; \
446 if (!i) { \
447 pr_err("%s: divider writing timeout\n", __func__); \
448 return -ETIMEDOUT; \
449 } \
450 \
451 return 0; \
452 }
453
454 _CLK_SET_RATE1(xbus_clk, XBUS)
455
456 /* saif clock uses 16 bits frac div */
457 #define _CLK_SET_RATE_SAIF(name, rs) \
458 static int name##_set_rate(struct clk *clk, unsigned long rate) \
459 { \
460 u16 div; \
461 u32 reg; \
462 u64 lrate; \
463 unsigned long parent_rate; \
464 int i; \
465 \
466 parent_rate = clk_get_rate(clk->parent); \
467 if (rate > parent_rate) \
468 return -EINVAL; \
469 \
470 lrate = (u64)rate << 16; \
471 do_div(lrate, parent_rate); \
472 div = (u16)lrate; \
473 \
474 if (!div) \
475 return -EINVAL; \
476 \
477 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
478 reg &= ~BM_CLKCTRL_##rs##_DIV; \
479 reg |= div << BP_CLKCTRL_##rs##_DIV; \
480 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
481 \
482 for (i = 10000; i; i--) \
483 if (!(__raw_readl(CLKCTRL_BASE_ADDR + \
484 HW_CLKCTRL_##rs) & BM_CLKCTRL_##rs##_BUSY)) \
485 break; \
486 if (!i) { \
487 pr_err("%s: divider writing timeout\n", __func__); \
488 return -ETIMEDOUT; \
489 } \
490 \
491 return 0; \
492 }
493
494 _CLK_SET_RATE_SAIF(saif0_clk, SAIF0)
495 _CLK_SET_RATE_SAIF(saif1_clk, SAIF1)
496
497 #define _CLK_SET_RATE_STUB(name) \
498 static int name##_set_rate(struct clk *clk, unsigned long rate) \
499 { \
500 return -EINVAL; \
501 }
502
503 _CLK_SET_RATE_STUB(emi_clk)
504 _CLK_SET_RATE_STUB(uart_clk)
505 _CLK_SET_RATE_STUB(pwm_clk)
506 _CLK_SET_RATE_STUB(spdif_clk)
507 _CLK_SET_RATE_STUB(clk32k_clk)
508 _CLK_SET_RATE_STUB(can0_clk)
509 _CLK_SET_RATE_STUB(can1_clk)
510 _CLK_SET_RATE_STUB(fec_clk)
511
512 /*
513 * clk_set_parent
514 */
515 #define _CLK_SET_PARENT(name, bit) \
516 static int name##_set_parent(struct clk *clk, struct clk *parent) \
517 { \
518 if (parent != clk->parent) { \
519 __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit, \
520 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ_TOG); \
521 clk->parent = parent; \
522 } \
523 \
524 return 0; \
525 }
526
527 _CLK_SET_PARENT(cpu_clk, CPU)
528 _CLK_SET_PARENT(emi_clk, EMI)
529 _CLK_SET_PARENT(ssp0_clk, SSP0)
530 _CLK_SET_PARENT(ssp1_clk, SSP1)
531 _CLK_SET_PARENT(ssp2_clk, SSP2)
532 _CLK_SET_PARENT(ssp3_clk, SSP3)
533 _CLK_SET_PARENT(lcdif_clk, DIS_LCDIF)
534 _CLK_SET_PARENT(gpmi_clk, GPMI)
535 _CLK_SET_PARENT(saif0_clk, SAIF0)
536 _CLK_SET_PARENT(saif1_clk, SAIF1)
537
538 #define _CLK_SET_PARENT_STUB(name) \
539 static int name##_set_parent(struct clk *clk, struct clk *parent) \
540 { \
541 if (parent != clk->parent) \
542 return -EINVAL; \
543 else \
544 return 0; \
545 }
546
547 _CLK_SET_PARENT_STUB(pwm_clk)
548 _CLK_SET_PARENT_STUB(uart_clk)
549 _CLK_SET_PARENT_STUB(clk32k_clk)
550 _CLK_SET_PARENT_STUB(spdif_clk)
551 _CLK_SET_PARENT_STUB(fec_clk)
552 _CLK_SET_PARENT_STUB(can0_clk)
553 _CLK_SET_PARENT_STUB(can1_clk)
554
555 /*
556 * clk definition
557 */
558 static struct clk cpu_clk = {
559 .get_rate = cpu_clk_get_rate,
560 .set_rate = cpu_clk_set_rate,
561 .set_parent = cpu_clk_set_parent,
562 .parent = &ref_cpu_clk,
563 };
564
565 static struct clk hbus_clk = {
566 .get_rate = hbus_clk_get_rate,
567 .parent = &cpu_clk,
568 };
569
570 static struct clk xbus_clk = {
571 .get_rate = xbus_clk_get_rate,
572 .set_rate = xbus_clk_set_rate,
573 .parent = &ref_xtal_clk,
574 };
575
576 static struct clk lradc_clk = {
577 .get_rate = lradc_clk_get_rate,
578 .parent = &clk32k_clk,
579 };
580
581 static struct clk rtc_clk = {
582 .get_rate = rtc_clk_get_rate,
583 .parent = &ref_xtal_clk,
584 };
585
586 /* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */
587 static struct clk usb0_clk = {
588 .enable_reg = DIGCTRL_BASE_ADDR,
589 .enable_shift = 2,
590 .enable = _raw_clk_enable,
591 .disable = _raw_clk_disable,
592 .parent = &pll0_clk,
593 };
594
595 static struct clk usb1_clk = {
596 .enable_reg = DIGCTRL_BASE_ADDR,
597 .enable_shift = 16,
598 .enable = _raw_clk_enable,
599 .disable = _raw_clk_disable,
600 .parent = &pll1_clk,
601 };
602
603 #define _DEFINE_CLOCK(name, er, es, p) \
604 static struct clk name = { \
605 .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
606 .enable_shift = BP_CLKCTRL_##er##_##es, \
607 .get_rate = name##_get_rate, \
608 .set_rate = name##_set_rate, \
609 .set_parent = name##_set_parent, \
610 .enable = _raw_clk_enable, \
611 .disable = _raw_clk_disable, \
612 .parent = p, \
613 }
614
615 _DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk);
616 _DEFINE_CLOCK(ssp0_clk, SSP0, CLKGATE, &ref_xtal_clk);
617 _DEFINE_CLOCK(ssp1_clk, SSP1, CLKGATE, &ref_xtal_clk);
618 _DEFINE_CLOCK(ssp2_clk, SSP2, CLKGATE, &ref_xtal_clk);
619 _DEFINE_CLOCK(ssp3_clk, SSP3, CLKGATE, &ref_xtal_clk);
620 _DEFINE_CLOCK(lcdif_clk, DIS_LCDIF, CLKGATE, &ref_xtal_clk);
621 _DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk);
622 _DEFINE_CLOCK(saif0_clk, SAIF0, CLKGATE, &ref_xtal_clk);
623 _DEFINE_CLOCK(saif1_clk, SAIF1, CLKGATE, &ref_xtal_clk);
624 _DEFINE_CLOCK(can0_clk, FLEXCAN, STOP_CAN0, &ref_xtal_clk);
625 _DEFINE_CLOCK(can1_clk, FLEXCAN, STOP_CAN1, &ref_xtal_clk);
626 _DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk);
627 _DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk);
628 _DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
629 _DEFINE_CLOCK(spdif_clk, SPDIF, CLKGATE, &pll0_clk);
630 _DEFINE_CLOCK(fec_clk, ENET, DISABLE, &hbus_clk);
631
632 #define _REGISTER_CLOCK(d, n, c) \
633 { \
634 .dev_id = d, \
635 .con_id = n, \
636 .clk = &c, \
637 },
638
639 static struct clk_lookup lookups[] = {
640 /* for amba bus driver */
641 _REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
642 /* for amba-pl011 driver */
643 _REGISTER_CLOCK("duart", NULL, uart_clk)
644 _REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
645 _REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
646 _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
647 _REGISTER_CLOCK("mxs-auart.1", NULL, uart_clk)
648 _REGISTER_CLOCK("mxs-auart.2", NULL, uart_clk)
649 _REGISTER_CLOCK("mxs-auart.3", NULL, uart_clk)
650 _REGISTER_CLOCK("mxs-auart.4", NULL, uart_clk)
651 _REGISTER_CLOCK("rtc", NULL, rtc_clk)
652 _REGISTER_CLOCK("pll2", NULL, pll2_clk)
653 _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
654 _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
655 _REGISTER_CLOCK("mxs-mmc.0", NULL, ssp0_clk)
656 _REGISTER_CLOCK("mxs-mmc.1", NULL, ssp1_clk)
657 _REGISTER_CLOCK("flexcan.0", NULL, can0_clk)
658 _REGISTER_CLOCK("flexcan.1", NULL, can1_clk)
659 _REGISTER_CLOCK(NULL, "usb0", usb0_clk)
660 _REGISTER_CLOCK(NULL, "usb1", usb1_clk)
661 _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
662 _REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk)
663 _REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk)
664 _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
665 _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
666 _REGISTER_CLOCK("mxs-pwm.5", NULL, pwm_clk)
667 _REGISTER_CLOCK("mxs-pwm.6", NULL, pwm_clk)
668 _REGISTER_CLOCK("mxs-pwm.7", NULL, pwm_clk)
669 _REGISTER_CLOCK(NULL, "lradc", lradc_clk)
670 _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
671 _REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
672 _REGISTER_CLOCK("mxs-saif.0", NULL, saif0_clk)
673 _REGISTER_CLOCK("mxs-saif.1", NULL, saif1_clk)
674 };
675
676 static int clk_misc_init(void)
677 {
678 u32 reg;
679 int i;
680
681 /* Fix up parent per register setting */
682 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
683 cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ?
684 &ref_xtal_clk : &ref_cpu_clk;
685 emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ?
686 &ref_xtal_clk : &ref_emi_clk;
687 ssp0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP0) ?
688 &ref_xtal_clk : &ref_io0_clk;
689 ssp1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP1) ?
690 &ref_xtal_clk : &ref_io0_clk;
691 ssp2_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP2) ?
692 &ref_xtal_clk : &ref_io1_clk;
693 ssp3_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP3) ?
694 &ref_xtal_clk : &ref_io1_clk;
695 lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF) ?
696 &ref_xtal_clk : &ref_pix_clk;
697 gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ?
698 &ref_xtal_clk : &ref_gpmi_clk;
699 saif0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0) ?
700 &ref_xtal_clk : &pll0_clk;
701 saif1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1) ?
702 &ref_xtal_clk : &pll0_clk;
703
704 /* Use int div over frac when both are available */
705 __raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN,
706 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
707 __raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN,
708 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
709 __raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN,
710 CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
711
712 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
713 reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN;
714 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
715
716 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
717 reg &= ~BM_CLKCTRL_SSP0_DIV_FRAC_EN;
718 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
719
720 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
721 reg &= ~BM_CLKCTRL_SSP1_DIV_FRAC_EN;
722 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
723
724 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
725 reg &= ~BM_CLKCTRL_SSP2_DIV_FRAC_EN;
726 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
727
728 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
729 reg &= ~BM_CLKCTRL_SSP3_DIV_FRAC_EN;
730 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
731
732 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
733 reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN;
734 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
735
736 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
737 reg &= ~BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN;
738 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
739
740 /* SAIF has to use frac div for functional operation */
741 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
742 reg |= BM_CLKCTRL_SAIF0_DIV_FRAC_EN;
743 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
744
745 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
746 reg |= BM_CLKCTRL_SAIF1_DIV_FRAC_EN;
747 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
748
749 /*
750 * Set safe hbus clock divider. A divider of 3 ensure that
751 * the Vddd voltage required for the cpu clock is sufficiently
752 * high for the hbus clock.
753 */
754 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
755 reg &= BM_CLKCTRL_HBUS_DIV;
756 reg |= 3 << BP_CLKCTRL_HBUS_DIV;
757 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
758
759 for (i = 10000; i; i--)
760 if (!(__raw_readl(CLKCTRL_BASE_ADDR +
761 HW_CLKCTRL_HBUS) & BM_CLKCTRL_HBUS_ASM_BUSY))
762 break;
763 if (!i) {
764 pr_err("%s: divider writing timeout\n", __func__);
765 return -ETIMEDOUT;
766 }
767
768 /* Gate off cpu clock in WFI for power saving */
769 __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
770 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
771
772 /*
773 * Extra fec clock setting
774 * The DENX M28 uses an external clock source
775 * and the clock output must not be enabled
776 */
777 if (!machine_is_m28evk()) {
778 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
779 reg &= ~BM_CLKCTRL_ENET_SLEEP;
780 reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
781 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
782 }
783
784 /*
785 * 480 MHz seems too high to be ssp clock source directly,
786 * so set frac0 to get a 288 MHz ref_io0.
787 */
788 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0);
789 reg &= ~BM_CLKCTRL_FRAC0_IO0FRAC;
790 reg |= 30 << BP_CLKCTRL_FRAC0_IO0FRAC;
791 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0);
792
793 return 0;
794 }
795
796 int __init mx28_clocks_init(void)
797 {
798 clk_misc_init();
799
800 /*
801 * source ssp clock from ref_io0 than ref_xtal,
802 * as ref_xtal only provides 24 MHz as maximum.
803 */
804 clk_set_parent(&ssp0_clk, &ref_io0_clk);
805 clk_set_parent(&ssp1_clk, &ref_io0_clk);
806
807 clk_prepare_enable(&cpu_clk);
808 clk_prepare_enable(&hbus_clk);
809 clk_prepare_enable(&xbus_clk);
810 clk_prepare_enable(&emi_clk);
811 clk_prepare_enable(&uart_clk);
812
813 clk_set_parent(&lcdif_clk, &ref_pix_clk);
814 clk_set_parent(&saif0_clk, &pll0_clk);
815 clk_set_parent(&saif1_clk, &pll0_clk);
816
817 /*
818 * Set an initial clock rate for the saif internal logic to work
819 * properly. This is important when working in EXTMASTER mode that
820 * uses the other saif's BITCLK&LRCLK but it still needs a basic
821 * clock which should be fast enough for the internal logic.
822 */
823 clk_set_rate(&saif0_clk, 24000000);
824 clk_set_rate(&saif1_clk, 24000000);
825
826 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
827
828 mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0);
829
830 return 0;
831 }