2 * Copyright (C) 1999 ARM Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright 2006-2007,2010 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
6 * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/clk.h>
22 #include <linux/err.h>
23 #include <linux/delay.h>
24 #include <linux/init.h>
25 #include <linux/module.h>
27 #include <asm/proc-fns.h>
28 #include <asm/system.h>
31 #include <mach/common.h>
33 #define MX23_CLKCTRL_RESET_OFFSET 0x120
34 #define MX28_CLKCTRL_RESET_OFFSET 0x1e0
35 #define MXS_CLKCTRL_RESET_CHIP (1 << 1)
37 #define MXS_MODULE_CLKGATE (1 << 30)
38 #define MXS_MODULE_SFTRST (1 << 31)
40 static void __iomem
*mxs_clkctrl_reset_addr
;
43 * Reset the system. It is called by machine_restart().
45 void mxs_restart(char mode
, const char *cmd
)
48 __mxs_setl(MXS_CLKCTRL_RESET_CHIP
, mxs_clkctrl_reset_addr
);
50 pr_err("Failed to assert the chip reset\n");
52 /* Delay to allow the serial port to show the message */
55 /* We'll take a jump through zero as a poor second */
59 static int __init
mxs_arch_reset_init(void)
63 mxs_clkctrl_reset_addr
= MXS_IO_ADDRESS(MXS_CLKCTRL_BASE_ADDR
) +
64 (cpu_is_mx23() ? MX23_CLKCTRL_RESET_OFFSET
:
65 MX28_CLKCTRL_RESET_OFFSET
);
67 clk
= clk_get_sys("rtc", NULL
);
69 clk_prepare_enable(clk
);
73 core_initcall(mxs_arch_reset_init
);
76 * Clear the bit and poll it cleared. This is usually called with
77 * a reset address and mask being either SFTRST(bit 31) or CLKGATE
80 static int clear_poll_bit(void __iomem
*addr
, u32 mask
)
85 __mxs_clrl(mask
, addr
);
88 * SFTRST needs 3 GPMI clocks to settle, the reference manual
89 * recommends to wait 1us.
93 /* poll the bit becoming clear */
94 while ((__raw_readl(addr
) & mask
) && --timeout
)
100 int mxs_reset_block(void __iomem
*reset_addr
)
105 /* clear and poll SFTRST */
106 ret
= clear_poll_bit(reset_addr
, MXS_MODULE_SFTRST
);
111 __mxs_clrl(MXS_MODULE_CLKGATE
, reset_addr
);
113 /* set SFTRST to reset the block */
114 __mxs_setl(MXS_MODULE_SFTRST
, reset_addr
);
117 /* poll CLKGATE becoming set */
118 while ((!(__raw_readl(reset_addr
) & MXS_MODULE_CLKGATE
)) && --timeout
)
120 if (unlikely(!timeout
))
123 /* clear and poll SFTRST */
124 ret
= clear_poll_bit(reset_addr
, MXS_MODULE_SFTRST
);
128 /* clear and poll CLKGATE */
129 ret
= clear_poll_bit(reset_addr
, MXS_MODULE_CLKGATE
);
136 pr_err("%s(%p): module reset timeout\n", __func__
, reset_addr
);
139 EXPORT_SYMBOL(mxs_reset_block
);