arch/arm/mach-mxs/timer.c

   1 /*
   2  *  Copyright (C) 2000-2001 Deep Blue Solutions
   3  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   4  *  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
   5  *  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
   6  *  Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version 2
  11  * of the License, or (at your option) any later version.
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  20  * MA 02110-1301, USA.
  21  */
  22
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/clockchips.h>
  26 #include <linux/clk.h>
  27
  28 #include <asm/mach/time.h>
  29 #include <mach/mxs.h>
  30 #include <mach/common.h>
  31
  32 /*
  33  * There are 2 versions of the timrot on Freescale MXS-based SoCs.
  34  * The v1 on MX23 only gets 16 bits counter, while v2 on MX28
  35  * extends the counter to 32 bits.
  36  *
  37  * The implementation uses two timers, one for clock_event and
  38  * another for clocksource. MX28 uses timrot 0 and 1, while MX23
  39  * uses 0 and 2.
  40  */
  41
  42 #define MX23_TIMROT_VERSION_OFFSET      0x0a0
  43 #define MX28_TIMROT_VERSION_OFFSET      0x120
  44 #define BP_TIMROT_MAJOR_VERSION         24
  45 #define BV_TIMROT_VERSION_1             0x01
  46 #define BV_TIMROT_VERSION_2             0x02
  47 #define timrot_is_v1()  (timrot_major_version == BV_TIMROT_VERSION_1)
  48
  49 /*
  50  * There are 4 registers for each timrotv2 instance, and 2 registers
  51  * for each timrotv1. So address step 0x40 in macros below strides
  52  * one instance of timrotv2 while two instances of timrotv1.
  53  *
  54  * As the result, HW_TIMROT_XXXn(1) defines the address of timrot1
  55  * on MX28 while timrot2 on MX23.
  56  */
  57 /* common between v1 and v2 */
  58 #define HW_TIMROT_ROTCTRL               0x00
  59 #define HW_TIMROT_TIMCTRLn(n)           (0x20 + (n) * 0x40)
  60 /* v1 only */
  61 #define HW_TIMROT_TIMCOUNTn(n)          (0x30 + (n) * 0x40)
  62 /* v2 only */
  63 #define HW_TIMROT_RUNNING_COUNTn(n)     (0x30 + (n) * 0x40)
  64 #define HW_TIMROT_FIXED_COUNTn(n)       (0x40 + (n) * 0x40)
  65
  66 #define BM_TIMROT_TIMCTRLn_RELOAD       (1 << 6)
  67 #define BM_TIMROT_TIMCTRLn_UPDATE       (1 << 7)
  68 #define BM_TIMROT_TIMCTRLn_IRQ_EN       (1 << 14)
  69 #define BM_TIMROT_TIMCTRLn_IRQ          (1 << 15)
  70 #define BP_TIMROT_TIMCTRLn_SELECT       0
  71 #define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL 0x8
  72 #define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL 0xb
  73
  74 static struct clock_event_device mxs_clockevent_device;
  75 static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED;
  76
  77 static void __iomem *mxs_timrot_base = MXS_IO_ADDRESS(MXS_TIMROT_BASE_ADDR);
  78 static u32 timrot_major_version;
  79
  80 static inline void timrot_irq_disable(void)
  81 {
  82         __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ_EN,
  83                         mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
  84 }
  85
  86 static inline void timrot_irq_enable(void)
  87 {
  88         __mxs_setl(BM_TIMROT_TIMCTRLn_IRQ_EN,
  89                         mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
  90 }
  91
  92 static void timrot_irq_acknowledge(void)
  93 {
  94         __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ,
  95                         mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
  96 }
  97
  98 static cycle_t timrotv1_get_cycles(struct clocksource *cs)
  99 {
 100         return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1))
 101                         & 0xffff0000) >> 16);
 102 }
 103
 104 static int timrotv1_set_next_event(unsigned long evt,
 105                                         struct clock_event_device *dev)
 106 {
 107         /* timrot decrements the count */
 108         __raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0));
 109
 110         return 0;
 111 }
 112
 113 static int timrotv2_set_next_event(unsigned long evt,
 114                                         struct clock_event_device *dev)
 115 {
 116         /* timrot decrements the count */
 117         __raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0));
 118
 119         return 0;
 120 }
 121
 122 static irqreturn_t mxs_timer_interrupt(int irq, void *dev_id)
 123 {
 124         struct clock_event_device *evt = dev_id;
 125
 126         timrot_irq_acknowledge();
 127         evt->event_handler(evt);
 128
 129         return IRQ_HANDLED;
 130 }
 131
 132 static struct irqaction mxs_timer_irq = {
 133         .name           = "MXS Timer Tick",
 134         .dev_id         = &mxs_clockevent_device,
 135         .flags          = IRQF_TIMER | IRQF_IRQPOLL,
 136         .handler        = mxs_timer_interrupt,
 137 };
 138
 139 #ifdef DEBUG
 140 static const char *clock_event_mode_label[] const = {
 141         [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
 142         [CLOCK_EVT_MODE_ONESHOT]  = "CLOCK_EVT_MODE_ONESHOT",
 143         [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
 144         [CLOCK_EVT_MODE_UNUSED]   = "CLOCK_EVT_MODE_UNUSED"
 145 };
 146 #endif /* DEBUG */
 147
 148 static void mxs_set_mode(enum clock_event_mode mode,
 149                                 struct clock_event_device *evt)
 150 {
 151         /* Disable interrupt in timer module */
 152         timrot_irq_disable();
 153
 154         if (mode != mxs_clockevent_mode) {
 155                 /* Set event time into the furthest future */
 156                 if (timrot_is_v1())
 157                         __raw_writel(0xffff,
 158                                 mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
 159                 else
 160                         __raw_writel(0xffffffff,
 161                                 mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
 162
 163                 /* Clear pending interrupt */
 164                 timrot_irq_acknowledge();
 165         }
 166
 167 #ifdef DEBUG
 168         pr_info("%s: changing mode from %s to %s\n", __func__,
 169                 clock_event_mode_label[mxs_clockevent_mode],
 170                 clock_event_mode_label[mode]);
 171 #endif /* DEBUG */
 172
 173         /* Remember timer mode */
 174         mxs_clockevent_mode = mode;
 175
 176         switch (mode) {
 177         case CLOCK_EVT_MODE_PERIODIC:
 178                 pr_err("%s: Periodic mode is not implemented\n", __func__);
 179                 break;
 180         case CLOCK_EVT_MODE_ONESHOT:
 181                 timrot_irq_enable();
 182                 break;
 183         case CLOCK_EVT_MODE_SHUTDOWN:
 184         case CLOCK_EVT_MODE_UNUSED:
 185         case CLOCK_EVT_MODE_RESUME:
 186                 /* Left event sources disabled, no more interrupts appear */
 187                 break;
 188         }
 189 }
 190
 191 static struct clock_event_device mxs_clockevent_device = {
 192         .name           = "mxs_timrot",
 193         .features       = CLOCK_EVT_FEAT_ONESHOT,
 194         .shift          = 32,
 195         .set_mode       = mxs_set_mode,
 196         .set_next_event = timrotv2_set_next_event,
 197         .rating         = 200,
 198 };
 199
 200 static int __init mxs_clockevent_init(struct clk *timer_clk)
 201 {
 202         unsigned int c = clk_get_rate(timer_clk);
 203
 204         mxs_clockevent_device.mult =
 205                 div_sc(c, NSEC_PER_SEC, mxs_clockevent_device.shift);
 206         mxs_clockevent_device.cpumask = cpumask_of(0);
 207         if (timrot_is_v1()) {
 208                 mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
 209                 mxs_clockevent_device.max_delta_ns =
 210                         clockevent_delta2ns(0xfffe, &mxs_clockevent_device);
 211                 mxs_clockevent_device.min_delta_ns =
 212                         clockevent_delta2ns(0xf, &mxs_clockevent_device);
 213         } else {
 214                 mxs_clockevent_device.max_delta_ns =
 215                         clockevent_delta2ns(0xfffffffe, &mxs_clockevent_device);
 216                 mxs_clockevent_device.min_delta_ns =
 217                         clockevent_delta2ns(0xf, &mxs_clockevent_device);
 218         }
 219
 220         clockevents_register_device(&mxs_clockevent_device);
 221
 222         return 0;
 223 }
 224
 225 static struct clocksource clocksource_mxs = {
 226         .name           = "mxs_timer",
 227         .rating         = 200,
 228         .read           = timrotv1_get_cycles,
 229         .mask           = CLOCKSOURCE_MASK(16),
 230         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 231 };
 232
 233 static int __init mxs_clocksource_init(struct clk *timer_clk)
 234 {
 235         unsigned int c = clk_get_rate(timer_clk);
 236
 237         if (timrot_is_v1())
 238                 clocksource_register_hz(&clocksource_mxs, c);
 239         else
 240                 clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1),
 241                         "mxs_timer", c, 200, 32, clocksource_mmio_readl_down);
 242
 243         return 0;
 244 }
 245
 246 void __init mxs_timer_init(struct clk *timer_clk, int irq)
 247 {
 248         clk_prepare_enable(timer_clk);
 249
 250         /*
 251          * Initialize timers to a known state
 252          */
 253         mxs_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);
 254
 255         /* get timrot version */
 256         timrot_major_version = __raw_readl(mxs_timrot_base +
 257                                 (cpu_is_mx23() ? MX23_TIMROT_VERSION_OFFSET :
 258                                                 MX28_TIMROT_VERSION_OFFSET));
 259         timrot_major_version >>= BP_TIMROT_MAJOR_VERSION;
 260
 261         /* one for clock_event */
 262         __raw_writel((timrot_is_v1() ?
 263                         BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
 264                         BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) |
 265                         BM_TIMROT_TIMCTRLn_UPDATE |
 266                         BM_TIMROT_TIMCTRLn_IRQ_EN,
 267                         mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
 268
 269         /* another for clocksource */
 270         __raw_writel((timrot_is_v1() ?
 271                         BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
 272                         BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) |
 273                         BM_TIMROT_TIMCTRLn_RELOAD,
 274                         mxs_timrot_base + HW_TIMROT_TIMCTRLn(1));
 275
 276         /* set clocksource timer fixed count to the maximum */
 277         if (timrot_is_v1())
 278                 __raw_writel(0xffff,
 279                         mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
 280         else
 281                 __raw_writel(0xffffffff,
 282                         mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
 283
 284         /* init and register the timer to the framework */
 285         mxs_clocksource_init(timer_clk);
 286         mxs_clockevent_init(timer_clk);
 287
 288         /* Make irqs happen */
 289         setup_irq(irq, &mxs_timer_irq);
 290 }