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spi-topcliff-pch: add recovery processing in case wait-event timeout
[zen-stable.git] / arch / mips / pnx833x / common / interrupts.c
blobadc171c8846f29bae0fa55e5a889b7dbc6335086
1 /*
2 * interrupts.c: Interrupt mappings for PNX833X.
3 *
4 * Copyright 2008 NXP Semiconductors
5 * Chris Steel <chris.steel@nxp.com>
6 * Daniel Laird <daniel.j.laird@nxp.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22 #include <linux/kernel.h>
23 #include <linux/irq.h>
24 #include <linux/hardirq.h>
25 #include <linux/interrupt.h>
26 #include <asm/mipsregs.h>
27 #include <asm/irq_cpu.h>
28 #include <irq.h>
29 #include <irq-mapping.h>
30 #include <gpio.h>
31
32 static int mips_cpu_timer_irq;
33
34 static const unsigned int irq_prio[PNX833X_PIC_NUM_IRQ] =
35 {
36 0, /* unused */
37 4, /* PNX833X_PIC_I2C0_INT 1 */
38 4, /* PNX833X_PIC_I2C1_INT 2 */
39 1, /* PNX833X_PIC_UART0_INT 3 */
40 1, /* PNX833X_PIC_UART1_INT 4 */
41 6, /* PNX833X_PIC_TS_IN0_DV_INT 5 */
42 6, /* PNX833X_PIC_TS_IN0_DMA_INT 6 */
43 7, /* PNX833X_PIC_GPIO_INT 7 */
44 4, /* PNX833X_PIC_AUDIO_DEC_INT 8 */
45 5, /* PNX833X_PIC_VIDEO_DEC_INT 9 */
46 4, /* PNX833X_PIC_CONFIG_INT 10 */
47 4, /* PNX833X_PIC_AOI_INT 11 */
48 9, /* PNX833X_PIC_SYNC_INT 12 */
49 9, /* PNX8335_PIC_SATA_INT 13 */
50 4, /* PNX833X_PIC_OSD_INT 14 */
51 9, /* PNX833X_PIC_DISP1_INT 15 */
52 4, /* PNX833X_PIC_DEINTERLACER_INT 16 */
53 9, /* PNX833X_PIC_DISPLAY2_INT 17 */
54 4, /* PNX833X_PIC_VC_INT 18 */
55 4, /* PNX833X_PIC_SC_INT 19 */
56 9, /* PNX833X_PIC_IDE_INT 20 */
57 9, /* PNX833X_PIC_IDE_DMA_INT 21 */
58 6, /* PNX833X_PIC_TS_IN1_DV_INT 22 */
59 6, /* PNX833X_PIC_TS_IN1_DMA_INT 23 */
60 4, /* PNX833X_PIC_SGDX_DMA_INT 24 */
61 4, /* PNX833X_PIC_TS_OUT_INT 25 */
62 4, /* PNX833X_PIC_IR_INT 26 */
63 3, /* PNX833X_PIC_VMSP1_INT 27 */
64 3, /* PNX833X_PIC_VMSP2_INT 28 */
65 4, /* PNX833X_PIC_PIBC_INT 29 */
66 4, /* PNX833X_PIC_TS_IN0_TRD_INT 30 */
67 4, /* PNX833X_PIC_SGDX_TPD_INT 31 */
68 5, /* PNX833X_PIC_USB_INT 32 */
69 4, /* PNX833X_PIC_TS_IN1_TRD_INT 33 */
70 4, /* PNX833X_PIC_CLOCK_INT 34 */
71 4, /* PNX833X_PIC_SGDX_PARSER_INT 35 */
72 4, /* PNX833X_PIC_VMSP_DMA_INT 36 */
73 #if defined(CONFIG_SOC_PNX8335)
74 4, /* PNX8335_PIC_MIU_INT 37 */
75 4, /* PNX8335_PIC_AVCHIP_IRQ_INT 38 */
76 9, /* PNX8335_PIC_SYNC_HD_INT 39 */
77 9, /* PNX8335_PIC_DISP_HD_INT 40 */
78 9, /* PNX8335_PIC_DISP_SCALER_INT 41 */
79 4, /* PNX8335_PIC_OSD_HD1_INT 42 */
80 4, /* PNX8335_PIC_DTL_WRITER_Y_INT 43 */
81 4, /* PNX8335_PIC_DTL_WRITER_C_INT 44 */
82 4, /* PNX8335_PIC_DTL_EMULATOR_Y_IR_INT 45 */
83 4, /* PNX8335_PIC_DTL_EMULATOR_C_IR_INT 46 */
84 4, /* PNX8335_PIC_DENC_TTX_INT 47 */
85 4, /* PNX8335_PIC_MMI_SIF0_INT 48 */
86 4, /* PNX8335_PIC_MMI_SIF1_INT 49 */
87 4, /* PNX8335_PIC_MMI_CDMMU_INT 50 */
88 4, /* PNX8335_PIC_PIBCS_INT 51 */
89 12, /* PNX8335_PIC_ETHERNET_INT 52 */
90 3, /* PNX8335_PIC_VMSP1_0_INT 53 */
91 3, /* PNX8335_PIC_VMSP1_1_INT 54 */
92 4, /* PNX8335_PIC_VMSP1_DMA_INT 55 */
93 4, /* PNX8335_PIC_TDGR_DE_INT 56 */
94 4, /* PNX8335_PIC_IR1_IRQ_INT 57 */
95 #endif
96 };
97
98 static void pnx833x_timer_dispatch(void)
99 {
100 do_IRQ(mips_cpu_timer_irq);
101 }
102
103 static void pic_dispatch(void)
104 {
105 unsigned int irq = PNX833X_REGFIELD(PIC_INT_SRC, INT_SRC);
106
107 if ((irq >= 1) && (irq < (PNX833X_PIC_NUM_IRQ))) {
108 unsigned long priority = PNX833X_PIC_INT_PRIORITY;
109 PNX833X_PIC_INT_PRIORITY = irq_prio[irq];
110
111 if (irq == PNX833X_PIC_GPIO_INT) {
112 unsigned long mask = PNX833X_PIO_INT_STATUS & PNX833X_PIO_INT_ENABLE;
113 int pin;
114 while ((pin = ffs(mask & 0xffff))) {
115 pin -= 1;
116 do_IRQ(PNX833X_GPIO_IRQ_BASE + pin);
117 mask &= ~(1 << pin);
118 }
119 } else {
120 do_IRQ(irq + PNX833X_PIC_IRQ_BASE);
121 }
122
123 PNX833X_PIC_INT_PRIORITY = priority;
124 } else {
125 printk(KERN_ERR "plat_irq_dispatch: unexpected irq %u\n", irq);
126 }
127 }
128
129 asmlinkage void plat_irq_dispatch(void)
130 {
131 unsigned int pending = read_c0_status() & read_c0_cause();
132
133 if (pending & STATUSF_IP4)
134 pic_dispatch();
135 else if (pending & STATUSF_IP7)
136 do_IRQ(PNX833X_TIMER_IRQ);
137 else
138 spurious_interrupt();
139 }
140
141 static inline void pnx833x_hard_enable_pic_irq(unsigned int irq)
142 {
143 /* Currently we do this by setting IRQ priority to 1.
144 If priority support is being implemented, 1 should be repalced
145 by a better value. */
146 PNX833X_PIC_INT_REG(irq) = irq_prio[irq];
147 }
148
149 static inline void pnx833x_hard_disable_pic_irq(unsigned int irq)
150 {
151 /* Disable IRQ by writing setting it's priority to 0 */
152 PNX833X_PIC_INT_REG(irq) = 0;
153 }
154
155 static DEFINE_RAW_SPINLOCK(pnx833x_irq_lock);
156
157 static unsigned int pnx833x_startup_pic_irq(unsigned int irq)
158 {
159 unsigned long flags;
160 unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
161
162 raw_spin_lock_irqsave(&pnx833x_irq_lock, flags);
163 pnx833x_hard_enable_pic_irq(pic_irq);
164 raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
165 return 0;
166 }
167
168 static void pnx833x_enable_pic_irq(struct irq_data *d)
169 {
170 unsigned long flags;
171 unsigned int pic_irq = d->irq - PNX833X_PIC_IRQ_BASE;
172
173 raw_spin_lock_irqsave(&pnx833x_irq_lock, flags);
174 pnx833x_hard_enable_pic_irq(pic_irq);
175 raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
176 }
177
178 static void pnx833x_disable_pic_irq(struct irq_data *d)
179 {
180 unsigned long flags;
181 unsigned int pic_irq = d->irq - PNX833X_PIC_IRQ_BASE;
182
183 raw_spin_lock_irqsave(&pnx833x_irq_lock, flags);
184 pnx833x_hard_disable_pic_irq(pic_irq);
185 raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
186 }
187
188 static DEFINE_RAW_SPINLOCK(pnx833x_gpio_pnx833x_irq_lock);
189
190 static void pnx833x_enable_gpio_irq(struct irq_data *d)
191 {
192 int pin = d->irq - PNX833X_GPIO_IRQ_BASE;
193 unsigned long flags;
194 raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
195 pnx833x_gpio_enable_irq(pin);
196 raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
197 }
198
199 static void pnx833x_disable_gpio_irq(struct irq_data *d)
200 {
201 int pin = d->irq - PNX833X_GPIO_IRQ_BASE;
202 unsigned long flags;
203 raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
204 pnx833x_gpio_disable_irq(pin);
205 raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
206 }
207
208 static int pnx833x_set_type_gpio_irq(struct irq_data *d, unsigned int flow_type)
209 {
210 int pin = d->irq - PNX833X_GPIO_IRQ_BASE;
211 int gpio_mode;
212
213 switch (flow_type) {
214 case IRQ_TYPE_EDGE_RISING:
215 gpio_mode = GPIO_INT_EDGE_RISING;
216 break;
217 case IRQ_TYPE_EDGE_FALLING:
218 gpio_mode = GPIO_INT_EDGE_FALLING;
219 break;
220 case IRQ_TYPE_EDGE_BOTH:
221 gpio_mode = GPIO_INT_EDGE_BOTH;
222 break;
223 case IRQ_TYPE_LEVEL_HIGH:
224 gpio_mode = GPIO_INT_LEVEL_HIGH;
225 break;
226 case IRQ_TYPE_LEVEL_LOW:
227 gpio_mode = GPIO_INT_LEVEL_LOW;
228 break;
229 default:
230 gpio_mode = GPIO_INT_NONE;
231 break;
232 }
233
234 pnx833x_gpio_setup_irq(gpio_mode, pin);
235
236 return 0;
237 }
238
239 static struct irq_chip pnx833x_pic_irq_type = {
240 .name = "PNX-PIC",
241 .irq_enable = pnx833x_enable_pic_irq,
242 .irq_disable = pnx833x_disable_pic_irq,
243 };
244
245 static struct irq_chip pnx833x_gpio_irq_type = {
246 .name = "PNX-GPIO",
247 .irq_enable = pnx833x_enable_gpio_irq,
248 .irq_disable = pnx833x_disable_gpio_irq,
249 .irq_set_type = pnx833x_set_type_gpio_irq,
250 };
251
252 void __init arch_init_irq(void)
253 {
254 unsigned int irq;
255
256 /* setup standard internal cpu irqs */
257 mips_cpu_irq_init();
258
259 /* Set IRQ information in irq_desc */
260 for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ); irq++) {
261 pnx833x_hard_disable_pic_irq(irq);
262 irq_set_chip_and_handler(irq, &pnx833x_pic_irq_type,
263 handle_simple_irq);
264 }
265
266 for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + PNX833X_GPIO_NUM_IRQ); irq++)
267 irq_set_chip_and_handler(irq, &pnx833x_gpio_irq_type,
268 handle_simple_irq);
269
270 /* Set PIC priority limiter register to 0 */
271 PNX833X_PIC_INT_PRIORITY = 0;
272
273 /* Setup GPIO IRQ dispatching */
274 pnx833x_startup_pic_irq(PNX833X_PIC_GPIO_INT);
275
276 /* Enable PIC IRQs (HWIRQ2) */
277 if (cpu_has_vint)
278 set_vi_handler(4, pic_dispatch);
279
280 write_c0_status(read_c0_status() | IE_IRQ2);
281 }
282
283 unsigned int __cpuinit get_c0_compare_int(void)
284 {
285 if (cpu_has_vint)
286 set_vi_handler(cp0_compare_irq, pnx833x_timer_dispatch);
287
288 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
289 return mips_cpu_timer_irq;
290 }
291
292 void __init plat_time_init(void)
293 {
294 /* calculate mips_hpt_frequency based on PNX833X_CLOCK_CPUCP_CTL reg */
295
296 extern unsigned long mips_hpt_frequency;
297 unsigned long reg = PNX833X_CLOCK_CPUCP_CTL;
298
299 if (!(PNX833X_BIT(reg, CLOCK_CPUCP_CTL, EXIT_RESET))) {
300 /* Functional clock is disabled so use crystal frequency */
301 mips_hpt_frequency = 25;
302 } else {
303 #if defined(CONFIG_SOC_PNX8335)
304 /* Functional clock is enabled, so get clock multiplier */
305 mips_hpt_frequency = 90 + (10 * PNX8335_REGFIELD(CLOCK_PLL_CPU_CTL, FREQ));
306 #else
307 static const unsigned long int freq[4] = {240, 160, 120, 80};
308 mips_hpt_frequency = freq[PNX833X_FIELD(reg, CLOCK_CPUCP_CTL, DIV_CLOCK)];
309 #endif
310 }
311
312 printk(KERN_INFO "CPU clock is %ld MHz\n", mips_hpt_frequency);
313
314 mips_hpt_frequency *= 500000;
315 }