arch/powerpc/include/asm/io.h

   1 #ifndef _ASM_POWERPC_IO_H
   2 #define _ASM_POWERPC_IO_H
   3 #ifdef __KERNEL__
   4
   5 #define ARCH_HAS_IOREMAP_WC
   6
   7 /*
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version
  11  * 2 of the License, or (at your option) any later version.
  12  */
  13
  14 /* Check of existence of legacy devices */
  15 extern int check_legacy_ioport(unsigned long base_port);
  16 #define I8042_DATA_REG  0x60
  17 #define FDC_BASE        0x3f0
  18 /* only relevant for PReP */
  19 #define _PIDXR          0x279
  20 #define _PNPWRP         0xa79
  21 #define PNPBIOS_BASE    0xf000
  22
  23 #include <linux/device.h>
  24 #include <linux/io.h>
  25
  26 #include <linux/compiler.h>
  27 #include <asm/page.h>
  28 #include <asm/byteorder.h>
  29 #include <asm/synch.h>
  30 #include <asm/delay.h>
  31 #include <asm/mmu.h>
  32
  33 #include <asm-generic/iomap.h>
  34
  35 #ifdef CONFIG_PPC64
  36 #include <asm/paca.h>
  37 #endif
  38
  39 #define SIO_CONFIG_RA   0x398
  40 #define SIO_CONFIG_RD   0x399
  41
  42 #define SLOW_DOWN_IO
  43
  44 /* 32 bits uses slightly different variables for the various IO
  45  * bases. Most of this file only uses _IO_BASE though which we
  46  * define properly based on the platform
  47  */
  48 #ifndef CONFIG_PCI
  49 #define _IO_BASE        0
  50 #define _ISA_MEM_BASE   0
  51 #define PCI_DRAM_OFFSET 0
  52 #elif defined(CONFIG_PPC32)
  53 #define _IO_BASE        isa_io_base
  54 #define _ISA_MEM_BASE   isa_mem_base
  55 #define PCI_DRAM_OFFSET pci_dram_offset
  56 #else
  57 #define _IO_BASE        pci_io_base
  58 #define _ISA_MEM_BASE   isa_mem_base
  59 #define PCI_DRAM_OFFSET 0
  60 #endif
  61
  62 extern unsigned long isa_io_base;
  63 extern unsigned long pci_io_base;
  64 extern unsigned long pci_dram_offset;
  65
  66 extern resource_size_t isa_mem_base;
  67
  68 #if defined(CONFIG_PPC32) && defined(CONFIG_PPC_INDIRECT_IO)
  69 #error CONFIG_PPC_INDIRECT_IO is not yet supported on 32 bits
  70 #endif
  71
  72 /*
  73  *
  74  * Low level MMIO accessors
  75  *
  76  * This provides the non-bus specific accessors to MMIO. Those are PowerPC
  77  * specific and thus shouldn't be used in generic code. The accessors
  78  * provided here are:
  79  *
  80  *      in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
  81  *      out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
  82  *      _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
  83  *
  84  * Those operate directly on a kernel virtual address. Note that the prototype
  85  * for the out_* accessors has the arguments in opposite order from the usual
  86  * linux PCI accessors. Unlike those, they take the address first and the value
  87  * next.
  88  *
  89  * Note: I might drop the _ns suffix on the stream operations soon as it is
  90  * simply normal for stream operations to not swap in the first place.
  91  *
  92  */
  93
  94 #ifdef CONFIG_PPC64
  95 #define IO_SET_SYNC_FLAG()      do { local_paca->io_sync = 1; } while(0)
  96 #else
  97 #define IO_SET_SYNC_FLAG()
  98 #endif
  99
 100 /* gcc 4.0 and older doesn't have 'Z' constraint */
 101 #if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ == 0)
 102 #define DEF_MMIO_IN_LE(name, size, insn)                                \
 103 static inline u##size name(const volatile u##size __iomem *addr)        \
 104 {                                                                       \
 105         u##size ret;                                                    \
 106         __asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync"    \
 107                 : "=r" (ret) : "r" (addr), "m" (*addr) : "memory");     \
 108         return ret;                                                     \
 109 }
 110
 111 #define DEF_MMIO_OUT_LE(name, size, insn)                               \
 112 static inline void name(volatile u##size __iomem *addr, u##size val)    \
 113 {                                                                       \
 114         __asm__ __volatile__("sync;"#insn" %1,0,%2"                     \
 115                 : "=m" (*addr) : "r" (val), "r" (addr) : "memory");     \
 116         IO_SET_SYNC_FLAG();                                             \
 117 }
 118 #else /* newer gcc */
 119 #define DEF_MMIO_IN_LE(name, size, insn)                                \
 120 static inline u##size name(const volatile u##size __iomem *addr)        \
 121 {                                                                       \
 122         u##size ret;                                                    \
 123         __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync"     \
 124                 : "=r" (ret) : "Z" (*addr) : "memory");                 \
 125         return ret;                                                     \
 126 }
 127
 128 #define DEF_MMIO_OUT_LE(name, size, insn)                               \
 129 static inline void name(volatile u##size __iomem *addr, u##size val)    \
 130 {                                                                       \
 131         __asm__ __volatile__("sync;"#insn" %1,%y0"                      \
 132                 : "=Z" (*addr) : "r" (val) : "memory");                 \
 133         IO_SET_SYNC_FLAG();                                             \
 134 }
 135 #endif
 136
 137 #define DEF_MMIO_IN_BE(name, size, insn)                                \
 138 static inline u##size name(const volatile u##size __iomem *addr)        \
 139 {                                                                       \
 140         u##size ret;                                                    \
 141         __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
 142                 : "=r" (ret) : "m" (*addr) : "memory");                 \
 143         return ret;                                                     \
 144 }
 145
 146 #define DEF_MMIO_OUT_BE(name, size, insn)                               \
 147 static inline void name(volatile u##size __iomem *addr, u##size val)    \
 148 {                                                                       \
 149         __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0"                 \
 150                 : "=m" (*addr) : "r" (val) : "memory");                 \
 151         IO_SET_SYNC_FLAG();                                             \
 152 }
 153
 154
 155 DEF_MMIO_IN_BE(in_8,     8, lbz);
 156 DEF_MMIO_IN_BE(in_be16, 16, lhz);
 157 DEF_MMIO_IN_BE(in_be32, 32, lwz);
 158 DEF_MMIO_IN_LE(in_le16, 16, lhbrx);
 159 DEF_MMIO_IN_LE(in_le32, 32, lwbrx);
 160
 161 DEF_MMIO_OUT_BE(out_8,     8, stb);
 162 DEF_MMIO_OUT_BE(out_be16, 16, sth);
 163 DEF_MMIO_OUT_BE(out_be32, 32, stw);
 164 DEF_MMIO_OUT_LE(out_le16, 16, sthbrx);
 165 DEF_MMIO_OUT_LE(out_le32, 32, stwbrx);
 166
 167 #ifdef __powerpc64__
 168 DEF_MMIO_OUT_BE(out_be64, 64, std);
 169 DEF_MMIO_IN_BE(in_be64, 64, ld);
 170
 171 /* There is no asm instructions for 64 bits reverse loads and stores */
 172 static inline u64 in_le64(const volatile u64 __iomem *addr)
 173 {
 174         return swab64(in_be64(addr));
 175 }
 176
 177 static inline void out_le64(volatile u64 __iomem *addr, u64 val)
 178 {
 179         out_be64(addr, swab64(val));
 180 }
 181 #endif /* __powerpc64__ */
 182
 183 /*
 184  * Low level IO stream instructions are defined out of line for now
 185  */
 186 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
 187 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
 188 extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
 189 extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
 190 extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
 191 extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
 192
 193 /* The _ns naming is historical and will be removed. For now, just #define
 194  * the non _ns equivalent names
 195  */
 196 #define _insw   _insw_ns
 197 #define _insl   _insl_ns
 198 #define _outsw  _outsw_ns
 199 #define _outsl  _outsl_ns
 200
 201
 202 /*
 203  * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
 204  */
 205
 206 extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
 207 extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
 208                            unsigned long n);
 209 extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
 210                          unsigned long n);
 211
 212 /*
 213  *
 214  * PCI and standard ISA accessors
 215  *
 216  * Those are globally defined linux accessors for devices on PCI or ISA
 217  * busses. They follow the Linux defined semantics. The current implementation
 218  * for PowerPC is as close as possible to the x86 version of these, and thus
 219  * provides fairly heavy weight barriers for the non-raw versions
 220  *
 221  * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_IO
 222  * allowing the platform to provide its own implementation of some or all
 223  * of the accessors.
 224  */
 225
 226 /*
 227  * Include the EEH definitions when EEH is enabled only so they don't get
 228  * in the way when building for 32 bits
 229  */
 230 #ifdef CONFIG_EEH
 231 #include <asm/eeh.h>
 232 #endif
 233
 234 /* Shortcut to the MMIO argument pointer */
 235 #define PCI_IO_ADDR     volatile void __iomem *
 236
 237 /* Indirect IO address tokens:
 238  *
 239  * When CONFIG_PPC_INDIRECT_IO is set, the platform can provide hooks
 240  * on all IOs. (Note that this is all 64 bits only for now)
 241  *
 242  * To help platforms who may need to differenciate MMIO addresses in
 243  * their hooks, a bitfield is reserved for use by the platform near the
 244  * top of MMIO addresses (not PIO, those have to cope the hard way).
 245  *
 246  * This bit field is 12 bits and is at the top of the IO virtual
 247  * addresses PCI_IO_INDIRECT_TOKEN_MASK.
 248  *
 249  * The kernel virtual space is thus:
 250  *
 251  *  0xD000000000000000          : vmalloc
 252  *  0xD000080000000000          : PCI PHB IO space
 253  *  0xD000080080000000          : ioremap
 254  *  0xD0000fffffffffff          : end of ioremap region
 255  *
 256  * Since the top 4 bits are reserved as the region ID, we use thus
 257  * the next 12 bits and keep 4 bits available for the future if the
 258  * virtual address space is ever to be extended.
 259  *
 260  * The direct IO mapping operations will then mask off those bits
 261  * before doing the actual access, though that only happen when
 262  * CONFIG_PPC_INDIRECT_IO is set, thus be careful when you use that
 263  * mechanism
 264  */
 265
 266 #ifdef CONFIG_PPC_INDIRECT_IO
 267 #define PCI_IO_IND_TOKEN_MASK   0x0fff000000000000ul
 268 #define PCI_IO_IND_TOKEN_SHIFT  48
 269 #define PCI_FIX_ADDR(addr)                                              \
 270         ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
 271 #define PCI_GET_ADDR_TOKEN(addr)                                        \
 272         (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >>             \
 273                 PCI_IO_IND_TOKEN_SHIFT)
 274 #define PCI_SET_ADDR_TOKEN(addr, token)                                 \
 275 do {                                                                    \
 276         unsigned long __a = (unsigned long)(addr);                      \
 277         __a &= ~PCI_IO_IND_TOKEN_MASK;                                  \
 278         __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT;      \
 279         (addr) = (void __iomem *)__a;                                   \
 280 } while(0)
 281 #else
 282 #define PCI_FIX_ADDR(addr) (addr)
 283 #endif
 284
 285
 286 /*
 287  * Non ordered and non-swapping "raw" accessors
 288  */
 289
 290 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
 291 {
 292         return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
 293 }
 294 static inline unsigned short __raw_readw(const volatile void __iomem *addr)
 295 {
 296         return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
 297 }
 298 static inline unsigned int __raw_readl(const volatile void __iomem *addr)
 299 {
 300         return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
 301 }
 302 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
 303 {
 304         *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
 305 }
 306 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
 307 {
 308         *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
 309 }
 310 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
 311 {
 312         *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
 313 }
 314
 315 #ifdef __powerpc64__
 316 static inline unsigned long __raw_readq(const volatile void __iomem *addr)
 317 {
 318         return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
 319 }
 320 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
 321 {
 322         *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
 323 }
 324 #endif /* __powerpc64__ */
 325
 326 /*
 327  *
 328  * PCI PIO and MMIO accessors.
 329  *
 330  *
 331  * On 32 bits, PIO operations have a recovery mechanism in case they trigger
 332  * machine checks (which they occasionally do when probing non existing
 333  * IO ports on some platforms, like PowerMac and 8xx).
 334  * I always found it to be of dubious reliability and I am tempted to get
 335  * rid of it one of these days. So if you think it's important to keep it,
 336  * please voice up asap. We never had it for 64 bits and I do not intend
 337  * to port it over
 338  */
 339
 340 #ifdef CONFIG_PPC32
 341
 342 #define __do_in_asm(name, op)                           \
 343 static inline unsigned int name(unsigned int port)      \
 344 {                                                       \
 345         unsigned int x;                                 \
 346         __asm__ __volatile__(                           \
 347                 "sync\n"                                \
 348                 "0:"    op "    %0,0,%1\n"              \
 349                 "1:     twi     0,%0,0\n"               \
 350                 "2:     isync\n"                        \
 351                 "3:     nop\n"                          \
 352                 "4:\n"                                  \
 353                 ".section .fixup,\"ax\"\n"              \
 354                 "5:     li      %0,-1\n"                \
 355                 "       b       4b\n"                   \
 356                 ".previous\n"                           \
 357                 ".section __ex_table,\"a\"\n"           \
 358                 "       .align  2\n"                    \
 359                 "       .long   0b,5b\n"                \
 360                 "       .long   1b,5b\n"                \
 361                 "       .long   2b,5b\n"                \
 362                 "       .long   3b,5b\n"                \
 363                 ".previous"                             \
 364                 : "=&r" (x)                             \
 365                 : "r" (port + _IO_BASE)                 \
 366                 : "memory");                            \
 367         return x;                                       \
 368 }
 369
 370 #define __do_out_asm(name, op)                          \
 371 static inline void name(unsigned int val, unsigned int port) \
 372 {                                                       \
 373         __asm__ __volatile__(                           \
 374                 "sync\n"                                \
 375                 "0:" op " %0,0,%1\n"                    \
 376                 "1:     sync\n"                         \
 377                 "2:\n"                                  \
 378                 ".section __ex_table,\"a\"\n"           \
 379                 "       .align  2\n"                    \
 380                 "       .long   0b,2b\n"                \
 381                 "       .long   1b,2b\n"                \
 382                 ".previous"                             \
 383                 : : "r" (val), "r" (port + _IO_BASE)    \
 384                 : "memory");                            \
 385 }
 386
 387 __do_in_asm(_rec_inb, "lbzx")
 388 __do_in_asm(_rec_inw, "lhbrx")
 389 __do_in_asm(_rec_inl, "lwbrx")
 390 __do_out_asm(_rec_outb, "stbx")
 391 __do_out_asm(_rec_outw, "sthbrx")
 392 __do_out_asm(_rec_outl, "stwbrx")
 393
 394 #endif /* CONFIG_PPC32 */
 395
 396 /* The "__do_*" operations below provide the actual "base" implementation
 397  * for each of the defined accessors. Some of them use the out_* functions
 398  * directly, some of them still use EEH, though we might change that in the
 399  * future. Those macros below provide the necessary argument swapping and
 400  * handling of the IO base for PIO.
 401  *
 402  * They are themselves used by the macros that define the actual accessors
 403  * and can be used by the hooks if any.
 404  *
 405  * Note that PIO operations are always defined in terms of their corresonding
 406  * MMIO operations. That allows platforms like iSeries who want to modify the
 407  * behaviour of both to only hook on the MMIO version and get both. It's also
 408  * possible to hook directly at the toplevel PIO operation if they have to
 409  * be handled differently
 410  */
 411 #define __do_writeb(val, addr)  out_8(PCI_FIX_ADDR(addr), val)
 412 #define __do_writew(val, addr)  out_le16(PCI_FIX_ADDR(addr), val)
 413 #define __do_writel(val, addr)  out_le32(PCI_FIX_ADDR(addr), val)
 414 #define __do_writeq(val, addr)  out_le64(PCI_FIX_ADDR(addr), val)
 415 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
 416 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
 417 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
 418
 419 #ifdef CONFIG_EEH
 420 #define __do_readb(addr)        eeh_readb(PCI_FIX_ADDR(addr))
 421 #define __do_readw(addr)        eeh_readw(PCI_FIX_ADDR(addr))
 422 #define __do_readl(addr)        eeh_readl(PCI_FIX_ADDR(addr))
 423 #define __do_readq(addr)        eeh_readq(PCI_FIX_ADDR(addr))
 424 #define __do_readw_be(addr)     eeh_readw_be(PCI_FIX_ADDR(addr))
 425 #define __do_readl_be(addr)     eeh_readl_be(PCI_FIX_ADDR(addr))
 426 #define __do_readq_be(addr)     eeh_readq_be(PCI_FIX_ADDR(addr))
 427 #else /* CONFIG_EEH */
 428 #define __do_readb(addr)        in_8(PCI_FIX_ADDR(addr))
 429 #define __do_readw(addr)        in_le16(PCI_FIX_ADDR(addr))
 430 #define __do_readl(addr)        in_le32(PCI_FIX_ADDR(addr))
 431 #define __do_readq(addr)        in_le64(PCI_FIX_ADDR(addr))
 432 #define __do_readw_be(addr)     in_be16(PCI_FIX_ADDR(addr))
 433 #define __do_readl_be(addr)     in_be32(PCI_FIX_ADDR(addr))
 434 #define __do_readq_be(addr)     in_be64(PCI_FIX_ADDR(addr))
 435 #endif /* !defined(CONFIG_EEH) */
 436
 437 #ifdef CONFIG_PPC32
 438 #define __do_outb(val, port)    _rec_outb(val, port)
 439 #define __do_outw(val, port)    _rec_outw(val, port)
 440 #define __do_outl(val, port)    _rec_outl(val, port)
 441 #define __do_inb(port)          _rec_inb(port)
 442 #define __do_inw(port)          _rec_inw(port)
 443 #define __do_inl(port)          _rec_inl(port)
 444 #else /* CONFIG_PPC32 */
 445 #define __do_outb(val, port)    writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
 446 #define __do_outw(val, port)    writew(val,(PCI_IO_ADDR)_IO_BASE+port);
 447 #define __do_outl(val, port)    writel(val,(PCI_IO_ADDR)_IO_BASE+port);
 448 #define __do_inb(port)          readb((PCI_IO_ADDR)_IO_BASE + port);
 449 #define __do_inw(port)          readw((PCI_IO_ADDR)_IO_BASE + port);
 450 #define __do_inl(port)          readl((PCI_IO_ADDR)_IO_BASE + port);
 451 #endif /* !CONFIG_PPC32 */
 452
 453 #ifdef CONFIG_EEH
 454 #define __do_readsb(a, b, n)    eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
 455 #define __do_readsw(a, b, n)    eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
 456 #define __do_readsl(a, b, n)    eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
 457 #else /* CONFIG_EEH */
 458 #define __do_readsb(a, b, n)    _insb(PCI_FIX_ADDR(a), (b), (n))
 459 #define __do_readsw(a, b, n)    _insw(PCI_FIX_ADDR(a), (b), (n))
 460 #define __do_readsl(a, b, n)    _insl(PCI_FIX_ADDR(a), (b), (n))
 461 #endif /* !CONFIG_EEH */
 462 #define __do_writesb(a, b, n)   _outsb(PCI_FIX_ADDR(a),(b),(n))
 463 #define __do_writesw(a, b, n)   _outsw(PCI_FIX_ADDR(a),(b),(n))
 464 #define __do_writesl(a, b, n)   _outsl(PCI_FIX_ADDR(a),(b),(n))
 465
 466 #define __do_insb(p, b, n)      readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
 467 #define __do_insw(p, b, n)      readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
 468 #define __do_insl(p, b, n)      readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
 469 #define __do_outsb(p, b, n)     writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
 470 #define __do_outsw(p, b, n)     writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
 471 #define __do_outsl(p, b, n)     writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
 472
 473 #define __do_memset_io(addr, c, n)      \
 474                                 _memset_io(PCI_FIX_ADDR(addr), c, n)
 475 #define __do_memcpy_toio(dst, src, n)   \
 476                                 _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
 477
 478 #ifdef CONFIG_EEH
 479 #define __do_memcpy_fromio(dst, src, n) \
 480                                 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
 481 #else /* CONFIG_EEH */
 482 #define __do_memcpy_fromio(dst, src, n) \
 483                                 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
 484 #endif /* !CONFIG_EEH */
 485
 486 #ifdef CONFIG_PPC_INDIRECT_PIO
 487 #define DEF_PCI_HOOK_pio(x)     x
 488 #else
 489 #define DEF_PCI_HOOK_pio(x)     NULL
 490 #endif
 491
 492 #ifdef CONFIG_PPC_INDIRECT_MMIO
 493 #define DEF_PCI_HOOK_mem(x)     x
 494 #else
 495 #define DEF_PCI_HOOK_mem(x)     NULL
 496 #endif
 497
 498 /* Structure containing all the hooks */
 499 extern struct ppc_pci_io {
 500
 501 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa)    ret (*name) at;
 502 #define DEF_PCI_AC_NORET(name, at, al, space, aa)       void (*name) at;
 503
 504 #include <asm/io-defs.h>
 505
 506 #undef DEF_PCI_AC_RET
 507 #undef DEF_PCI_AC_NORET
 508
 509 } ppc_pci_io;
 510
 511 /* The inline wrappers */
 512 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa)            \
 513 static inline ret name at                                       \
 514 {                                                               \
 515         if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL)      \
 516                 return ppc_pci_io.name al;                      \
 517         return __do_##name al;                                  \
 518 }
 519
 520 #define DEF_PCI_AC_NORET(name, at, al, space, aa)               \
 521 static inline void name at                                      \
 522 {                                                               \
 523         if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL)              \
 524                 ppc_pci_io.name al;                             \
 525         else                                                    \
 526                 __do_##name al;                                 \
 527 }
 528
 529 #include <asm/io-defs.h>
 530
 531 #undef DEF_PCI_AC_RET
 532 #undef DEF_PCI_AC_NORET
 533
 534 /* Some drivers check for the presence of readq & writeq with
 535  * a #ifdef, so we make them happy here.
 536  */
 537 #ifdef __powerpc64__
 538 #define readq   readq
 539 #define writeq  writeq
 540 #endif
 541
 542 /*
 543  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 544  * access
 545  */
 546 #define xlate_dev_mem_ptr(p)    __va(p)
 547
 548 /*
 549  * Convert a virtual cached pointer to an uncached pointer
 550  */
 551 #define xlate_dev_kmem_ptr(p)   p
 552
 553 /*
 554  * We don't do relaxed operations yet, at least not with this semantic
 555  */
 556 #define readb_relaxed(addr) readb(addr)
 557 #define readw_relaxed(addr) readw(addr)
 558 #define readl_relaxed(addr) readl(addr)
 559 #define readq_relaxed(addr) readq(addr)
 560
 561 #ifdef CONFIG_PPC32
 562 #define mmiowb()
 563 #else
 564 /*
 565  * Enforce synchronisation of stores vs. spin_unlock
 566  * (this does it explicitly, though our implementation of spin_unlock
 567  * does it implicitely too)
 568  */
 569 static inline void mmiowb(void)
 570 {
 571         unsigned long tmp;
 572
 573         __asm__ __volatile__("sync; li %0,0; stb %0,%1(13)"
 574         : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync))
 575         : "memory");
 576 }
 577 #endif /* !CONFIG_PPC32 */
 578
 579 static inline void iosync(void)
 580 {
 581         __asm__ __volatile__ ("sync" : : : "memory");
 582 }
 583
 584 /* Enforce in-order execution of data I/O.
 585  * No distinction between read/write on PPC; use eieio for all three.
 586  * Those are fairly week though. They don't provide a barrier between
 587  * MMIO and cacheable storage nor do they provide a barrier vs. locks,
 588  * they only provide barriers between 2 __raw MMIO operations and
 589  * possibly break write combining.
 590  */
 591 #define iobarrier_rw() eieio()
 592 #define iobarrier_r()  eieio()
 593 #define iobarrier_w()  eieio()
 594
 595
 596 /*
 597  * output pause versions need a delay at least for the
 598  * w83c105 ide controller in a p610.
 599  */
 600 #define inb_p(port)             inb(port)
 601 #define outb_p(val, port)       (udelay(1), outb((val), (port)))
 602 #define inw_p(port)             inw(port)
 603 #define outw_p(val, port)       (udelay(1), outw((val), (port)))
 604 #define inl_p(port)             inl(port)
 605 #define outl_p(val, port)       (udelay(1), outl((val), (port)))
 606
 607
 608 #define IO_SPACE_LIMIT ~(0UL)
 609
 610
 611 /**
 612  * ioremap     -   map bus memory into CPU space
 613  * @address:   bus address of the memory
 614  * @size:      size of the resource to map
 615  *
 616  * ioremap performs a platform specific sequence of operations to
 617  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 618  * writew/writel functions and the other mmio helpers. The returned
 619  * address is not guaranteed to be usable directly as a virtual
 620  * address.
 621  *
 622  * We provide a few variations of it:
 623  *
 624  * * ioremap is the standard one and provides non-cacheable guarded mappings
 625  *   and can be hooked by the platform via ppc_md
 626  *
 627  * * ioremap_prot allows to specify the page flags as an argument and can
 628  *   also be hooked by the platform via ppc_md.
 629  *
 630  * * ioremap_nocache is identical to ioremap
 631  *
 632  * * ioremap_wc enables write combining
 633  *
 634  * * iounmap undoes such a mapping and can be hooked
 635  *
 636  * * __ioremap_at (and the pending __iounmap_at) are low level functions to
 637  *   create hand-made mappings for use only by the PCI code and cannot
 638  *   currently be hooked. Must be page aligned.
 639  *
 640  * * __ioremap is the low level implementation used by ioremap and
 641  *   ioremap_prot and cannot be hooked (but can be used by a hook on one
 642  *   of the previous ones)
 643  *
 644  * * __ioremap_caller is the same as above but takes an explicit caller
 645  *   reference rather than using __builtin_return_address(0)
 646  *
 647  * * __iounmap, is the low level implementation used by iounmap and cannot
 648  *   be hooked (but can be used by a hook on iounmap)
 649  *
 650  */
 651 extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
 652 extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size,
 653                                   unsigned long flags);
 654 extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
 655 #define ioremap_nocache(addr, size)     ioremap((addr), (size))
 656
 657 extern void iounmap(volatile void __iomem *addr);
 658
 659 extern void __iomem *__ioremap(phys_addr_t, unsigned long size,
 660                                unsigned long flags);
 661 extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
 662                                       unsigned long flags, void *caller);
 663
 664 extern void __iounmap(volatile void __iomem *addr);
 665
 666 extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea,
 667                                    unsigned long size, unsigned long flags);
 668 extern void __iounmap_at(void *ea, unsigned long size);
 669
 670 /*
 671  * When CONFIG_PPC_INDIRECT_IO is set, we use the generic iomap implementation
 672  * which needs some additional definitions here. They basically allow PIO
 673  * space overall to be 1GB. This will work as long as we never try to use
 674  * iomap to map MMIO below 1GB which should be fine on ppc64
 675  */
 676 #define HAVE_ARCH_PIO_SIZE              1
 677 #define PIO_OFFSET                      0x00000000UL
 678 #define PIO_MASK                        (FULL_IO_SIZE - 1)
 679 #define PIO_RESERVED                    (FULL_IO_SIZE)
 680
 681 #define mmio_read16be(addr)             readw_be(addr)
 682 #define mmio_read32be(addr)             readl_be(addr)
 683 #define mmio_write16be(val, addr)       writew_be(val, addr)
 684 #define mmio_write32be(val, addr)       writel_be(val, addr)
 685 #define mmio_insb(addr, dst, count)     readsb(addr, dst, count)
 686 #define mmio_insw(addr, dst, count)     readsw(addr, dst, count)
 687 #define mmio_insl(addr, dst, count)     readsl(addr, dst, count)
 688 #define mmio_outsb(addr, src, count)    writesb(addr, src, count)
 689 #define mmio_outsw(addr, src, count)    writesw(addr, src, count)
 690 #define mmio_outsl(addr, src, count)    writesl(addr, src, count)
 691
 692 /**
 693  *      virt_to_phys    -       map virtual addresses to physical
 694  *      @address: address to remap
 695  *
 696  *      The returned physical address is the physical (CPU) mapping for
 697  *      the memory address given. It is only valid to use this function on
 698  *      addresses directly mapped or allocated via kmalloc.
 699  *
 700  *      This function does not give bus mappings for DMA transfers. In
 701  *      almost all conceivable cases a device driver should not be using
 702  *      this function
 703  */
 704 static inline unsigned long virt_to_phys(volatile void * address)
 705 {
 706         return __pa((unsigned long)address);
 707 }
 708
 709 /**
 710  *      phys_to_virt    -       map physical address to virtual
 711  *      @address: address to remap
 712  *
 713  *      The returned virtual address is a current CPU mapping for
 714  *      the memory address given. It is only valid to use this function on
 715  *      addresses that have a kernel mapping
 716  *
 717  *      This function does not handle bus mappings for DMA transfers. In
 718  *      almost all conceivable cases a device driver should not be using
 719  *      this function
 720  */
 721 static inline void * phys_to_virt(unsigned long address)
 722 {
 723         return (void *)__va(address);
 724 }
 725
 726 /*
 727  * Change "struct page" to physical address.
 728  */
 729 #define page_to_phys(page)      ((phys_addr_t)page_to_pfn(page) << PAGE_SHIFT)
 730
 731 /*
 732  * 32 bits still uses virt_to_bus() for it's implementation of DMA
 733  * mappings se we have to keep it defined here. We also have some old
 734  * drivers (shame shame shame) that use bus_to_virt() and haven't been
 735  * fixed yet so I need to define it here.
 736  */
 737 #ifdef CONFIG_PPC32
 738
 739 static inline unsigned long virt_to_bus(volatile void * address)
 740 {
 741         if (address == NULL)
 742                 return 0;
 743         return __pa(address) + PCI_DRAM_OFFSET;
 744 }
 745
 746 static inline void * bus_to_virt(unsigned long address)
 747 {
 748         if (address == 0)
 749                 return NULL;
 750         return __va(address - PCI_DRAM_OFFSET);
 751 }
 752
 753 #define page_to_bus(page)       (page_to_phys(page) + PCI_DRAM_OFFSET)
 754
 755 #endif /* CONFIG_PPC32 */
 756
 757 /* access ports */
 758 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) |  (_v))
 759 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
 760
 761 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) |  (_v))
 762 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
 763
 764 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) |  (_v))
 765 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
 766
 767 /* Clear and set bits in one shot.  These macros can be used to clear and
 768  * set multiple bits in a register using a single read-modify-write.  These
 769  * macros can also be used to set a multiple-bit bit pattern using a mask,
 770  * by specifying the mask in the 'clear' parameter and the new bit pattern
 771  * in the 'set' parameter.
 772  */
 773
 774 #define clrsetbits(type, addr, clear, set) \
 775         out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
 776
 777 #ifdef __powerpc64__
 778 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
 779 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
 780 #endif
 781
 782 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
 783 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
 784
 785 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
 786 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
 787
 788 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
 789
 790 void __iomem *devm_ioremap_prot(struct device *dev, resource_size_t offset,
 791                                 size_t size, unsigned long flags);
 792
 793 #endif /* __KERNEL__ */
 794
 795 #endif /* _ASM_POWERPC_IO_H */