| blob | e980faae4225098d37e087d502bfb70166d9ea29 |
1 /*
2 * Copyright 2009 Freescale Semicondutor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * provides masks and opcode images for use by code generation, emulation
10 * and for instructions that older assemblers might not know about
11 */
12 #ifndef _ASM_POWERPC_PPC_OPCODE_H
13 #define _ASM_POWERPC_PPC_OPCODE_H
15 #include <linux/stringify.h>
16 #include <asm/asm-compat.h>
18 /* sorted alphabetically */
19 #define PPC_INST_DCBA 0x7c0005ec
20 #define PPC_INST_DCBA_MASK 0xfc0007fe
21 #define PPC_INST_DCBAL 0x7c2005ec
22 #define PPC_INST_DCBZL 0x7c2007ec
23 #define PPC_INST_ISEL 0x7c00001e
24 #define PPC_INST_ISEL_MASK 0xfc00003e
25 #define PPC_INST_LDARX 0x7c0000a8
26 #define PPC_INST_LSWI 0x7c0004aa
27 #define PPC_INST_LSWX 0x7c00042a
28 #define PPC_INST_LWARX 0x7c000028
29 #define PPC_INST_LWSYNC 0x7c2004ac
30 #define PPC_INST_LXVD2X 0x7c000698
31 #define PPC_INST_MCRXR 0x7c000400
32 #define PPC_INST_MCRXR_MASK 0xfc0007fe
33 #define PPC_INST_MFSPR_PVR 0x7c1f42a6
34 #define PPC_INST_MFSPR_PVR_MASK 0xfc1fffff
35 #define PPC_INST_MSGSND 0x7c00019c
36 #define PPC_INST_NOP 0x60000000
37 #define PPC_INST_POPCNTB 0x7c0000f4
38 #define PPC_INST_POPCNTB_MASK 0xfc0007fe
39 #define PPC_INST_POPCNTD 0x7c0003f4
40 #define PPC_INST_POPCNTW 0x7c0002f4
41 #define PPC_INST_RFCI 0x4c000066
42 #define PPC_INST_RFDI 0x4c00004e
43 #define PPC_INST_RFMCI 0x4c00004c
44 #define PPC_INST_MFSPR_DSCR 0x7c1102a6
45 #define PPC_INST_MFSPR_DSCR_MASK 0xfc1fffff
46 #define PPC_INST_MTSPR_DSCR 0x7c1103a6
47 #define PPC_INST_MTSPR_DSCR_MASK 0xfc1fffff
49 #define PPC_INST_STRING 0x7c00042a
50 #define PPC_INST_STRING_MASK 0xfc0007fe
51 #define PPC_INST_STRING_GEN_MASK 0xfc00067e
53 #define PPC_INST_STSWI 0x7c0005aa
54 #define PPC_INST_STSWX 0x7c00052a
55 #define PPC_INST_STXVD2X 0x7c000798
56 #define PPC_INST_TLBIE 0x7c000264
57 #define PPC_INST_TLBILX 0x7c000024
58 #define PPC_INST_WAIT 0x7c00007c
59 #define PPC_INST_TLBIVAX 0x7c000624
60 #define PPC_INST_TLBSRX_DOT 0x7c0006a5
61 #define PPC_INST_XXLOR 0xf0000510
63 #define PPC_INST_NAP 0x4c000364
64 #define PPC_INST_SLEEP 0x4c0003a4
66 /* A2 specific instructions */
67 #define PPC_INST_ERATWE 0x7c0001a6
68 #define PPC_INST_ERATRE 0x7c000166
69 #define PPC_INST_ERATILX 0x7c000066
70 #define PPC_INST_ERATIVAX 0x7c000666
71 #define PPC_INST_ERATSX 0x7c000126
72 #define PPC_INST_ERATSX_DOT 0x7c000127
74 /* Misc instructions for BPF compiler */
75 #define PPC_INST_LD 0xe8000000
76 #define PPC_INST_LHZ 0xa0000000
77 #define PPC_INST_LWZ 0x80000000
78 #define PPC_INST_STD 0xf8000000
79 #define PPC_INST_STDU 0xf8000001
80 #define PPC_INST_MFLR 0x7c0802a6
81 #define PPC_INST_MTLR 0x7c0803a6
82 #define PPC_INST_CMPWI 0x2c000000
83 #define PPC_INST_CMPDI 0x2c200000
84 #define PPC_INST_CMPLW 0x7c000040
85 #define PPC_INST_CMPLWI 0x28000000
86 #define PPC_INST_ADDI 0x38000000
87 #define PPC_INST_ADDIS 0x3c000000
88 #define PPC_INST_ADD 0x7c000214
89 #define PPC_INST_SUB 0x7c000050
90 #define PPC_INST_BLR 0x4e800020
91 #define PPC_INST_BLRL 0x4e800021
92 #define PPC_INST_MULLW 0x7c0001d6
93 #define PPC_INST_MULHWU 0x7c000016
94 #define PPC_INST_MULLI 0x1c000000
95 #define PPC_INST_DIVWU 0x7c0003d6
96 #define PPC_INST_RLWINM 0x54000000
97 #define PPC_INST_RLDICR 0x78000004
98 #define PPC_INST_SLW 0x7c000030
99 #define PPC_INST_SRW 0x7c000430
100 #define PPC_INST_AND 0x7c000038
101 #define PPC_INST_ANDDOT 0x7c000039
102 #define PPC_INST_OR 0x7c000378
103 #define PPC_INST_ANDI 0x70000000
104 #define PPC_INST_ORI 0x60000000
105 #define PPC_INST_ORIS 0x64000000
106 #define PPC_INST_NEG 0x7c0000d0
107 #define PPC_INST_BRANCH 0x48000000
108 #define PPC_INST_BRANCH_COND 0x40800000
110 /* macros to insert fields into opcodes */
111 #define __PPC_RA(a) (((a) & 0x1f) << 16)
112 #define __PPC_RB(b) (((b) & 0x1f) << 11)
113 #define __PPC_RS(s) (((s) & 0x1f) << 21)
114 #define __PPC_RT(s) __PPC_RS(s)
115 #define __PPC_XA(a) ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
116 #define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
117 #define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
118 #define __PPC_XT(s) __PPC_XS(s)
119 #define __PPC_T_TLB(t) (((t) & 0x3) << 21)
120 #define __PPC_WC(w) (((w) & 0x3) << 21)
121 #define __PPC_WS(w) (((w) & 0x1f) << 11)
122 #define __PPC_SH(s) __PPC_WS(s)
123 #define __PPC_MB(s) (((s) & 0x1f) << 6)
124 #define __PPC_ME(s) (((s) & 0x1f) << 1)
125 #define __PPC_BI(s) (((s) & 0x1f) << 16)
127 /*
128 * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
129 * larx with EH set as an illegal instruction.
130 */
131 #ifdef CONFIG_PPC64
132 #define __PPC_EH(eh) (((eh) & 0x1) << 0)
133 #else
134 #define __PPC_EH(eh) 0
135 #endif
137 /* Deal with instructions that older assemblers aren't aware of */
138 #define PPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \
139 __PPC_RA(a) | __PPC_RB(b))
140 #define PPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \
141 __PPC_RA(a) | __PPC_RB(b))
142 #define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LDARX | \
143 __PPC_RT(t) | __PPC_RA(a) | \
144 __PPC_RB(b) | __PPC_EH(eh))
145 #define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \
146 __PPC_RT(t) | __PPC_RA(a) | \
147 __PPC_RB(b) | __PPC_EH(eh))
148 #define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \
149 __PPC_RB(b))
150 #define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_INST_POPCNTB | \
151 __PPC_RA(a) | __PPC_RS(s))
152 #define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_INST_POPCNTD | \
153 __PPC_RA(a) | __PPC_RS(s))
154 #define PPC_POPCNTW(a, s) stringify_in_c(.long PPC_INST_POPCNTW | \
155 __PPC_RA(a) | __PPC_RS(s))
156 #define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI)
157 #define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI)
158 #define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI)
159 #define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \
160 __PPC_T_TLB(t) | __PPC_RA(a) | __PPC_RB(b))
161 #define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b)
162 #define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b)
163 #define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b)
164 #define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \
165 __PPC_WC(w))
166 #define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \
167 __PPC_RB(a) | __PPC_RS(lp))
168 #define PPC_TLBSRX_DOT(a,b) stringify_in_c(.long PPC_INST_TLBSRX_DOT | \
169 __PPC_RA(a) | __PPC_RB(b))
170 #define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \
171 __PPC_RA(a) | __PPC_RB(b))
173 #define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_INST_ERATWE | \
174 __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
175 #define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_INST_ERATRE | \
176 __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
177 #define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_INST_ERATILX | \
178 __PPC_T_TLB(t) | __PPC_RA(a) | \
179 __PPC_RB(b))
180 #define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_INST_ERATIVAX | \
181 __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
182 #define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_INST_ERATSX | \
183 __PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b))
184 #define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \
185 __PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b))
188 /*
189 * Define what the VSX XX1 form instructions will look like, then add
190 * the 128 bit load store instructions based on that.
191 */
192 #define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
193 #define VSX_XX3(t, a, b) (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
194 #define STXVD2X(s, a, b) stringify_in_c(.long PPC_INST_STXVD2X | \
195 VSX_XX1((s), (a), (b)))
196 #define LXVD2X(s, a, b) stringify_in_c(.long PPC_INST_LXVD2X | \
197 VSX_XX1((s), (a), (b)))
198 #define XXLOR(t, a, b) stringify_in_c(.long PPC_INST_XXLOR | \
199 VSX_XX3((t), (a), (b)))
201 #define PPC_NAP stringify_in_c(.long PPC_INST_NAP)
202 #define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP)